ao_mca.c revision 25f476773dea2a0ee593dcf662a38d5f02487196
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * CDDL HEADER START
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a307a2550e1618a7971751ee83c22441ced27bbegavinm * Common Development and Distribution License (the "License").
a307a2550e1618a7971751ee83c22441ced27bbegavinm * You may not use this file except in compliance with the License.
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
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fb2f18f820d90b001aea4fb27dd654bc1263c440esaxe * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * Use is subject to license terms.
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi#pragma ident "%Z%%M% %I% %E% SMI"
20c794b39650d115e17a15983b6b82e46238cf45gavinm#define AO_F_REVS_FG (X86_CHIPREV_AMD_F_REV_F | X86_CHIPREV_AMD_F_REV_G)
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindiint ao_mca_smi_disable = 1; /* attempt to disable SMI polling */
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm uint32_t ctl_revmask; /* rev(s) to which this applies */
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * Additional NB MCA ctl initialization for revs F and G
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecinditypedef struct ao_bank_cfg {
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm const struct ao_ctl_init *bank_ctl_init_extra; /* Extra for each rev */
20c794b39650d115e17a15983b6b82e46238cf45gavinm void (*bank_misc_initfunc)(cmi_hdl_t, ao_ms_data_t *, uint32_t);
20c794b39650d115e17a15983b6b82e46238cf45gavinmstatic void nb_mcamisc_init(cmi_hdl_t, ao_ms_data_t *, uint32_t);
20c794b39650d115e17a15983b6b82e46238cf45gavinm { AMD_DC_CTL_INIT_CMN, NULL, NULL, AMD_MSR_DC_MASK },
20c794b39650d115e17a15983b6b82e46238cf45gavinm { AMD_IC_CTL_INIT_CMN, NULL, NULL, AMD_MSR_IC_MASK },
20c794b39650d115e17a15983b6b82e46238cf45gavinm { AMD_BU_CTL_INIT_CMN, NULL, NULL, AMD_MSR_BU_MASK },
20c794b39650d115e17a15983b6b82e46238cf45gavinm { AMD_LS_CTL_INIT_CMN, NULL, NULL, AMD_MSR_LS_MASK },
20c794b39650d115e17a15983b6b82e46238cf45gavinm { AMD_NB_CTL_INIT_CMN, &ao_nb_ctl_init[0], nb_mcamisc_init,
20c794b39650d115e17a15983b6b82e46238cf45gavinmstatic int ao_nbanks = sizeof (ao_bank_cfgs) / sizeof (ao_bank_cfgs[0]);
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * This is quite awful but necessary to work around x86 system vendor's view of
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * the world. Other operating systems (you know who you are) don't understand
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * Opteron-specific error handling, so BIOS and system vendors often hide these
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * conditions from them by using SMI polling to copy out any errors from the
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * machine-check registers. When Solaris runs on a system with this feature,
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * we want to disable the SMI polling so we can use FMA instead. Sadly, there
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * isn't even a standard self-describing way to express the whole situation,
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * so we have to resort to hard-coded values. This should all be changed to
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * be a self-describing vendor-specific SMBIOS structure in the future.
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindistatic const struct ao_smi_disable {
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi const char *asd_sys_vendor; /* SMB_TYPE_SYSTEM vendor prefix */
4156fc34b973159b0334e05ae5ec19344487bdc0gavinm const char *asd_sys_product; /* SMB_TYPE_SYSTEM product prefix */
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi const char *asd_bios_vendor; /* SMB_TYPE_BIOS vendor prefix */
20c794b39650d115e17a15983b6b82e46238cf45gavinm AO_MCA_R4_BIT_PREFETCH, /* MCAX86_ERRCODE_RRRR_PREFETCH */
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindibit_strip(uint16_t *codep, uint16_t mask, uint16_t shift)
20c794b39650d115e17a15983b6b82e46238cf45gavinm/*ARGSUSED*/
8a40a695ee676a322b094e9afe5375567bfb51e3gavinmao_disp_match_one(const ao_error_disp_t *aed, uint64_t status, uint32_t rev,
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * If the bank's status register indicates overflow, then we can no
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * longer rely on the value of CECC: our experience with actual fault
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * injection has shown that multiple CE's overwriting each other shows
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * AMD_BANK_STAT_CECC and AMD_BANK_STAT_UECC both set to zero. This
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * should be clarified in a future BKDG or by the Revision Guide.
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * This behaviour is fixed in revision F.
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm !X86_CHIPREV_ATLEAST(rev, X86_CHIPREV_AMD_F_REV_F) &&
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi return (0);
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * r4 and pp bits are stored separately, so we mask off and compare them
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * for the code types that use them. Once we've taken the r4 and pp
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * bits out of the equation, we can directly compare the resulting code
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * with the one stored in the ao_error_disp_t.
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi return (0);
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi return (0);
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi return (code == aed->aed_stat_code && extcode == aed->aed_stat_extcode);
20c794b39650d115e17a15983b6b82e46238cf45gavinm/*ARGSUSED*/
20c794b39650d115e17a15983b6b82e46238cf45gavinmao_ms_disp_match(cmi_hdl_t hdl, int banknum, uint64_t status,
20c794b39650d115e17a15983b6b82e46238cf45gavinm for (aed = ao_error_disp[banknum]; aed->aed_stat_mask != 0; aed++) {
20c794b39650d115e17a15983b6b82e46238cf45gavinm/*ARGSUSED*/
20c794b39650d115e17a15983b6b82e46238cf45gavinmao_ms_ereport_class(cmi_hdl_t hdl, cms_cookie_t mscookie,
20c794b39650d115e17a15983b6b82e46238cf45gavinmao_chip_once(ao_ms_data_t *ao, enum ao_cfgonce_bitnum what)
20c794b39650d115e17a15983b6b82e46238cf45gavinm return (atomic_set_long_excl(&ao->ao_ms_shared->aos_cfgonce,
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * This knob exists in case any platform has a problem with our default
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * policy of disabling any interrupt registered in the NB MC4_MISC
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * register. Setting this may cause Solaris and external entities
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * who also have an interest in this register to argue over available
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * telemetry (so setting it is generally not recommended).
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * The BIOS may have setup to receive SMI on counter overflow. It may also
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * have locked various fields or made them read-only. We will clear any
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * SMI request and leave the register locked. We will also clear the
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * counter and enable counting - while we don't use the counter it is nice
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * to have it enabled for verification and debug work.
20c794b39650d115e17a15983b6b82e46238cf45gavinmnb_mcamisc_init(cmi_hdl_t hdl, ao_ms_data_t *ao, uint32_t rev)
20c794b39650d115e17a15983b6b82e46238cf45gavinm if (cmi_hdl_rdmsr(hdl, AMD_MSR_NB_MISC, &val) != CMI_SUCCESS)
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm return; /* stash BIOS value, but no changes */
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * The Valid bit tells us whether the CtrP bit is defined; if it
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * is the CtrP bit tells us whether an ErrCount field is present.
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * If not then there is nothing for us to do.
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm if (!(val & AMD_NB_MISC_VALID) || !(val & AMD_NB_MISC_CTRP))
20c794b39650d115e17a15983b6b82e46238cf45gavinm nval |= AMD_NB_MISC_CNTEN; /* enable ECC error counting */
20c794b39650d115e17a15983b6b82e46238cf45gavinm nval &= ~AMD_NB_MISC_ERRCOUNT_MASK; /* clear ErrCount */
20c794b39650d115e17a15983b6b82e46238cf45gavinm nval &= ~AMD_NB_MISC_INTTYPE_MASK; /* no interrupt on overflow */
bb86c3425be684b7eaa9e875ec2740b39d444ec8gavinm * NorthBridge (NB) MCA Configuration.
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * We add and remove bits from the BIOS-configured value, rather than
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * writing an absolute value. The variables ao_nb_cfg_{add,remove}_cmn and
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * ap_nb_cfg_{add,remove}_revFG are available for modification via kmdb
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * and /etc/system. The revision-specific adds and removes are applied
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * after the common changes, and one write is made to the config register.
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * These are not intended for watchdog configuration via these variables -
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * use the watchdog policy below.
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * Bits to be added to the NB configuration register - all revs.
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * Bits to be cleared from the NB configuration register - all revs.
8a40a695ee676a322b094e9afe5375567bfb51e3gavinmuint32_t ao_nb_cfg_remove_cmn = AMD_NB_CFG_REMOVE_CMN;
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * Bits to be added to the NB configuration register - revs F and G.
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * Bits to be cleared from the NB configuration register - revs F and G.
8a40a695ee676a322b094e9afe5375567bfb51e3gavinmuint32_t ao_nb_cfg_remove_revFG = AMD_NB_CFG_REMOVE_REV_FG;
20c794b39650d115e17a15983b6b82e46238cf45gavinm { AO_F_REVS_FG, &ao_nb_cfg_add_revFG, &ao_nb_cfg_remove_revFG },
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * Bits to be used if we configure the NorthBridge (NB) Watchdog. The watchdog
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * triggers a machine check exception when no response to an NB system access
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * occurs within a specified time interval.
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * The default watchdog policy is to enable it (at the above rate) if it
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * is disabled; if it is enabled then we leave it enabled at the rate
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * chosen by the BIOS.
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm AO_NB_WDOG_LEAVEALONE, /* Don't touch watchdog config */
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm AO_NB_WDOG_ENABLE_IF_DISABLED, /* If disabled, enable at our rate */
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm AO_NB_WDOG_ENABLE_FORCE_RATE /* Enable and set our rate */
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm} ao_nb_watchdog_policy = AO_NB_WDOG_ENABLE_IF_DISABLED;
fb2f18f820d90b001aea4fb27dd654bc1263c440esaxe uint_t chipid = pg_plat_hw_instance_id(CPU, PGHW_CHIP);
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * Read the NorthBridge (NB) configuration register in PCI space,
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * modify the settings accordingly, and store the new value back.
20c794b39650d115e17a15983b6b82e46238cf45gavinm * Note that the stashed BIOS config value aos_bcfg_nb_cfg is used
20c794b39650d115e17a15983b6b82e46238cf45gavinm * in ereport payload population to determine ECC syndrome type for
20c794b39650d115e17a15983b6b82e46238cf45gavinm * memory errors.
bb86c3425be684b7eaa9e875ec2740b39d444ec8gavinm ao_pcicfg_read(chipid, MC_FUNC_MISCCTL, MC_CTL_REG_NBCFG);
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm cmn_err(CE_NOTE, "ao_nb_watchdog_policy=%d unrecognised, "
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm /*FALLTHRU*/
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm break; /* if enabled leave rate intact */
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm /*FALLTHRU*/
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * Now apply bit adds and removes, first those common to all revs
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * and then the revision-specific ones.
bb86c3425be684b7eaa9e875ec2740b39d444ec8gavinm ao_pcicfg_write(chipid, MC_FUNC_MISCCTL, MC_CTL_REG_NBCFG, val);
bb86c3425be684b7eaa9e875ec2740b39d444ec8gavinm uint_t chipid = pg_plat_hw_instance_id(CPU, PGHW_CHIP);
20c794b39650d115e17a15983b6b82e46238cf45gavinm ao->ao_ms_shared->aos_bcfg_dcfg_lo = MCREG_VAL32(&dcfglo) =
bb86c3425be684b7eaa9e875ec2740b39d444ec8gavinm ao_pcicfg_read(chipid, MC_FUNC_DRAMCTL, MC_DC_REG_DRAMCFGLO);
bb86c3425be684b7eaa9e875ec2740b39d444ec8gavinm ao_pcicfg_read(chipid, MC_FUNC_DRAMCTL, MC_DC_REG_DRAMCFGHI);
bb86c3425be684b7eaa9e875ec2740b39d444ec8gavinm ao_pcicfg_write(chipid, MC_FUNC_DRAMCTL, MC_DC_REG_DRAMCFGLO,
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * This knob exists in case any platform has a problem with our default
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * policy of disabling any interrupt registered in the online spare
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * control register. Setting this may cause Solaris and external entities
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * who also have an interest in this register to argue over available
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * telemetry (so setting it is generally not recommended).
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * Setup the online spare control register (revs F and G). We disable
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * any interrupt registered by the BIOS and zero all error counts.
fb2f18f820d90b001aea4fb27dd654bc1263c440esaxe uint_t chipid = pg_plat_hw_instance_id(CPU, PGHW_CHIP);
20c794b39650d115e17a15983b6b82e46238cf45gavinm ao->ao_ms_shared->aos_bcfg_nb_sparectl = MCREG_VAL32(&sparectl) =
bb86c3425be684b7eaa9e875ec2740b39d444ec8gavinm ao_pcicfg_read(chipid, MC_FUNC_MISCCTL, MC_CTL_REG_SPARECTL);
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm return; /* stash BIOS value, but no changes */
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * If the BIOS has requested SMI interrupt type for ECC count
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * overflow for a chip-select or channel force those off.
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * Zero EccErrCnt and write this back to all chan/cs combinations.
20c794b39650d115e17a15983b6b82e46238cf45gavinm MCREG_FIELD_F_revFG(&sparectl, EccErrCntDramChan) = chan;
20c794b39650d115e17a15983b6b82e46238cf45gavinm MCREG_FIELD_F_revFG(&sparectl, EccErrCntDramCs) = cs;
20c794b39650d115e17a15983b6b82e46238cf45gavinmao_ms_error_action(cmi_hdl_t hdl, int ismc, int banknum,
20c794b39650d115e17a15983b6b82e46238cf45gavinm uint64_t status, uint64_t addr, uint64_t misc, void *mslogout)
20c794b39650d115e17a15983b6b82e46238cf45gavinm aed = ao_ms_disp_match(hdl, banknum, status, addr, misc, mslogout);
20c794b39650d115e17a15983b6b82e46238cf45gavinm * If we do not recognise the error let the cpu module apply
20c794b39650d115e17a15983b6b82e46238cf45gavinm * the generic criteria to decide how to react.
20c794b39650d115e17a15983b6b82e46238cf45gavinm return (0);
20c794b39650d115e17a15983b6b82e46238cf45gavinm if ((when = aed->aed_panic_when) == AO_AED_PANIC_NEVER)
20c794b39650d115e17a15983b6b82e46238cf45gavinm * The original AMD implementation would panic on a machine check
20c794b39650d115e17a15983b6b82e46238cf45gavinm * (not a poll) if the status overflow bit was set, with an
20c794b39650d115e17a15983b6b82e46238cf45gavinm * exception for the case of rev F or later with an NB error
20c794b39650d115e17a15983b6b82e46238cf45gavinm * indicating CECC. This came from the perception that the
20c794b39650d115e17a15983b6b82e46238cf45gavinm * overflow bit was not correctly managed on rev E and earlier, for
20c794b39650d115e17a15983b6b82e46238cf45gavinm * example that repeated correctable memeory errors did not set
20c794b39650d115e17a15983b6b82e46238cf45gavinm * OVER but somehow clear CECC.
20c794b39650d115e17a15983b6b82e46238cf45gavinm * We will leave the generic support to evaluate overflow errors
20c794b39650d115e17a15983b6b82e46238cf45gavinm * and decide to panic on their individual merits, e.g., if PCC
20c794b39650d115e17a15983b6b82e46238cf45gavinm * is set and so on. The AMD docs do say (as Intel does) that
20c794b39650d115e17a15983b6b82e46238cf45gavinm * the status information is *all* from the higher-priority
20c794b39650d115e17a15983b6b82e46238cf45gavinm * error in the case of an overflow, so it is at least as serious
20c794b39650d115e17a15983b6b82e46238cf45gavinm * as the original and we can decide panic etc based on it.
20c794b39650d115e17a15983b6b82e46238cf45gavinm * Will need to change for family 0x10
20c794b39650d115e17a15983b6b82e46238cf45gavinmao_ereport_synd(ao_ms_data_t *ao, uint64_t status, uint_t *typep,
20c794b39650d115e17a15983b6b82e46238cf45gavinmao_ereport_create_resource_elem(nv_alloc_t *nva, mc_unum_t *unump, int dimmnum)
20c794b39650d115e17a15983b6b82e46238cf45gavinm if ((nvl = fm_nvlist_create(nva)) == NULL) /* freed by caller */
20c794b39650d115e17a15983b6b82e46238cf45gavinm fm_nvlist_destroy(nvl, nva ? FM_NVA_RETAIN : FM_NVA_FREE);
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi (void) nvlist_add_uint64(snvl, FM_FMRI_HC_SPECIFIC_OFFSET,
20c794b39650d115e17a15983b6b82e46238cf45gavinm fm_fmri_hc_set(nvl, FM_HC_SCHEME_VERSION, NULL, snvl, 5,
52d60c845b4569ed1f136c204372e7e5a3535239gavinm fm_nvlist_destroy(snvl, nva ? FM_NVA_RETAIN : FM_NVA_FREE);
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindiao_ereport_add_resource(nvlist_t *payload, nv_alloc_t *nva, mc_unum_t *unump)
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi for (i = 0; i < MC_UNUM_NDIMM; i++) {
20c794b39650d115e17a15983b6b82e46238cf45gavinm if ((elems[nelems] = ao_ereport_create_resource_elem(nva,
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_RESOURCE,
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi for (i = 0; i < nelems; i++)
52d60c845b4569ed1f136c204372e7e5a3535239gavinm fm_nvlist_destroy(elems[i], nva ? FM_NVA_RETAIN : FM_NVA_FREE);
20c794b39650d115e17a15983b6b82e46238cf45gavinm/*ARGSUSED*/
20c794b39650d115e17a15983b6b82e46238cf45gavinmao_ms_ereport_add_logout(cmi_hdl_t hdl, nvlist_t *ereport,
20c794b39650d115e17a15983b6b82e46238cf45gavinm nv_alloc_t *nva, int banknum, uint64_t status, uint64_t addr,
20c794b39650d115e17a15983b6b82e46238cf45gavinm uint64_t misc, void *mslogout, cms_cookie_t mscookie)
20c794b39650d115e17a15983b6b82e46238cf45gavinm fm_payload_set(ereport, FM_EREPORT_PAYLOAD_NAME_SYND,
20c794b39650d115e17a15983b6b82e46238cf45gavinm fm_payload_set(ereport, FM_EREPORT_PAYLOAD_NAME_SYND_TYPE,
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi DATA_TYPE_STRING, (syndtype == AMD_SYNDTYPE_CHIPKILL ?
20c794b39650d115e17a15983b6b82e46238cf45gavinm AO_AED_F_PHYSICAL) && (status & MSR_MC_STATUS_ADDRV) &&
20c794b39650d115e17a15983b6b82e46238cf45gavinm/*ARGSUSED*/
20c794b39650d115e17a15983b6b82e46238cf45gavinmao_ms_ereport_includestack(cmi_hdl_t hdl, cms_cookie_t mscookie)
20c794b39650d115e17a15983b6b82e46238cf45gavinm return (0);
20c794b39650d115e17a15983b6b82e46238cf45gavinmao_ms_msrinject(cmi_hdl_t hdl, uint_t msr, uint64_t val)
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi/*ARGSUSED*/
20c794b39650d115e17a15983b6b82e46238cf45gavinmao_ms_mcgctl_val(cmi_hdl_t hdl, int nbanks, uint64_t def)
20c794b39650d115e17a15983b6b82e46238cf45gavinmao_ms_bankctl_val(cmi_hdl_t hdl, int banknum, uint64_t def)
20c794b39650d115e17a15983b6b82e46238cf45gavinm if (banknum >= sizeof (ao_bank_cfgs) / sizeof (ao_bank_cfgs[0]))
20c794b39650d115e17a15983b6b82e46238cf45gavinm while (extrap != NULL && extrap->ctl_revmask != X86_CHIPREV_UNKNOWN) {
20c794b39650d115e17a15983b6b82e46238cf45gavinmao_bankstatus_prewrite(cmi_hdl_t hdl, ao_ms_data_t *ao)
20c794b39650d115e17a15983b6b82e46238cf45gavinm if (cmi_hdl_rdmsr(hdl, MSR_AMD_HWCR, &hwcr) != CMI_SUCCESS)
20c794b39650d115e17a15983b6b82e46238cf45gavinmao_bankstatus_postwrite(cmi_hdl_t hdl, ao_ms_data_t *ao)
20c794b39650d115e17a15983b6b82e46238cf45gavinm maskp = mca->ao_mca_bios_cfg.bcfg_bank_mask = kmem_zalloc(nbanks *
20c794b39650d115e17a15983b6b82e46238cf45gavinm * Read the bank ctl mask MSRs, but only as many as we know
20c794b39650d115e17a15983b6b82e46238cf45gavinm * certainly exist - don't calculate the register address.
20c794b39650d115e17a15983b6b82e46238cf45gavinm * Also initialize the MCi_MISC register where required.
20c794b39650d115e17a15983b6b82e46238cf45gavinm (void) cmi_hdl_rdmsr(hdl, ao_bank_cfgs[i].bank_ctl_mask,
bc946ef3d51a883d2aa15b39f2d8b03a119e26casethg * Note that although this cpu module is loaded before the PSMs are
bc946ef3d51a883d2aa15b39f2d8b03a119e26casethg * loaded (and hence before acpica is loaded), this function is
bc946ef3d51a883d2aa15b39f2d8b03a119e26casethg * called from post_startup(), after PSMs are initialized and acpica
bc946ef3d51a883d2aa15b39f2d8b03a119e26casethg * is loaded.
bc946ef3d51a883d2aa15b39f2d8b03a119e26casethg * AcpiGetFirmwareTable works even if ACPI is disabled, so a failure
bc946ef3d51a883d2aa15b39f2d8b03a119e26casethg * here means we weren't able to retreive a pointer to the FADT.
bc946ef3d51a883d2aa15b39f2d8b03a119e26casethg if (AcpiGetFirmwareTable(FADT_SIG, 1, ACPI_LOGICAL_ADDRESSING,
bc946ef3d51a883d2aa15b39f2d8b03a119e26casethg return (-1);
bc946ef3d51a883d2aa15b39f2d8b03a119e26casethg return (0);
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi/*ARGSUSED*/
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * Fetch the System and BIOS vendor strings from SMBIOS and see if they
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * match a value in our table. If so, disable SMI error polling. This
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * is grotesque and should be replaced by self-describing vendor-
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * specific SMBIOS data or a specification enhancement instead.
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi for (asd = ao_smi_disable; asd->asd_sys_vendor != NULL; asd++) {
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi if (strncmp(asd->asd_sys_vendor, si.smbi_manufacturer,
bc946ef3d51a883d2aa15b39f2d8b03a119e26casethg * Look for the SMI_CMD port in the ACPI FADT,
bc946ef3d51a883d2aa15b39f2d8b03a119e26casethg * if the port is 0, this platform doesn't support
bc946ef3d51a883d2aa15b39f2d8b03a119e26casethg * SMM, so there is no SMI error polling to disable.
bc946ef3d51a883d2aa15b39f2d8b03a119e26casethg "favor of Solaris Fault Management for "
bc946ef3d51a883d2aa15b39f2d8b03a119e26casethg "AMD Processors\n");
bc946ef3d51a883d2aa15b39f2d8b03a119e26casethg } else if (rv < 0) {
bc946ef3d51a883d2aa15b39f2d8b03a119e26casethg "for AMD Processors could not disable SMI "
bc946ef3d51a883d2aa15b39f2d8b03a119e26casethg "polling because an error occurred while "
bc946ef3d51a883d2aa15b39f2d8b03a119e26casethg "trying to determine the SMI command port "
bc946ef3d51a883d2aa15b39f2d8b03a119e26casethg "from the ACPI FADT table\n");