ao_cpu.c revision fb2f18f820d90b001aea4fb27dd654bc1263c440
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fb2f18f820d90b001aea4fb27dd654bc1263c440esaxe * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * Use is subject to license terms.
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi#pragma ident "%Z%%M% %I% %E% SMI"
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * AMD Opteron CPU Subroutines
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * The following three tunables are used to determine the scrubbing rates for
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * the D$, L2$, and DRAM hardware scrubbers. The values range from 0x00-0x16
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * as described in BKDG 3.6.6 Scrub Control Register. A value of zero disables
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * the scrubber. Values above zero indicate rates in descending order.
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * The current default values are used on several Sun systems. In the future
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * this code should assign values dynamically based on memory sizing. If you
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * tune these values manually be aware of the following architectural issue:
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * At present, Opteron can only survive certain kinds of multi-bit errors if
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * they are detected by the scrubbers. Therefore in general we want these
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * values tuned as high as possible without impacting workload performance.
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindiuint32_t ao_scrub_rate_dcache = 8; /* 64B every 5.12 us */
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindiuint32_t ao_scrub_rate_l2cache = 9; /* 64B every 10.2 us */
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindiuint32_t ao_scrub_rate_dram = 0xd; /* 64B every 163.8 us */
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindiuint32_t ao_scrub_system; /* debug stash for system's value */
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindiuint32_t ao_scrub_bios; /* debug stash for bios's value */
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindiuint32_t ao_scrub_lo; /* debug stash for system low addr */
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindiuint32_t ao_scrub_hi; /* debug stash for system high addr */
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm AO_SCRUB_BIOSDEFAULT, /* retain system default values */
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi fm_fmri_hc_set(nvl, FM_HC_SCHEME_VERSION, NULL, NULL, 3,
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi "motherboard", 0,
fb2f18f820d90b001aea4fb27dd654bc1263c440esaxe "chip", pg_plat_hw_instance_id(ao->ao_cpu, PGHW_CHIP),
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * Return the maximum scrubbing rate between r1 and r2, where r2 is extracted
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * from the specified 'cfg' register value using 'mask' and 'shift'. If a
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * value is zero, scrubbing is off so return the opposite value. Otherwise
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * the maximum rate is the smallest non-zero value of the two values.
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindiao_scrubber_max(uint32_t r1, uint32_t cfg, uint32_t mask, uint32_t shift)
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * Enable the chip-specific hardware scrubbers for the D$, L2$, and DRAM, and
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * return a boolean value indicating if we enabled the DRAM scrubber. We set
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * the scrubber rate based on a set of tunables defined at the top of the file.
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * The 'base' parameter is the DRAM Base Address for this chip and is used to
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * determine where the scrubber starts. The 'ilen' value is the IntvlEn field
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * from the DRAM configuration indicating the node-interleaving configuration.
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * Where chip-select sparing is available the DRAM scrub address registers
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * must not be modified while a swap is in-progress. This can't happen
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * because we (the amd cpu module) take control of the online spare
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * away from the BIOS when we perform NB configuration and we complete
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * that operation before the memory controller driver loads.
8a40a695ee676a322b094e9afe5375567bfb51e3gavinmao_scrubber_enable(void *data, uint64_t base, uint64_t ilen, int csdiscontig)
fb2f18f820d90b001aea4fb27dd654bc1263c440esaxe chipid_t chipid = pg_plat_hw_instance_id(ao->ao_cpu, PGHW_CHIP);
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * Read the initial scrubber configuration and save it for debugging.
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * If ao_scrub_policy is DEFAULT, return immediately. Otherwise we
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * disable scrubbing activity while we fiddle with the configuration.
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi scrubctl = ao_pcicfg_read(chipid, AMD_NB_FUNC, AMD_NB_REG_SCRUBCTL);
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi ao_pcicfg_write(chipid, AMD_NB_FUNC, AMD_NB_REG_SCRUBCTL, scrubctl);
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * Read the DRAM Scrub Address Low and High registers, clear their
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * address fields, enable sequential-redirect mode, and update the
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * address fields using the specified DRAM Base Address.
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi lo = ao_pcicfg_read(chipid, AMD_NB_FUNC, AMD_NB_REG_SCRUBADDR_LO);
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi hi = ao_pcicfg_read(chipid, AMD_NB_FUNC, AMD_NB_REG_SCRUBADDR_HI);
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi lo |= AMD_NB_SCRUBADDR_MKLO(base) | AMD_NB_SCRUBADDR_LO_SCRUBREDIREN;
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi ao_pcicfg_write(chipid, AMD_NB_FUNC, AMD_NB_REG_SCRUBADDR_LO, lo);
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi ao_pcicfg_write(chipid, AMD_NB_FUNC, AMD_NB_REG_SCRUBADDR_HI, hi);
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi if (ao_scrub_rate_dcache > AMD_NB_SCRUBCTL_RATE_MAX) {
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi cmn_err(CE_WARN, "ao_scrub_rate_dcache is too large; "
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi if (ao_scrub_rate_l2cache > AMD_NB_SCRUBCTL_RATE_MAX) {
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi cmn_err(CE_WARN, "ao_scrub_rate_l2cache is too large; "
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm /* Use the system values checked above */
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm cmn_err(CE_WARN, "Unknown ao_scrub_policy value %d - "
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm "using default policy of AO_SCRUB_MAX", ao_scrub_policy);
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm /*FALLTHRU*/
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi AMD_NB_SCRUBCTL_DRAM_MASK, AMD_NB_SCRUBCTL_DRAM_SHIFT);
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * This erratum applies on revisions D and earlier.
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * Do not enable the dram scrubber is the chip-select ranges
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * for the node are not contiguous.
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm if (csdiscontig && !X86_CHIPREV_ATLEAST(rev, X86_CHIPREV_AMD_F_REV_E)) {
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm cmn_err(CE_CONT, "?Opteron DRAM scrubber disabled on revision "
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm "%s chip because DRAM hole is present on this node",
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm * This erratum applies on revisions D and earlier.
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * If the DRAM Base Address register's IntlvEn field indicates that
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * node interleaving is enabled, we must disable the DRAM scrubber
7aec1d6e253b21f9e9b7ef68b4d81ab9859b51fecindi * and return zero to indicate that Solaris should use s/w instead.
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm !X86_CHIPREV_ATLEAST(rev, X86_CHIPREV_AMD_F_REV_E)) {
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm cmn_err(CE_CONT, "?Opteron DRAM scrubber disabled on revision "
8a40a695ee676a322b094e9afe5375567bfb51e3gavinm "%s chip because DRAM memory is node-interleaved",