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843e19887f64dde75055cf8842fc4db2171eff45johnlev * DEALINGS IN THE SOFTWARE.
a576ab5b6e08c47732b3dedca9eaa8a8cbb85720rab * Parameter space for HVMOP_{set,get}_param.
a576ab5b6e08c47732b3dedca9eaa8a8cbb85720rab * How should CPU0 event-channel notifications be delivered?
a576ab5b6e08c47732b3dedca9eaa8a8cbb85720rab * val[63:56] == 0: val[55:0] is a delivery GSI (Global System Interrupt).
a576ab5b6e08c47732b3dedca9eaa8a8cbb85720rab * val[63:56] == 1: val[55:0] is a delivery PCI INTx line, as follows:
a576ab5b6e08c47732b3dedca9eaa8a8cbb85720rab * Domain = val[47:32], Bus = val[31:16],
a576ab5b6e08c47732b3dedca9eaa8a8cbb85720rab * DevFn = val[15: 8], IntX = val[ 1: 0]
a576ab5b6e08c47732b3dedca9eaa8a8cbb85720rab * If val == 0 then CPU0 event-channel notifications are not delivered.
a576ab5b6e08c47732b3dedca9eaa8a8cbb85720rab * These are not used by Xen. They are here for convenience of HVM-guest
a576ab5b6e08c47732b3dedca9eaa8a8cbb85720rab * xenbus implementations.
349b53dd4e695e3d833b5380540385145b2d3ae8Stuart Maybee/* Expose Viridian interfaces to this HVM guest? */
349b53dd4e695e3d833b5380540385145b2d3ae8Stuart Maybee * Set mode for virtual timers (currently x86 only):
349b53dd4e695e3d833b5380540385145b2d3ae8Stuart Maybee * delay_for_missed_ticks (default):
349b53dd4e695e3d833b5380540385145b2d3ae8Stuart Maybee * Do not advance a vcpu's time beyond the correct delivery time for
349b53dd4e695e3d833b5380540385145b2d3ae8Stuart Maybee * interrupts that have been missed due to preemption. Deliver missed
349b53dd4e695e3d833b5380540385145b2d3ae8Stuart Maybee * interrupts when the vcpu is rescheduled and advance the vcpu's virtual
349b53dd4e695e3d833b5380540385145b2d3ae8Stuart Maybee * time stepwise for each one.
349b53dd4e695e3d833b5380540385145b2d3ae8Stuart Maybee * no_delay_for_missed_ticks:
349b53dd4e695e3d833b5380540385145b2d3ae8Stuart Maybee * As above, missed interrupts are delivered, but guest time always tracks
349b53dd4e695e3d833b5380540385145b2d3ae8Stuart Maybee * wallclock (i.e., real) time while doing so.
349b53dd4e695e3d833b5380540385145b2d3ae8Stuart Maybee * no_missed_ticks_pending:
349b53dd4e695e3d833b5380540385145b2d3ae8Stuart Maybee * No missed interrupts are held pending. Instead, to ensure ticks are
349b53dd4e695e3d833b5380540385145b2d3ae8Stuart Maybee * delivered at some non-zero rate, if we detect missed ticks then the
349b53dd4e695e3d833b5380540385145b2d3ae8Stuart Maybee * internal tick alarm is not disabled if the VCPU is preempted during the
349b53dd4e695e3d833b5380540385145b2d3ae8Stuart Maybee * next tick period.
349b53dd4e695e3d833b5380540385145b2d3ae8Stuart Maybee * one_missed_tick_pending:
349b53dd4e695e3d833b5380540385145b2d3ae8Stuart Maybee * Missed interrupts are collapsed together and delivered as one 'late tick'.
349b53dd4e695e3d833b5380540385145b2d3ae8Stuart Maybee * Guest time always tracks wallclock (i.e., real) time.
349b53dd4e695e3d833b5380540385145b2d3ae8Stuart Maybee/* Boolean: Enable virtual HPET (high-precision event timer)? (x86-only) */
349b53dd4e695e3d833b5380540385145b2d3ae8Stuart Maybee/* Identity-map page directory used by Intel EPT when CR0.PG=0. */
349b53dd4e695e3d833b5380540385145b2d3ae8Stuart Maybee/* Device Model domain, defaults to 0. */
349b53dd4e695e3d833b5380540385145b2d3ae8Stuart Maybee/* ACPI S state: currently support S0 and S3 on x86. */
ad09f8b827db90c9a0093f0b6382803fa64a5fd1Mark Johnson/* TSS used on Intel when CR0.PE=0. */
ad09f8b827db90c9a0093f0b6382803fa64a5fd1Mark Johnson/* Boolean: Enable aligning all periodic vpts to reduce interrupts */
843e19887f64dde75055cf8842fc4db2171eff45johnlev#endif /* __XEN_PUBLIC_HVM_PARAMS_H__ */