ehcid.h revision 9b58c2ad19d1f06f07604b0f61b7ff38f757c8fa
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_USB_EHCID_H
#define _SYS_USB_EHCID_H
#ifdef __cplusplus
extern "C" {
#endif
/*
* Enchanced Host Controller Driver (EHCI)
*
* The EHCI driver is a software driver which interfaces to the Universal
* Serial Bus layer (USBA) and the Host Controller (HC). The interface to
* the Host Controller is defined by the EHCI Host Controller Interface.
*
* This header file describes the data structures and function prototypes
* required for the EHCI Driver to maintain state of Host Controller (HC),
* to perform different USB transfers and for the bandwidth allocations.
*/
/*
* EHCI Bandwidth Maintainence Structure.
*
* The ehci_bandwidth array keeps track of allocated bandwidth for ehci
* host controller. There are 32 bandwidth lists corresponding to 32 ms
* periodic frame lists. Each bandwidth list inturn will contain eight
* micro frame bandwidth lists.
*/
typedef struct ehci_frame_bandwidth {
/*
* EHCI Host Controller state structure
*
* The Host Controller Driver (HCD) maintains the state of Host Controller
* (HC). There is an ehci_state structure per instance of the EHCI
* host controller.
*/
typedef struct ehci_state {
int ehci_intr_type; /* intr type used */
int ehci_intr_cnt; /* # of intrs inuse */
int ehci_intr_cap; /* intr capabilities */
/* Periodic Frame List area */
/* Virtual Periodic Frame List ptr */
/*
* There are two pools of memory. One pool contains the memory for
* the transfer descriptors and other pool contains the memory for
* the endpoint descriptors. The advantage of the pools is that it's
* easy to go back and forth between the iommu and the cpu addresses.
*
* The pools are protected by the ehci_int_mutex because the memory
* in the pools may be accessed by either the host controller or the
* host controller driver.
*/
/* Endpoint descriptor pool */
/* General transfer descriptor pool */
/* Isochronous transfer descriptor pool */
/* Condition variable for advance on Asynchronous Schedule */
/* Head of Asynchronous Schedule List */
/*
* List of QTD inserted either into Asynchronous or Periodic
* Schedule lists.
*/
/*
* List of ITD active itd list.
*/
/*
* Bandwidth fields
*
* The ehci_bandwidth array keeps track of allocated bandwidth for
* ehci host controller. There are 32 bandwidth lists corresponding
* to 32 ms periodic frame lists. Each bandwidth list in turn will
* contain eight micro frame bandwidth lists.
*
* ehci_min_frame_bandwidth field indicates least allocated milli
* second bandwidth list.
*/
/* No. of open pipes, async qh, and periodic qh */
/*
* Endpoint Reclamation List
*
* The interrupt list processing cannot be stopped when a periodic
* endpoint is removed from the list. The endpoints are detached
* from the interrupt lattice tree and put on to the reclaimation
* list. On next SOF interrupt all those endpoints, which are on
* the reclaimation list will be deallocated.
*/
/* Frame number overflow information */
/* For host controller error counter */
/*
* ehci_missed_intr_sts is used to save the normal mode interrupt
* status information if an interrupt is pending for normal mode
* when polled code is entered.
*/
/*
* Saved copy of the ehci registers of the normal mode & change
* required ehci registers values for the polled mode operation.
* Before returning from the polled mode to normal mode replace
* the required current registers with this saved ehci registers
* copy.
*/
/*
* Saved copy of the interrupt table used in normal ehci mode and
* replace this table by another interrupt table that used in the
* POLLED mode.
*/
/* ehci polled mode enter counter */
/*
* counter for polled mode and used in suspend mode to see if
* there is a keyboard connected.
*/
/* counter for polled read and use it to clean the interrupt status */
#if defined(__x86)
/* counter for polled root hub status */
#endif /* __x86 */
/* EHCI Host Controller Software State information */
/* Log handle for debug, console, log messages */
/* Kstat structures */
} ehci_state_t;
typedef struct ehci_intrs_stats {
struct kstat_named ehci_sts_host_ctrl_halted;
struct kstat_named ehci_sts_usb_error_intr;
struct kstat_named ehci_sts_usb_intr;
struct kstat_named ehci_sts_not_claimed;
struct kstat_named ehci_sts_total;
/*
* ehci kstat defines
*/
#define EHCI_INTRS_STATS_DATA(ehci) \
#define EHCI_CTRL_STATS(ehci) \
#define EHCI_BULK_STATS(ehci) \
#define EHCI_INTR_STATS(ehci) \
#define EHCI_ISOC_STATS(ehci) \
/* warlock directives, stable data */
/* this may not be stable data in the future */
/*
* Host Contoller Software States
*
* EHCI_CTLR_INIT_STATE:
* The host controller soft state will be set to this during the
* ehci_attach.
*
* EHCI_CTLR_SUSPEND_STATE:
* The host controller soft state will be set to this during the
* ehci_cpr_suspend.
*
* EHCI_CTLR_OPERATIONAL_STATE:
* The host controller soft state will be set to this after moving
* host controller to operational state and host controller start
* generating SOF successfully.
*
* EHCI_CTLR_ERROR_STATE:
* The host controller soft state will be set to this during the
* no SOF or UE error conditions.
*
* Under this state or condition, only pipe stop polling, pipe reset
* and pipe close are allowed. But all other entry points like pipe
*
* State Diagram for the host controller software state
*
*
* ehci_attach->[INIT_STATE]
* |
* | -------->----[ERROR_STATE]--<-----------<---
* | ^ ^
* V | Success |
* ^ |
* | |
* | V
* -<-ehci_cpr_resume--[SUSPEND_STATE]-<-ehci_cpr_suspend
*/
#define EHCI_CTLR_INIT_STATE 0 /* Initilization state */
/*
* Flags for initializatoin of host controller
*/
#define EHCI_NORMAL_INITIALIZATION 0 /* Normal initialization */
/*
* Periodic and non-periodic macros
*/
USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) ||\
((endpoint->bmAttributes &\
USB_EP_ATTR_MASK) == USB_EP_ATTR_CONTROL) ||\
((endpoint->bmAttributes &\
/*
* EHCI QH and QTD Pool sizes.
*/
#define EHCI_QH_POOL_SIZE 100
#define EHCI_QTD_POOL_SIZE 200
#define EHCI_ITD_POOL_SIZE 200
/*
* ehci_dma_addr_bind_flag values
*
* This flag indicates if the various DMA addresses allocated by the EHCI
* have been bound to their respective handles. This is needed to recover
* without errors from ehci_cleanup when it calls ddi_dma_unbind_handle()
*/
/*
* Maximum SOF wait count
*/
/*
* One uFrame 125 micro seconds
* One Frame 1 milli second or 8 uFrames
*/
#define EHCI_uFRAMES_PER_USB_FRAME 8
#define EHCI_uFRAMES_PER_USB_FRAME_SHIFT 3
/*
* Pipe private structure
*
* There is an instance of this structure per pipe. This structure holds
* HCD specific pipe information. A pointer to this structure is kept in
* the USBA pipe handle (usba_pipe_handle_data_t).
*/
typedef struct ehci_pipe_private {
/* State of the pipe */
/* Local copy of the pipe policy */
/* For Periodic Pipes Only */
/* For Isochronous pipes only */
/*
* Each pipe may have multiple transfer wrappers. Each transfer
* wrapper represents a USB transfer on the bus. A transfer is
* made up of one or more transactions.
*/
/*
* Pipe's transfer timeout handling & this transfer timeout handling
* will be per pipe.
*/
/* Done td count */
/* Errors */
/* Condition variable for transfers completion event */
/* Pipe flag */
/* Halting States */
/* Condition variable for halt completion event */
/*
* HCD gets Interrupt/Isochronous IN polling request only once and
* it has to insert next polling requests after completion of first
* has to take copy of the original Interrupt/Isochronous IN request.
*/
/*
* Pipe states
*
* ehci pipe states will be similar to usba. Refer usbai.h.
*/
/* Additional ehci pipe states for the ehci_pipe_cleanup */
/*
* Pipe flag
*
* For polled mode flag.
*/
/* Pipe specific flags */
/*
* Halting States
* prevent halting from interleaving.
*/
#define EHCI_HALT_STATE_FREE 0 /* Pipe free to accept reqs */
/*
* Request values for Clear_TT_Buffer
*/
#define EHCI_CLEAR_TT_BUFFER_REQTYPE (USB_DEV_REQ_TYPE_CLASS | \
#define EHCI_CLEAR_TT_BUFFER_BREQ 8
/*
* USB frame offset
*
* Add appropriate frame offset to the current usb frame number and use it
* as a starting frame number for a given usb isochronous request.
*/
/*
* Different interrupt polling intervals supported for high speed
* devices and its range must be from 1 to 16 units. This value is
* used as th exponent for a 2 ^ (bInterval - 1). Ex: a Binterval
* of 4 means a period of 8us (2 ^ (4-1)).
*
* The following values are defined after above convertion in terms
* 125us units.
*/
/*
* The following indecies are are used to calculate Start and complete
* masks as per the polling interval.
*/
#define EHCI_XUS_MASK_INDEX 0 /* 8us and above */
/*
* speed devices. For high speed devices, the following values are
* applicable after convertion.
*/
/*
* Number of interrupt transfer requests that should be maintained on
* the interrupt endpoint corresponding to different polling intervals
* supported.
*/
/* Function prototype */
typedef void (*ehci_handler_function_t)(
struct ehci_trans_wrapper *tw,
void *ehci_handle_callback_value);
/*
* Transfer wrapper
*
* The transfer wrapper represents a USB transfer on the bus and there
* is one instance per USB transfer. A transfer is made up of one or
* more transactions. EHCI uses one QTD for one transaction. So one
* transfer wrapper may have one or more QTDs associated.
*
* The data to be transferred are contained in the TW buffer which is
* virtually contiguous but physically discontiguous. When preparing
* the QTDs for a USB transfer, the DMA cookies corresponding to the
* TW buffer need to be walked through to retrieve the DMA addresses.
*
* Control and bulk pipes will have one transfer wrapper per transfer
* and where as Isochronous and Interrupt pipes will only have one
* transfer wrapper. The transfers wrapper are continually reused for
* the Interrupt and Isochronous pipes as those pipes are polled.
*/
typedef struct ehci_trans_wrapper {
char *tw_buf; /* Buffer for Xfer */
/* Current transfer request pointer */
/* Transfer timeout information */
int tw_timeout; /* Timeout value */
/*
* This is the function to call when this td is done. This way
* we don't have to look in the td to figure out what kind it is.
*/
/*
* This is the callback value used when processing a done td.
*/
/* We preallocate all the td's for each tw and place them here */
/*
* Isochronous Transfer Wrapper
*
* isochronous transfers. A transfer wrapper consists of one or more
* transactionsl, but there is one one instance per USB transfer request.
*
* The isochrnous transfer wrapper are continiously reused because these
* pipes are polled.
*/
typedef struct ehci_isoc_xwrapper {
/* DMA and memory pointers */
/* Transfer information */
char *itw_buf; /* Buffer for Xfer */
/* ITD information */
/* We preallocate all the td's for each tw and place them here */
/* Device and hub information needed by every iTD */
/*
* Callback handling function and arguement. Called when an iTD is
* is done.
*/
/* 32bit ID */
/*
* Time waits for the different EHCI specific operations.
* These timeout values are specified in terms of microseconds.
*/
/* These timeout values are specified in seconds */
/* EHCI flags for general use */
/*
* Maximum allowable data transfer size per transaction as supported
* by EHCI is 20k. (See EHCI Host Controller Interface Spec Rev 0.96)
*
* Also within QTD, there will be five buffer pointers abd each buffer
* pointer can transfer upto 4k bytes of data.
*/
/*
* The maximum allowable bulk data transfer size. It can be different
* from EHCI_MAX_QTD_XFER_SIZE and if it is more then ehci driver will
* take care of breaking a bulk data request into multiples of ehci
* EHCI_MAX_QTD_XFER_SIZE until request is satisfied. Currently this
* value is set to 640k bytes.
*/
/*
* Timeout flags
*
* These flags will be used to stop the timer before timeout handler
* gets executed.
*/
/*
* High speed bandwidth allocation
*
* The following definitions are used during bandwidth calculations
* for a given high speed endpoint or high speed split transactions.
*/
/*
* As per USB 2.0 specification section 5.5.4, 20% of bus time is reserved
* for the non-periodic high-speed transfers. Where as peridoic high-speed
* transfers will get 80% of the bus time. In one micro-frame or 125us, we
* can transfer 7500 bytes or 60,000 bits.
*/
#define HS_NON_PERIODIC_BANDWIDTH 1500
/*
* High speed periodic frame bandwidth will be eight times the micro frame
* high speed periodic bandwidth.
*/
/*
* The following are the protocol overheads in terms of Bytes for the
* different transfer types. All these protocol overhead values are
* derived from the 5.11.3 section of USB 2.0 Specification.
*/
#define HS_NON_ISOC_PROTO_OVERHEAD 55
#define HS_ISOC_PROTO_OVERHEAD 38
/*
* The following are THE protocol overheads in terms of Bytes for the
* start and complete split transactions tokens overheads. All these
* protocol overhead values are derived from the 8.4.2.2 and 8.4.2.3
* of USB2.0 Specification.
*/
#define START_SPLIT_OVERHEAD 04
#define COMPLETE_SPLIT_OVERHEAD 04
/*
* The Host Controller (HC) delays are the USB host controller specific
* delays. The value shown below is the host controller delay for the
* given EHCI host controller.
*/
#define EHCI_HOST_CONTROLLER_DELAY 18
/*
*
* The following definitions are used during bandwidth calculations for
* a given high speed hub or a transaction translator (TT) and for a
* split transactions
*/
/*
* Minimum polling interval for low speed endpoint
*
* According USB 2.0 Specification, a full-speed endpoint can specify
* a desired polling interval 1ms to 255ms and a low speed endpoints
* are limited to specifying only 10ms to 255ms. But some old keyboards
* and mice uses polling interval of 8ms. For compatibility purpose,
* we are using polling interval between 8ms and 255ms for low speed
* endpoints. The ehci driver will use 8ms polling interval if a low
* speed device reports a polling interval that is less than 8ms.
*/
/*
* For non-periodic transfers, reserve atleast for one low-speed device
* transaction. According to USB Bandwidth Analysis white paper and also
* as per OHCI Specification 1.0a, section 7.3.5, page 123, one low-speed
* transaction takes 0x628h full speed bits (197 bytes), which comes to
* around 13% of USB frame time.
*
* The periodic transfers will get around 87% of USB frame time.
*/
#define FS_NON_PERIODIC_BANDWIDTH 197
/*
* The following are the protocol overheads in terms of Bytes for the
* different transfer types. All these protocol overhead values are
* derived from the 5.11.3 section of USB Specification and with the
* help of Bandwidth Analysis white paper which is posted on the USB
* developer forum.
*/
#define FS_NON_ISOC_PROTO_OVERHEAD 14
#define FS_ISOC_INPUT_PROTO_OVERHEAD 11
#define FS_ISOC_OUTPUT_PROTO_OVERHEAD 10
#define LOW_SPEED_PROTO_OVERHEAD 97
#define HUB_LOW_SPEED_PROTO_OVERHEAD 01
/* The maximum amount of isoch data that can be transferred in one uFrame */
#define MAX_UFRAME_SITD_XFER 188
/*
* The low speed clock below represents that to transmit one low-speed
* bit takes eight times more than one full speed bit time.
*/
#define LOW_SPEED_CLOCK 8
/*
* The Transaction Translator (TT) delay is the additional time needed
*/
#define TT_DELAY 18
/*
*/
(val))
#define EHCI_MAX_RETRY 10
if (r >= EHCI_MAX_RETRY) \
break; \
r++; \
}
0, EHCI_QH_POOL_SIZE * sizeof (ehci_qh_t), \
(void) ddi_dma_sync( \
0, EHCI_QTD_POOL_SIZE * sizeof (ehci_qtd_t), \
0, EHCI_ITD_POOL_SIZE * sizeof (ehci_itd_t), \
(void) ddi_dma_sync(dma_handle, \
0, length, DDI_DMA_SYNC_FORCPU);
(void) ddi_dma_sync(dma_handle, \
0, length, DDI_DMA_SYNC_FORDEV);
/*
* Macros to speed handling of 32bit IDs
*/
#define EHCI_LOOKUP_ID(x) id32_lookup((x))
#define EHCI_FREE_ID(x) id32_free((x))
/*
* Miscellaneous definitions.
*/
/* Data toggle bits */
#define DATA0 0
#define DATA1 1
/* Halt bit actions */
#define CLEAR_HALT 0
#define SET_HALT 1
typedef uint_t halt_bit_t;
/*
* Setup Packet
*/
typedef struct setup_pkt {
#define REQUEST_TYPE_OFFSET 0
#define REQUEST_OFFSET 1
#define VALUE_OFFSET 2
#define INDEX_OFFSET 4
#define LENGTH_OFFSET 6
#define TYPE_DEV_TO_HOST 0x80000000
#define DEVICE 0x00000001
#define CONFIGURATION 0x00000002
/*
* The following are used in attach to indicate
* what has been succesfully allocated, so detach
* can remove them.
*/
/*
* This variable is used in the EHCI_FLAGS to tell the ISR to broadcase
* the ehci_async_schedule_advance_cv when an intr occurs. It is used to
* make sure that EHCI is receiving interrupts.
*/
/*
* Debug printing
* Masks
*/
#define PRINT_MASK_ALL 0xFFFFFFFF
#define PCI_DEVICE_NVIDIA_CK804 0x5b
#define PCI_DEVICE_NVIDIA_MCP04 0x3c
/*
* workaround for ALI chips
*/
/*
* NEC on COMBO and Uli M1575 can support PM
*/
#define PCI_VENDOR_NEC_COMBO 0x1033
#define PCI_DEVICE_NEC_COMBO 0xe0
#define PCI_VENDOR_ULi_M1575 0x10b9
#define PCI_DEVICE_ULi_M1575 0x5239
/*
* VIA chips have some problems, the workaround can ensure those chips
* work reliably. Revisions >= 0x80 are part of a southbridge and appear
* to be reliable.
*/
#define EHCI_VIA_LOST_INTERRUPTS 0x01
#define EHCI_VIA_ASYNC_SCHEDULE 0x02
#define EHCI_VIA_REDUCED_MAX_BULK_XFER_SIZE 0x04
#define EHCI_VIA_WORKAROUNDS \
/*
* EHCI HCDI entry points
*
* The Host Controller Driver Interfaces (HCDI) are the software interfaces
* between the Universal Serial Bus Driver (USBA) and the Host Controller
* Driver (HCD). The HCDI interfaces or entry points are subject to change.
*/
int ehci_hcdi_pipe_open(
int ehci_hcdi_pipe_close(
int ehci_hcdi_pipe_reset(
/*
* EHCI Polled entry points function prototypes.
*/
/*
* EHCI Root Hub entry points function prototypes.
*/
int ehci_init_root_hub(
/*
* EHCI Interrupt Handler entry point.
*/
#ifdef __cplusplus
}
#endif
#endif /* _SYS_USB_EHCID_H */