sff_frames.h revision ac88567a7a5bb7f01cf22cf366bc9d6203e24d7a
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
*/
#ifndef _SYS_SCSI_GENERIC_SFF_FRAMES_H
#define _SYS_SCSI_GENERIC_SFF_FRAMES_H
#ifdef __cplusplus
extern "C" {
#endif
#include <sys/sysmacros.h>
/*
* The definitions of SMP frame formats defined by SFF-8485.
* formats, but the function numbers and result codes are defined by SAS-2.
*/
#pragma pack(1)
typedef struct sff_request_frame {
typedef struct sff_response_frame {
/*
* SFF-8485 8.4.1 GPIO register overview
*/
typedef enum sff_gpio_reg_type {
SFF_GPIO_CFG = 0x00,
SFF_GPIO_RX = 0x01,
SFF_GPIO_RX_GP = 0x02,
SFF_GPIO_TX = 0x03,
SFF_GPIO_TX_GP = 0x04
/*
* SFF-8485 8.4.2.1 GPIO configuration registers overview
*/
typedef enum sff_gpio_cfg_reg_index {
SFF_GPIO_CFG_0 = 0x00,
SFF_GPIO_CFG_1 = 0x01
/*
* SFF-8485 8.4.2.2 GPIO_CFG[0] register
*/
typedef struct sff_gpio_cfg_reg_0 {
sgcr0_version :4,
_reserved2 :4);
sgcr0_gpio_enable :1);
/*
* SFF-8485 8.4.2.3 GPIO_CFG[1] register
*/
typedef struct sff_gpio_cfg_reg_1 {
/*
* SFF-8485 8.4.3 GPIO receive registers
*/
typedef struct sff_gpio_rx_reg {
_reserved1 :5);
_reserved1 :5);
_reserved1 :5);
_reserved1 :5);
/*
* SFF-8485 8.4.4 GPIO transmit registers
*/
typedef enum sff_drive_error {
SFF_DRIVE_ERR_DISABLE = 0x0,
SFF_DRIVE_ERR_ENABLE = 0x1,
SFF_DRIVE_ERR_BLINK_A_1_0 = 0x2,
SFF_DRIVE_ERR_BLINK_A_0_1 = 0x3,
SFF_DRIVE_ERR_ENABLE_4 = 0x4,
SFF_DRIVE_ERR_ENABLE_5 = 0x5,
SFF_DRIVE_ERR_BLINK_B_1_0 = 0x6,
typedef enum sff_drive_locate {
SFF_DRIVE_LOC_DISABLE = 0x0,
SFF_DRIVE_LOC_ENABLE = 0x1,
SFF_DRIVE_BLINK_A_1_0 = 0x2,
SFF_DRIVE_BLINK_A_0_1 = 0x3
typedef enum sff_drive_activity {
SFF_DRIVE_ACT_DISABLE = 0x0,
SFF_DRIVE_ACT_ENABLE = 0x1,
SFF_DRIVE_ACT_BLINK_A_1_0 = 0x2,
SFF_DRIVE_ACT_BLINK_A_0_1 = 0x3,
SFF_DRIVE_ACT_ENABLE_END = 0x4,
SFF_DRIVE_ACT_ENABLE_START = 0x5,
SFF_DRIVE_ACT_BLINK_B_1_0 = 0x6,
typedef struct sff_gpio_tx_reg {
/*
* SFF-8485 8.4.5.1 GPIO general purpose receive registers overview
*/
typedef enum sff_gpio_rx_gp_reg_index {
SFF_GPIO_REG_RX_GP_CFG = 0x00,
/*
* SFF-8485 8.4.5.2 GPIO_RX_GP_CFG register
*/
typedef struct sff_gpio_rx_gp_cfg_reg {
/*
* SFF-8485 8.4.5.3 GPIO_RX_GP[1..n] register
*/
/*
* SFF-8485 8.4.6.1 GPIO general purpose transmit registers overview
*/
typedef enum sff_gpio_tx_gp_reg_index {
SFF_GPIO_REG_TX_GP_CFG = 0x00,
/*
* SFF-8485 8.4.6.2 GPIO_TX_GP_CFG register
*/
typedef struct sff_gpio_tx_cfg_reg {
sgtcr_sload_0 :1,
sgtcr_sload_1 :1,
sgtcr_sload_2 :1,
sgtcr_sload_3 :1,
_reserved2 :4);
/*
* SFF-8485 8.4.6.3 GPIO_TX_GP[1..n] registers
*/
/*
* SFF-8485 8.2.2 READ GPIO REGISTER request
*/
typedef struct sff_read_gpio_req {
/*
* SFF-8485 8.2.2 READ GPIO REGISTER response
*/
typedef struct sff_read_gpio_resp {
/*
* SFF-8485 8.2.3 WRITE GPIO REGISTER request (no additional response)
*/
typedef struct sff_write_gpio_req {
#pragma pack()
#ifdef __cplusplus
}
#endif
#endif /* _SYS_SCSI_GENERIC_SFF_FRAMES_H */