4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh * CDDL HEADER START
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4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
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4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh * CDDL HEADER END
c280a92b706bf16eee2a24cc328c9b78d71cb38cDavid Hollister * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh * Use is subject to license terms.
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh * PMC 8x6G Message Passing Interface Definitions
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dhextern "C" {
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh * MPI Configuration Table Offsets
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh#define PMCS_FW_VERSION(maj, min, mic) ((maj << 16)|(min << 8)|mic)
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh#define PMCS_MPI_MOIO PMCS_DWRD(3) /* Maximum # of outstandiong I/Os */
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh#define PMCS_MPI_INFO0 PMCS_DWRD(4) /* Maximum S/G Elem, Max Dev Handle */
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh#define PMCS_MNIQ(x) (x & 0xff) /* Max # of Inbound Queues */
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh#define PMCS_MNOQ(x) ((x >> 8) & 0xff) /* Max # of Outbound Queues */
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh#define PMCS_HPIQ(x) ((x >> 16) & 0x1) /* High Pri Queue Supported */
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh#define PMCS_ICS(x) ((x >> 18) & 0x1) /* Interrupt Coalescing */
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh#define PMCS_NPHY(x) ((x >> 19) & 0x3f) /* Numbers of PHYs */
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh#define PMCS_SASREV(x) ((x >> 25) & 0x7) /* SAS Revision Specification */
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh#define PMCS_MPI_GSTO PMCS_DWRD(6) /* General Status Table Offset */
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh#define PMCS_MPI_IQCTO PMCS_DWRD(7) /* Inbound Queue Config Table Offset */
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh#define PMCS_MPI_OQCTO PMCS_DWRD(8) /* Outbound Queue Config Table Offset */
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh#define PMCS_MPI_EVQS PMCS_DWRD(0xA) /* SAS Event Queues */
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh uint32_t tmp = pmcs_rd_mpi_tbl(pwp, PMCS_MPI_EVQS + (woff << 2)); \
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh pmcs_wr_mpi_tbl(pwp, PMCS_MPI_EVQS + (woff << 2), tmp); \
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh#define PMCS_MPI_SNCQ PMCS_DWRD(0xC) /* Sata NCQ Notification Queues */
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh uint32_t tmp = pmcs_rd_mpi_tbl(pwp, PMCS_MPI_SNCQ + (woff << 2)); \
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh pmcs_wr_mpi_tbl(pwp, PMCS_MPI_SNCQ + (woff << 2), tmp); \
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh * I_T Nexus Target Event Notification Queue
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh * SSP Target Event Notification Queue
c280a92b706bf16eee2a24cc328c9b78d71cb38cDavid Hollister * I/O Abort Delay
c280a92b706bf16eee2a24cc328c9b78d71cb38cDavid Hollister * Customization Setting
c280a92b706bf16eee2a24cc328c9b78d71cb38cDavid Hollister#define PMCS_MPI_CUST_HW_RSC_BSY_ALT 0x1 /* Bit 0 */
c280a92b706bf16eee2a24cc328c9b78d71cb38cDavid Hollister#define PMCS_MPI_CUST_ABORT_ITNL 0x2 /* Bit 1 */
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh * This specifies a log buffer in host memory for the MSGU.
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh#define PMCS_MPI_MELBAH PMCS_DWRD(0x14) /* MSGU Log Buffer high 32 bits */
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh#define PMCS_MPI_MELBAL PMCS_DWRD(0x15) /* MSGU Log Buffer low 32 bits */
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh#define PMCS_MPI_MELBS PMCS_DWRD(0x16) /* size in bytes of MSGU log buffer */
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh#define PMCS_MPI_MELSEV PMCS_DWRD(0x17) /* Log Severity */
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh * This specifies a log buffer in host memory for the IOP.
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh#define PMCS_MPI_IELBAH PMCS_DWRD(0x18) /* IOP Log Buffer high 32 bits */
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh#define PMCS_MPI_IELBAL PMCS_DWRD(0x19) /* IOP Log Buffer low 32 bits */
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh#define PMCS_MPI_IELBS PMCS_DWRD(0x1A) /* size in bytes of IOP log buffer */
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh#define PMCS_MPI_IELSEV PMCS_DWRD(0x1B) /* Log Severity */
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh * Fatal Error Handling
c280a92b706bf16eee2a24cc328c9b78d71cb38cDavid Hollister#define PMCS_PCAD64 0x2 /* PI/CI addresses are 64-bit */
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh#define PMCS_FERIV_MASK 0xff00 /* Fatal Err Interrupt Mask */
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh#define PMCS_FERIV_SHIFT 8 /* Fatal Err Interrupt Shift */
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh#define PMCS_MPI_IRAE 0x20000 /* Interrupt Reassertion Enable */
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh#define PMCS_MPI_IRAU 0x40000 /* Interrupt Reassertion Unit */
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh#define PMCS_MPI_IRAD_MASK 0xfff80000 /* Reassertion Delay Mask */
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh * MPI GST Table Offsets
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh#define PMCS_GST_PHY_INFO(x) (PMCS_GST_BASE + PMCS_DWRD(0x6) + PMCS_DWRD(x))
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh#define PMCS_GST_RERR_BASE (PMCS_GST_BASE + PMCS_DWRD(0x11))
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh#define PMCS_GST_RERR_INFO(x) (PMCS_GST_RERR_BASE + PMCS_DWRD(x))
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh * MPI Inbound Queue Configuration Table Offsets
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh * Each Inbound Queue configuration area consumes 8 DWORDS (32 bit words),
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh * or 32 bytes.
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh * MPI Outbound Queue Configuration Table Offsets
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh * Each Outbound Queue configuration area consumes 9 DWORDS (32 bit words),
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh * or 36 bytes.
4c06356b0f0fffb4fc1b6eccc8e5d8e2254a84d6dh#endif /* _PMCS_MPI_H */