pmcs_iomb.h revision 2ac4abe882db38ef90020f7c5ca28586e3d57258
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*
*
* Copyright 2010 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
/*
* PMC 8x6G IOMB Definitions
*/
#ifndef _PMCS_IOMB_H
#define _PMCS_IOMB_H
#ifdef __cplusplus
extern "C" {
#endif
/*
* An IOMB (IO Message Buffer) is the principle means of communication
* between the PMC and the HOST. The host places IOMBs on the Inbound
* Queues (IQ) which are in HOST memory and updates a producer index
* within the PMC. The PMC pulls the IOMB off the IQ and updates a
* consumer index in HOST memory. If appropriate, when the PMC is
* done with the action requested by the IOMB, the PMC writes a
* reply IOMB to host memory and updates its producer index and
* interrupts the HOST.
*/
/*
* The first word of all IOMBs is always laid out thusly:
*
* |Byte 3 |Byte 2 |Byte 1 |Byte 0 |
* +-------------+-------------+----------------------+
* |V Resvd BC|Resvd OBID |CAT | OPCODE |
* +--------------------------------------------------+
*
* V == Valid
* BC = Buffer Count
* OBID = Outbound Queue ID
* CAT = Category
* OPCODE = Well, uh, OPCODE.
*/
#define PMCS_IOMB_BC_SHIFT (24)
#define PMCS_IOMB_OBID_SHIFT (16)
#define PMCS_IOMB_CAT_SHIFT (12)
#define PMCS_IOMB_OPCODE_MASK (0xfff)
#define PMCS_IOMB_CAT_NET 0
#define PMCS_IOMB_CAT_FC 1
#define PMCS_IOMB_CAT_SAS 2
#define PMCS_IOMB_CAT_SCSI 3
/*
* Shorthand
*/
#define PMCS_IOMB_IN_SAS(q, opcode) \
(PMCS_IOMB_CAT_SAS << PMCS_IOMB_CAT_SHIFT) | \
((q << PMCS_IOMB_OBID_SHIFT) & PMCS_IOMB_OBID_MASK) | \
/*
* PMC IOMB Inbound Queue Opcodes
*/
#define PMCIN_ECHO 0x01
#define PMCIN_GET_INFO 0x02
#define PMCIN_GET_VPD 0x03
#define PMCIN_PHY_START 0x04
#define PMCIN_PHY_STOP 0x05
#define PMCIN_SSP_INI_IO_START 0x06
#define PMCIN_SSP_INI_TM_START 0x07
#define PMCIN_SSP_INI_EXT_IO_START 0x08
#define PMCIN_DEVICE_HANDLE_ACCEPT 0x09
#define PMCIN_SSP_TGT_IO_START 0x0A
#define PMCIN_SSP_TGT_RESPONSE_START 0x0B
#define PMCIN_SSP_INI_EDC_EXT_IO_START 0x0C
#define PMCIN_SSP_INI_EDC_EXT_IO_START1 0x0D
#define PMCIN_SSP_TGT_EDC_IO_START 0x0E
#define PMCIN_SSP_ABORT 0x0F
#define PMCIN_DEREGISTER_DEVICE_HANDLE 0x10
#define PMCIN_GET_DEVICE_HANDLE 0x11
#define PMCIN_SMP_REQUEST 0x12
#define PMCIN_SMP_RESPONSE 0x13
#define PMCIN_SMP_ABORT 0x14
#define PMCIN_ASSISTED_DISCOVERY 0x15
#define PMCIN_REGISTER_DEVICE 0x16
#define PMCIN_SATA_HOST_IO_START 0x17
#define PMCIN_SATA_ABORT 0x18
#define PMCIN_LOCAL_PHY_CONTROL 0x19
#define PMCIN_GET_DEVICE_INFO 0x1A
#define PMCIN_TWI 0x1B
#define PMCIN_FW_FLASH_UPDATE 0x20
#define PMCIN_SET_VPD 0x21
#define PMCIN_GPIO 0x22
#define PMCIN_SAS_DIAG_MODE_START_END 0x23
#define PMCIN_SAS_DIAG_EXECUTE 0x24
#define PMCIN_SAW_HW_EVENT_ACK 0x25
#define PMCIN_GET_TIME_STAMP 0x26
#define PMCIN_PORT_CONTROL 0x27
#define PMCIN_GET_NVMD_DATA 0x28
#define PMCIN_SET_NVMD_DATA 0x29
#define PMCIN_SET_DEVICE_STATE 0x2A
#define PMCIN_GET_DEVICE_STATE 0x2B
/*
* General Inbound Queue related parameters (DWORD 4)
*/
/*
* SATA Host IO Start ATA Protocol Types
* (placed into DWORD 4)
*/
/*
* SAS Host IO Start TLR definitions
* (placed into DWORD 4)
*/
#define SAS_TLR_ALL 0 /* SAS 1.1 and SAS 2.0 per device mode page */
/*
* IOP SMP Request Information
*/
#define SMP_INDIRECT_RESPONSE 0x01
#define SMP_INDIRECT_REQUEST 0x02
#define SMP_PHY_OVERRIDE 0x04
#define SMP_REQUEST_LENGTH_SHIFT 16
/*
* PHY Start related definitions
*/
#define PHY_LINK_1_5 0x01
#define PHY_LINK_3 0x02
#define PHY_LINK_6 0x04
#define PHY_LINK_SHIFT 8
#define PHY_LM_SAS 1
#define PHY_LM_SATA 2
#define PHY_LM_AUTO 3
#define PHY_MODE_SHIFT 12
/*
* LOCAL PHY CONTROL related definitions
*/
/*
* Device Registration related definitions
*/
#define PMCS_DEVREG_LINK_RATE_SHIFT 24
#define PMCS_DEVREG_TYPE_SATA 0
#define PMCS_DEVREG_IT_NEXUS_TIMEOUT 2000U
/* bits for device ID. */
/*
*/
typedef struct pmcs_get_nvmd_cmd_s {
typedef struct pmcs_set_nvmd_cmd_s {
#define PMCIN_NVMD_DIRECT_PLD 0x00
#define PMCIN_NVMD_INDIRECT_PLD 0x80
/* TWI bus number is upper 4 bits of tbn_tdps */
#define PMCIN_NVMD_TBN(x) (x << 4)
/* TWI Device Page Size bits (lower 4 bits of tbn_tdps */
#define PMCIN_NVMD_TDPS_1 0 /* 1 byte */
/* TWI Device Address Size (upper 4 bits of tdas_nvmd) */
/*
* TWI Device Address
* The address used to access TWI device for the 2Kb SEEPROM device is
* arranged as follows:
* Bits 7-4 are fixed (0xA)
* Bits 3-1 are page numbers for each 256 byte page
* Bit 0: Set to "1" to read, "0" to write
* SET or a GET.
*/
#define PMCIN_TDA_BASE 0xA0
/* NVM Device bits (lower 4 bits of tdas_nvmd) */
#define PMCIN_NVMD_TWI 0 /* TWI Device */
#define PMCS_SEEPROM_PAGE_SIZE 256
/*
* Minimum and maximum sizes of SPCBoot image
*/
#define PMCS_SPCBOOT_MIN_SIZE 64
#define PMCS_SPCBOOT_MAX_SIZE 512
#define PMCS_SEEPROM_SIGNATURE 0xFEDCBA98
/*
* Register dump information
*
* There are two 16KB regions for register dump information
*/
#define PMCS_NVMD_EVENT_LOG_OFFSET 0x10000
/*
* The list of items we can retrieve via the GET_NVMD_DATA command
*/
typedef enum {
PMCS_NVMD_VPD = 0,
/*
* Command types, descriptors and offsets for SAS_DIAG_EXECUTE.
*/
#define PMCS_DIAG_CMD_DESC_SHIFT 8
#define PMCS_DIAG_CMD_SHIFT 13
/*
* VPD data layout
*/
/*
* This structure defines the "header" for the VPD data. Everything
* following this structure is self-defining. The consumer just needs
* to allocate a buffer large enough for vpd_length + 3 bytes of data.
*/
typedef struct {
/* strid_length bytes follow */
typedef struct {
char keyword[2];
/*
* From here on out are definitions related to Outbound Queues
* (completions of Inbound Queue requests and async events)
*/
/*
* PMC IOMB Outbound Queue Opcodes
*/
#define PMCOUT_ECHO 0x01
#define PMCOUT_GET_INFO 0x02
#define PMCOUT_GET_VPD 0x03
#define PMCOUT_SAS_HW_EVENT 0x04
#define PMCOUT_SSP_COMPLETION 0x05
#define PMCOUT_SMP_COMPLETION 0x06
#define PMCOUT_LOCAL_PHY_CONTROL 0x07
#define PMCOUT_SAS_ASSISTED_DISCOVERY_EVENT 0x08
#define PMCOUT_SATA_ASSISTED_DISCOVERY_EVENT 0x09
#define PMCOUT_DEVICE_REGISTRATION 0x0A
#define PMCOUT_DEREGISTER_DEVICE_HANDLE 0x0B
#define PMCOUT_GET_DEVICE_HANDLE 0x0C
#define PMCOUT_SATA_COMPLETION 0x0D
#define PMCOUT_SATA_EVENT 0x0E
#define PMCOUT_SSP_EVENT 0x0F
#define PMCOUT_DEVICE_HANDLE_ARRIVED 0x10
#define PMCOUT_SMP_REQUEST_RECEIVED 0x11
#define PMCOUT_SSP_REQUEST_RECEIVED 0x12
#define PMCOUT_DEVICE_INFO 0x13
#define PMCOUT_FW_FLASH_UPDATE 0x14
#define PMCOUT_SET_VPD 0x15
#define PMCOUT_GPIO 0x16
#define PMCOUT_GPIO_EVENT 0x17
#define PMCOUT_GENERAL_EVENT 0x18
#define PMCOUT_TWI 0x19
#define PMCOUT_SSP_ABORT 0x1A
#define PMCOUT_SATA_ABORT 0x1B
#define PMCOUT_SAS_DIAG_MODE_START_END 0x1C
#define PMCOUT_SAS_DIAG_EXECUTE 0x1D
#define PMCOUT_GET_TIME_STAMP 0x1E
#define PMCOUT_SAS_HW_EVENT_ACK_ACK 0x1F
#define PMCOUT_PORT_CONTROL 0x20
#define PMCOUT_SKIP_ENTRIES 0x21
#define PMCOUT_SMP_ABORT 0x22
#define PMCOUT_GET_NVMD_DATA 0x23
#define PMCOUT_SET_NVMD_DATA 0x24
#define PMCOUT_DEVICE_HANDLE_REMOVED 0x25
#define PMCOUT_SET_DEVICE_STATE 0x26
#define PMCOUT_GET_DEVICE_STATE 0x27
#define PMCOUT_SET_DEVICE_INFO 0x28
/*
* General Outbound Status Definitions
*/
#define PMCOUT_STATUS_OK 0x00
#define PMCOUT_STATUS_ABORTED 0x01
#define PMCOUT_STATUS_OVERFLOW 0x02
#define PMCOUT_STATUS_UNDERFLOW 0x03
#define PMCOUT_STATUS_FAILED 0x04
#define PMCOUT_STATUS_ABORT_RESET 0x05
#define PMCOUT_STATUS_IO_NOT_VALID 0x06
#define PMCOUT_STATUS_NO_DEVICE 0x07
#define PMCOUT_STATUS_ILLEGAL_PARAMETER 0x08
#define PMCOUT_STATUS_LINK_FAILURE 0x09
#define PMCOUT_STATUS_PROG_ERROR 0x0A
#define PMCOUT_STATUS_EDC_IN_ERROR 0x0B
#define PMCOUT_STATUS_EDC_OUT_ERROR 0x0C
#define PMCOUT_STATUS_ERROR_HW_TIMEOUT 0x0D
#define PMCOUT_STATUS_XFER_ERR_BREAK 0x0E
#define PMCOUT_STATUS_XFER_ERR_PHY_NOT_READY 0x0F
#define PMCOUT_STATUS_OPEN_CNX_PROTOCOL_NOT_SUPPORTED 0x10
#define PMCOUT_STATUS_OPEN_CNX_ERROR_ZONE_VIOLATION 0x11
#define PMCOUT_STATUS_OPEN_CNX_ERROR_BREAK 0x12
#define PMCOUT_STATUS_OPEN_CNX_ERROR_IT_NEXUS_LOSS 0x13
#define PMCOUT_STATUS_OPENCNX_ERROR_BAD_DESTINATION 0x14
#define PMCOUT_STATUS_OPEN_CNX_ERROR_STP_RESOURCES_BUSY 0x16
#define PMCOUT_STATUS_OPEN_CNX_ERROR_WRONG_DESTINATION 0x17
#define PMCOUT_STATUS_OPEN_CNX_ERROR_UNKNOWN_ERROR 0x18
#define PMCOUT_STATUS_IO_XFER_ERROR_NAK_RECEIVED 0x19
#define PMCOUT_STATUS_XFER_ERROR_ACK_NAK_TIMEOUT 0x1A
#define PMCOUT_STATUS_XFER_ERROR_PEER_ABORTED 0x1B
#define PMCOUT_STATUS_XFER_ERROR_RX_FRAME 0x1C
#define PMCOUT_STATUS_IO_XFER_ERROR_DMA 0x1D
#define PMCOUT_STATUS_XFER_ERROR_CREDIT_TIMEOUT 0x1E
#define PMCOUT_STATUS_XFER_ERROR_SATA_LINK_TIMEOUT 0x1F
#define PMCOUT_STATUS_XFER_ERROR_SATA 0x20
#define PMCOUT_STATUS_XFER_ERROR_REJECTED_NCQ_MODE 0x21
#define PMCOUT_STATUS_XFER_ERROR_ABORTED_DUE_TO_SRST 0x22
#define PMCOUT_STATUS_XFER_ERROR_ABORTED_NCQ_MODE 0x23
#define PMCOUT_STATUS_IO_XFER_OPEN_RETRY_TIMEOUT 0x24
#define PMCOUT_STATUS_SMP_RESP_CONNECTION_ERROR 0x25
#define PMCOUT_STATUS_XFER_ERROR_UNEXPECTED_PHASE 0x26
#define PMCOUT_STATUS_XFER_ERROR_RDY_OVERRUN 0x27
#define PMCOUT_STATUS_XFER_ERROR_RDY_NOT_EXPECTED 0x28
/* 0x29 */
/* 0x2A */
/* 0x2B */
/* 0x2C */
/* 0x2D */
/* 0x2E */
/* 0x2F */
#define PMCOUT_STATUS_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT 0x30
/* 0x33 */
#define PMCOUT_STATUS_XFER_ERROR_OFFSET_MISMATCH 0x34
#define PMCOUT_STATUS_XFER_ERROR_ZERO_DATA_LEN 0x35
#define PMCOUT_STATUS_XFER_CMD_FRAME_ISSUED 0x36
#define PMCOUT_STATUS_ERROR_INTERNAL_SMP_RESOURCE 0x37
#define PMCOUT_STATUS_IO_PORT_IN_RESET 0x38
#define PMCOUT_STATUS_IO_DS_NON_OPERATIONAL 0x39
#define PMCOUT_STATUS_IO_DS_IN_RECOVERY 0x3A
#define PMCOUT_STATUS_IO_TM_TAG_NOT_FOUND 0x3B
#define PMCOUT_STATUS_IO_SSP_EXT_IU_ZERO_LEN_ERROR 0x3D
#define PMCOUT_STATUS_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY 0x3F
#define PMCOUT_STATUS_IO_ABORT_IN_PROGRESS 0x40
/*
* IOMB formats
*
* NOTE: All IOMBs are little-endian with exceptions to certain parts of
* some IOMBs. For example, the SSP_RESPONSE_IU in the SSP_COMPLETION
* outbound IOMB is big-endian (SAS).
*/
/* Common IOMB header */
typedef struct pmcs_iomb_header {
cat : 4);
rsvd1 : 2);
rsvd2 : 1,
h_bit : 1,
v_bit : 1);
/* PMCOUT_SSP_COMPLETION */
typedef struct pmcout_ssp_comp {
resc_pad : 2,
rsvd1 : 5);
/* SSP_RESPONSE_IU (if it exists) */
/* Residual count (if resc_v is set) */
/*
* Device State definitions
*/
#define PMCS_DEVICE_STATE_OPERATIONAL 0x1
#define PMCS_DEVICE_STATE_PORT_IN_RESET 0x2
#define PMCS_DEVICE_STATE_IN_RECOVERY 0x3
#define PMCS_DEVICE_STATE_IN_ERROR 0x4
#define PMCS_DEVICE_STATE_NON_OPERATIONAL 0x7
/*
* Reset Types
*/
#define PMCS_SSP_LINK_RESET 0x1
#define PMCS_SSP_HARD_RESET 0x2
#define PMCS_SMP_HARD_RESET 0x3
/*
* PHYOP for LOCAL_PHY_CONTROL Command
*/
#define PMCS_PHYOP_LINK_RESET 0x01
#define PMCS_PHYOP_HARD_RESET 0x02
/*
* Specialized status values
*/
/* PHY Stop Status Results */
#define IOP_PHY_STOP_OK 0x0
#define IOP_PHY_STOP_INVALID 0x1
#define IOP_PHY_STOP_ERROR 0x3
#define IOP_PHY_STOP_ALREADY 0x4
/* PHY Start Status Results */
#define IOP_PHY_START_OK 0
#define IOP_PHY_START_INVALID 1
#define IOP_PHY_START_ALREADY 2
#define IOP_PHY_START_ERROR 3
#define PMCS_NVMD_STAT_SUCCESS 0x0000
#define PMCS_NVMD_STAT_PLD_NVMD_COMB_ERR 0x0001
#define PMCS_NVMD_STAT_PLD_LEN_ERR 0x0002
#define PMCS_NVMD_STAT_TWI_DEV_NACK 0x2001
#define PMCS_NVMD_STAT_TWI_DEV_LOST_ARB 0x2002
#define PMCS_NVMD_STAT_TWI_TIMEOUT 0x2021
#define PMCS_NVMD_STAT_TWI_BUS_NACK 0x2081
#define PMCS_NVMD_STAT_TWI_DEV_ARB_FAIL 0x2082
#define PMCS_NVMD_STAT_TWI_BUS_SER_TIMEO 0x20FF
#define PMCS_NVMD_STAT_PART_NOT_IN_FLASH 0x9001
#define PMCS_NVMD_STAT_LEN_TOO_LARGE 0x9002
#define PMCS_NVMD_STAT_FLASH_PRGRM_FAIL 0x9003
#define PMCS_NVMD_STAT_DEVID_MATCH_FAIL 0x9004
#define PMCS_NVMD_STAT_VENDID_MATCH_FAIL 0x9005
#define PMCS_NVMD_STAT_SEC_ERASE_TIMEO 0x9006
#define PMCS_NVMD_STAT_SEC_ERASE_CWE 0x9007
#define PMCS_NVMD_STAT_FLASH_DEV_BUSY 0x9008
#define PMCS_NVMD_STAT_FLASH_DEV_NOT_SUP 0x9009
#define PMCS_NVMD_STAT_FLASH_NO_CFI 0x900A
#define PMCS_NVMD_STAT_ERASE_BLOCKS 0x900B
#define PMCS_NVMD_STAT_PART_READ_ONLY 0x900C
#define PMCS_NVMD_STAT_PART_INV_MAP_TYPE 0x900D
#define PMCS_NVMD_STAT_PART_INIT_STR_DIS 0x900E
/*
* General Event Status Codes
*/
#define INBOUND_IOMB_V_BIT_NOT_SET 0x1
#define INBOUND_IOMB_OPC_NOT_SUPPORTED 0x2
/* Device Register Status Results */
#define PMCS_DEVREG_OK 0x0
#define PMCS_DEVREG_DEVICE_ALREADY_REGISTERED 0x2
#define PMCS_DEVREG_PHY_ALREADY_REGISTERED 0x4
/*
* Flash Update responses
*/
#define FLASH_UPDATE_COMPLETE_PENDING_REBOOT 0x0
#define FLASH_UPDATE_IN_PROGRESS 0x1
#define FLASH_UPDATE_HDR_ERR 0x2
#define FLASH_UPDATE_OFFSET_ERR 0x3
#define FLASH_UPDATE_UPDATE_CRC_ERR 0x4
#define FLASH_UPDATE_LENGTH_ERR 0x5
#define FLASH_UPDATE_HW_ERR 0x6
#define FLASH_UPDATE_DNLD_NOT_SUPPORTED 0x10
#define FLASH_UPDATE_DISABLED 0x11
/*
* IOP SAS HW Event Related definitions
*/
#define IOP_EVENT_PORTID(x) ((x) & 0xf)
#define IOP_EVENT_PHY_STOP_STATUS 0x03
#define IOP_EVENT_SAS_PHY_UP 0x04
#define IOP_EVENT_SATA_PHY_UP 0x05
#define IOP_EVENT_SATA_SPINUP_HOLD 0x06
#define IOP_EVENT_PHY_DOWN 0x07
#define IOP_EVENT_BROADCAST_CHANGE 0x09
#define IOP_EVENT_BROADCAST_SES 0x0B
#define IOP_EVENT_PHY_ERR_INBOUND_CRC 0x0C
#define IOP_EVENT_HARD_RESET_RECEIVED 0x0D
#define IOP_EVENT_EVENT_ID_FRAME_TIMO 0x0F
#define IOP_EVENT_BROADCAST_EXP 0x10
#define IOP_EVENT_PHY_START_STATUS 0x11
#define IOP_EVENT_PHY_ERR_INVALID_DWORD 0x12
#define IOP_EVENT_PHY_ERR_DISPARITY_ERROR 0x13
#define IOP_EVENT_PHY_ERR_CODE_VIOLATION 0x14
#define IOP_EVENT_PHY_ERR_LOSS_OF_DWORD_SYN 0x15
#define IOP_EVENT_PHY_ERR_PHY_RESET_FAILD 0x16
#define IOP_EVENT_PORT_RECOVERY_TIMER_TMO 0x17
#define IOP_EVENT_PORT_RECOVER 0x18
#define IOP_EVENT_PORT_RESET_TIMER_TMO 0x19
#define IOP_EVENT_PORT_RESET_COMPLETE 0x20
#define IOP_EVENT_BROADCAST_ASYNC_EVENT 0x21
#define IOP_EVENT_IT_NEXUS_LOSS 0x22
#define IOP_EVENT_PORT_STATE(x) ((x) & 0xf)
/*
* HW Event Acknowledge Response Values
*/
#define SAS_HW_EVENT_ACK_OK 0x0
#define SAS_HW_EVENT_ACK_INVALID_SEA 0x1
#define SAS_HW_EVENT_ACK_INVALID_PHY 0x2
#define SAS_HW_EVENT_ACK_INVALID_PORT 0x4
#define SAS_HW_EVENT_ACK_INVALID_PARAM 0x8
/*
* IOMB Queue definitions and Macros
*/
/*
* Inbound Queue Producer Indices live inside the PMC card.
*
* Inbound Queue Consumer indices live in host memory. We use the Consumer
* Index to return a pointer to an Inbound Queue entry. We then can fill
* it with an IOMB. We then update the the Producer index which kicks
* card to read the IOMB we just wrote.
*
* There is one mutex for each inbound queue that is held from the time
* we get an entry until we increment the producer index, or released
* manually if we don't actually send the message.
*/
/*
* NB: the appropriate iqp_lock must be held
*/
/*
* NB: This releases the lock on the Inbound Queue that GET_IO_IQ_ENTRY
* acquired below.
*/
#ifdef DEBUG
{ \
DDI_DMA_SYNC_FORDEV) != DDI_SUCCESS) { \
} \
}
#else
DDI_DMA_SYNC_FORDEV) != DDI_SUCCESS) { \
} \
#endif
/*
* NB: sucessfull acquisition of an IO Inbound Queue
* entry leaves the lock on that Inbound Queue held.
*/
if (msg) { \
break; \
} \
} \
}
/*
* Outbound Queue Macros
*
* Outbound Queue Consumer indices live inside the card.
*
* Outbound Queue Producer indices live in host memory. When the card
* wants to send an IOMB, it uses the producer index to find the spot
* to write the IOMB. After it's done it updates the producer index
* and interrupts the host. The host reads the producer index (from
* host memory) and reads IOMBs up to but not including that index.
* It writes that index back to the consumer index on the card,
* signifying that it has read up to that which the card has sent.
*/
#ifdef __cplusplus
}
#endif
#endif /* _PMCS_IOMB_H */