/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _NV_SGPIO_H
#define _NV_SGPIO_H
#ifdef __cplusplus
extern "C" {
#endif
/*
* SGPIO Command Timeout (2000ms, in nsecs)
*/
/*
* SGPIO Configuration Space Offsets
*/
/*
*/
/* Command field - write-only */
/* Command field values */
/* Command Status field - read-only */
/* Command Status field values */
/* Sequence field - read-only */
/* SGPIO Status field - read-only */
#define SGPIO_CSR_SSTAT_SHFT 0
/* SGPIO Status field values */
/*
* SGPIO Control Block
* This is not the entire control block. It stops at the last register
* that could possibly be used.
*/
typedef struct nv_sgp_cb {
#if defined(__amd64)
#else
#endif
/* Configuration Register */
/* Configuration Register */
} nv_sgp_cb_t;
/*
* NVIDIA Configuration Register (SGPIO_NVCR)
* Contains read-only configuration fields that are unique to NVIDIA's
* implementation of SGPIO and therefore not defined in SFF8485.
*/
/* Initiator Count */
#define SGP_NVCR_INIT_CNT_SHFT 0
/* fixed value */
/* Command Block Size */
/* Command Block Version */
/* current version value */
#define SGP_NVCR_CB_VERSION 0
/*
* SGPIO Configuration Register 0 (SGPIO_CR0)
*/
/* Version */
/* fixed value */
#define SGP_CR0_VERSION 0
/* Enable - write-only */
/* CFG Register Count */
/* fixed value */
/* GP Register Count */
/* fixed value */
/* Supported Drive Count */
/* fixed value */
/*
* SGPIO Configuration Register 1 (SGPIO_CR1)
*/
#ifdef SGPIO_BLINK
/*
* NVIDIA documents these Blink Generator Rate values. However,
* setting up the LEDs to use these Blink Generators does not result
* in blinking LEDs.
*/
/* Blink Generator Rate B */
/* Blink Generator Rate A */
/* Blink Generator Rate values */
#endif /* SGPIO_BLINK */
/*
* SGPIO 0 Transmit Register (SGPIO_0_TR)
*/
/* Drive x Activity */
/* Drive x Activity values */
#ifdef SGPIO_BLINK
/* duty cycle, on for the first */
/* half-cycle, off for the second */
/* half. */
/* duty cycle, off for the first */
/* half-cycle, on for the second */
/* half. */
/* duty cycle, on for the first */
/* half-cycle, off for the second */
/* half. */
/* duty cycle, off for the first */
/* half-cycle, on for the second */
/* half. */
#endif /* SGPIO_BLINK */
/* Drive x Locate */
/* Drive x Locate values */
#ifdef SGPIO_BLINK
/* duty cycle, on for the first */
/* half-cycle, off for the second */
/* half. */
/* duty cycle, off for the first */
/* half-cycle, on for the second */
/* half. */
#endif /* SGPIO_BLINK */
/* Drive x Error */
#define TR_ERROR_SHFT 0
/* Drive x Error values */
#ifdef SGPIO_BLINK
/* duty cycle, on for the first */
/* half-cycle, off for the second */
/* half for error indicator. */
/* duty cycle, off for the first */
/* half-cycle, on for the second */
/* half for error indicator. */
/* duty cycle, on for the first */
/* half-cycle, off for the second */
/* half for error indicator. */
/* duty cycle, off for the first */
/* half-cycle, on for the second */
/* half for error indicator. */
#endif /* SGPIO_BLINK */
/*
* SGPIO 1 Transmit Register (SGPIO_1_TR)
*/
#ifdef __cplusplus
}
#endif
#endif /* _NV_SGPIO_H */