nv_sata.h revision b5fc475bca6525d8da80728128eefb7100aaf66b
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * CDDL HEADER START
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * The contents of this file are subject to the terms of the
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * Common Development and Distribution License (the "License").
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * You may not use this file except in compliance with the License.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * or http://www.opensolaris.org/os/licensing.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * See the License for the specific language governing permissions
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * and limitations under the License.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * When distributing Covered Code, include this CDDL HEADER in each
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
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49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * fields enclosed by brackets "[]" replaced with your own identifying
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49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * CDDL HEADER END
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * Use is subject to license terms.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#pragma ident "%Z%%M% %I% %E% SMI"
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define NV_MAX_PORTS(nvc) nvc->nvc_sata_hba_tran.sata_tran_hba_num_cports
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amoretypedef struct nv_ctl {
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * Each of these are specific to the chipset in use.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore uint_t (*nvc_interrupt)(caddr_t arg1, caddr_t arg2);
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore dev_info_t *nvc_dip; /* devinfo pointer of controller */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore struct nv_port *nvc_port; /* array of pointers to port struct */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * handle and base address to register space.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * 0: port 0 task file
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * 1: port 0 status
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * 2: port 1 task file
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * 3: port 1 status
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * 4: bus master for both ports
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * 5: extended registers for SATA features
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * sata registers in bar 5 which are shared on all devices
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * on the channel.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore uint32_t *nvc_mcp55_ncq; /* NCQ status control bits */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore ddi_intr_handle_t *nvc_htable; /* For array of interrupts */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore int nvc_intr_type; /* What type of interrupt */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore int nvc_intr_cnt; /* # of intrs count returned */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore size_t nvc_intr_size; /* Size of intr array to */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore uint_t nvc_intr_pri; /* Interrupt priority */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore int nvc_intr_cap; /* Interrupt capabilities */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore uint8_t *nvc_mcp04_int_status; /* interrupt status mcp04 */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore sata_hba_tran_t nvc_sata_hba_tran; /* sata_hba_tran for ctrl */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * enable/disable interrupts, controller specific
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore void (*nvc_set_intr)(nv_port_t *nvp, int flag);
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore int nvc_state; /* state flags of ctrl see below */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore uint8_t nvc_revid; /* PCI revid of device */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore struct nv_ctl *nvp_ctlp; /* back pointer to controller */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore uint8_t nvp_port_num; /* port number, ie 1 or 2 */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore uint8_t nvp_type; /* SATA_DTYPE_{NONE,ATADISK,UNKNOWN} */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore uint32_t nvp_signature; /* sig acquired from task file regs */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore uchar_t *nvp_cmd_addr; /* base addr for cmd regs for port */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore uchar_t *nvp_bm_addr; /* base addr for bus master for port */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore uchar_t *nvp_ctl_addr; /* base addr for ctrl regs for port */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore uchar_t *nvp_error; /* error register (read) */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore uchar_t *nvp_feature; /* features (write) */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore uchar_t *nvp_drvhd; /* drive/head register */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore uchar_t *nvp_status; /* status/command register */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore uchar_t *nvp_cmd; /* status/command register */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore uchar_t *nvp_altstatus; /* alternate status (read) */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore uchar_t *nvp_devctl; /* device control (write) */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore ddi_dma_handle_t *nvp_sg_dma_hdl; /* dma handle to prd table */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore caddr_t *nvp_sg_addr; /* virtual addr of prd table */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore uint32_t *nvp_sg_paddr; /* physical address of prd table */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore ddi_acc_handle_t *nvp_sg_acc_hdl; /* mem acc handle to the prd table */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore kmutex_t nvp_mutex; /* main per port mutex */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore kcondvar_t nvp_poll_cv; /* handshake cv between poll & isr */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * nvp_slot is a pointer to an array of nv_slot
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore uint32_t nvp_sactive_cache; /* cache of SACTIVE */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * NCQ flow control. During NCQ operation, no other commands
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * allowed. The following are used to enforce this.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore clock_t nvp_reset_time; /* time of last reset */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore clock_t nvp_probe_time; /* time when probe began */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore clock_t nvp_link_lost_time; /* time link lost was noticed */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore int nvp_state; /* state of port. flags defined below */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore ushort_t type; /* chipset type, mcp04 or mcp55 */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amoretypedef struct nv_slot {
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore caddr_t nvslot_v_addr; /* I/O buffer address */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore size_t nvslot_byte_count; /* # bytes left to read/write */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore uint8_t nvslot_rqsense_buff[SATA_ATAPI_RQSENSE_LEN];
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore int (*nvslot_start)(nv_port_t *nvp, int queue);
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * nvslot_flags
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define NVSLOT_RQSENSE 0x04 /* processing request sense */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * state values for nv_attach
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define ATTACH_PROGRESS_STATEP_ALLOC (1 << 1)
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define ATTACH_PROGRESS_SATA_MODULE (1 << 10)
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#endif /* DEBUG */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * nv_debug_flags
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * indicates whether nv_wait functions can sleep or not.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * port offsets from base address ioaddr1
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define NV_ERROR 0x01 /* error register (read) */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define NV_FEATURE 0x01 /* features (write) */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define NV_HCYL 0x05 /* cylinder high byte */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define NV_DRVHD 0x06 /* drive/head register */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define NV_STATUS 0x07 /* status/command register */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define NV_CMD 0x07 /* status/command register */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * port offsets from base address ioaddr2
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define NV_ALTSTATUS 0x02 /* alternate status (read) */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define NV_DEVCTL 0x02 /* device control (write) */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * device control register
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define ATDC_NIEN 0x02 /* disable interrupts */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define ATDC_SRST 0x04 /* controller reset */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define ATDC_HOB 0x80 /* high order byte to read 48-bit values */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define MCP55_CTL 0x400 /* queuing control */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define MCP55_INT_STATUS 0x440 /* status bits for interrupt */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define MCP55_INT_CTL 0x444 /* enable bits for interrupt */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define MCP55_NCQ 0x448 /* NCQ status and ctrl bits */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * if either of these bits are set, when using NCQ, if no other commands are
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * active while a new command is started, DMA engine can be programmed ahead
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * of time to save extra interrupt. Presumably pre-programming is discarded
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * if a subsequent command ends up finishing first.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define MCP_SATA_AE_NCQ_PDEV_FIRST_CMD (1 << 7)
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define MCP_SATA_AE_NCQ_SDEV_FIRST_CMD (1 << 23)
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * bit definitions to indicate which NCQ command requires
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define MCP_SATA_AE_NCQ_PDEV_DMA_SETUP_TAG_SHIFT 2
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define MCP_SATA_AE_NCQ_SDEV_DMA_SETUP_TAG_SHIFT 18
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define MCP_SATA_AE_NCQ_DMA_SETUP_TAG_MASK 0x1f
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * Bits for NV_MCP55_INT_CTL and NV_MCP55_INT_STATUS
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define MCP55_INT_SNOTIFY 0x200 /* snotification set */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define MCP55_INT_SERROR 0x100 /* serror set */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define MCP55_INT_DMA_SETUP 0x80 /* DMA to be programmed */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define MCP55_INT_DH_REGFIS 0x40 /* REGFIS received */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define MCP55_INT_TX_BACKOUT 0x10 /* TX backout */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define MCP55_INT_REM 0x08 /* device removed */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define MCP55_INT_ADD 0x04 /* device added */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define MCP55_INT_PM 0x02 /* power changed */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define MCP55_INT_COMPLETE 0x01 /* device interrupt */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * Bits above that are not used for now.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define MCP55_INT_IGNORE (MCP55_INT_DMA_SETUP|MCP55_INT_DH_REGFIS|\
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore MCP55_INT_SDB_FIS|MCP55_INT_TX_BACKOUT|MCP55_INT_PM|\
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * Bits for MCP_SATA_AE_CTL
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define MCP_SATA_AE_CTL_PRI_SWNCQ (1 << 1) /* software NCQ chan 0 */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define MCP_SATA_AE_CTL_SEC_SWNCQ (1 << 2) /* software NCQ chan 1 */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * signatures in task file registers after device reset
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * These bar5 offsets are common to mcp55/mcp04 and thus
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * prefixed with NV.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * The following config space offsets are needed to enable
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * bar 5 register access in mcp04/mcp55
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * mcp04 interrupt status register
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * offsets to bar 5 registers
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * bit fields for int status and int enable
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define MCP04_INT_PDEV_INT 0x01 /* completion interrupt */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define MCP04_INT_PDEV_PM 0x02 /* power change */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define MCP04_INT_PDEV_ADD 0x04 /* hot plug */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define MCP04_INT_PDEV_REM 0x08 /* hot remove */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define MCP04_INT_PDEV_HOT MCP04_INT_PDEV_ADD|MCP04_INT_PDEV_REM
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define MCP04_INT_SDEV_INT 0x10 /* completion interrupt */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define MCP04_INT_SDEV_PM 0x20 /* power change */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define MCP04_INT_SDEV_ADD 0x40 /* hot plug */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define MCP04_INT_SDEV_REM 0x80 /* hot remove */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define MCP04_INT_SDEV_HOT MCP04_INT_SDEV_ADD|MCP04_INT_SDEV_REM
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define MCP04_INT_PDEV_ALL MCP04_INT_PDEV_INT|MCP04_INT_PDEV_HOT|\
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define MCP04_INT_SDEV_ALL MCP04_INT_SDEV_INT|MCP04_INT_SDEV_HOT|\
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * config space offset 42
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * bit in CFG_42 which delays hotplug interrupt until
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define MCP04_CFG_DELAY_HOTPLUG_INTR (0x1 << 12)
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * bar 5 offsets for SATA registers in ck804
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * bar 5 offsets for ADMACTL settings for both mcp04/mcp55
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * Bits for NV_ADMACTL_X and NV_ADMACTL_Y
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define NV_HIRQ_EN 0x01 /* hot plug/unplug interrupt enable */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * bar 5 offset for ADMASTAT regs for mcp04
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * Bits for MCP04_ADMASTAT_X and MCP04_ADMASTAT_Y
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * bar 4 offset to bus master command registers
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * bit definitions for BMICX_REG
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define BMICX_SSBM 0x01 /* Start/Stop Bus Master */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore /* 1=Start (Enable) */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore /* 0=Start (Disable) */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * NOTE: "read" and "write" are the actions of the DMA engine
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * on the PCI bus, not the SATA bus. Therefore for a ATA READ
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * command, program the DMA engine to "write to memory" mode
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * (and vice versa).
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define BMICX_RWCON 0x08 /* Read/Write Control */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define BMICX_RWCON_WRITE_TO_MEMORY 0x08 /* 1=Write (dev to host) */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define BMICX_RWCON_READ_FROM_MEMORY 0x00 /* 0=Read (host to dev) */
typedef struct prde {
} prde_t;
#ifdef NCQ
* flags for mcp04_set_intr/mcp55_set_intr
#ifdef __cplusplus