nv_sata.h revision a78a9fafefff1ddbaa3ef65fa09190848e704a27
2a8d6eba033e4713ab12b61178f0513f1f075482Rod Evans * CDDL HEADER START
2a8d6eba033e4713ab12b61178f0513f1f075482Rod Evans * The contents of this file are subject to the terms of the
2a8d6eba033e4713ab12b61178f0513f1f075482Rod Evans * Common Development and Distribution License (the "License").
2a8d6eba033e4713ab12b61178f0513f1f075482Rod Evans * You may not use this file except in compliance with the License.
2a8d6eba033e4713ab12b61178f0513f1f075482Rod Evans * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
2a8d6eba033e4713ab12b61178f0513f1f075482Rod Evans * See the License for the specific language governing permissions
2a8d6eba033e4713ab12b61178f0513f1f075482Rod Evans * and limitations under the License.
2a8d6eba033e4713ab12b61178f0513f1f075482Rod Evans * When distributing Covered Code, include this CDDL HEADER in each
2a8d6eba033e4713ab12b61178f0513f1f075482Rod Evans * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
2a8d6eba033e4713ab12b61178f0513f1f075482Rod Evans * If applicable, add the following below this CDDL HEADER, with the
2a8d6eba033e4713ab12b61178f0513f1f075482Rod Evans * fields enclosed by brackets "[]" replaced with your own identifying
2a8d6eba033e4713ab12b61178f0513f1f075482Rod Evans * information: Portions Copyright [yyyy] [name of copyright owner]
2a8d6eba033e4713ab12b61178f0513f1f075482Rod Evans * CDDL HEADER END
2a8d6eba033e4713ab12b61178f0513f1f075482Rod Evans * Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved.
2a8d6eba033e4713ab12b61178f0513f1f075482Rod Evans * SGPIO Support
2a8d6eba033e4713ab12b61178f0513f1f075482Rod Evans * Enable SGPIO support only on x86/x64, because it is implemented using
2a8d6eba033e4713ab12b61178f0513f1f075482Rod Evans * functions that are only available on x86/x64.
2a8d6eba033e4713ab12b61178f0513f1f075482Rod Evans#define NV_MAX_PORTS(nvc) nvc->nvc_sata_hba_tran.sata_tran_hba_num_cports
2a8d6eba033e4713ab12b61178f0513f1f075482Rod Evans * sizes of strings to allocate
2a8d6eba033e4713ab12b61178f0513f1f075482Rod Evanstypedef struct nv_ctl {
2a8d6eba033e4713ab12b61178f0513f1f075482Rod Evans * Each of these are specific to the chipset in use.
2a8d6eba033e4713ab12b61178f0513f1f075482Rod Evans uint_t (*nvc_interrupt)(caddr_t arg1, caddr_t arg2);
2a8d6eba033e4713ab12b61178f0513f1f075482Rod Evans dev_info_t *nvc_dip; /* devinfo pointer of controller */
2a8d6eba033e4713ab12b61178f0513f1f075482Rod Evans struct nv_port *nvc_port; /* array of pointers to port struct */
2a8d6eba033e4713ab12b61178f0513f1f075482Rod Evans * handle and base address to register space.
2a8d6eba033e4713ab12b61178f0513f1f075482Rod Evans * 0: port 0 task file
2a8d6eba033e4713ab12b61178f0513f1f075482Rod Evans * 1: port 0 status
2a8d6eba033e4713ab12b61178f0513f1f075482Rod Evans * 2: port 1 task file
2a8d6eba033e4713ab12b61178f0513f1f075482Rod Evans * 3: port 1 status
2a8d6eba033e4713ab12b61178f0513f1f075482Rod Evans * 4: bus master for both ports
2a8d6eba033e4713ab12b61178f0513f1f075482Rod Evans * 5: extended registers for SATA features
#ifdef SGPIO_SUPPORT
} nv_ctl_t;
struct nv_port {
int nvp_ncq_run;
int nvp_non_ncq_run;
int nvp_seq;
#ifdef SGPIO_SUPPORT
int nvp_trans_link_count;
int nvp_reset_count;
int intr_loop_cnt;
typedef struct nv_device_table {
typedef struct nv_slot {
} nv_slot_t;
#ifdef SGPIO_SUPPORT
struct nv_sgp_cmn {
struct nv_sgp_cbp2cmn {
#ifdef DEBUG
#define NV_SUCCESS 0
#define BMICX_REG 0
typedef struct prde {
} prde_t;
#ifdef NCQ
#define NV_ADD_DEV 0
* flags for ck804_set_intr/mcp5x_set_intr
#ifdef SGPIO_SUPPORT
#ifdef __cplusplus