nv_sata.h revision 42a68bf3e24266637dd43e76027e23767bbdb1b4
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _NV_SATA_H
#define _NV_SATA_H
#ifdef __cplusplus
extern "C" {
#endif
/*
* SGPIO Support
*/
#ifdef SGPIO_SUPPORT
typedef struct nv_sgp_cmn nv_sgp_cmn_t;
#endif
typedef struct nv_ctl {
/*
* Each of these are specific to the chipset in use.
*/
/*
* handle and base address to register space.
*
* 0: port 0 task file
* 1: port 0 status
* 2: port 1 task file
* 3: port 1 status
* 4: bus master for both ports
* 5: extended registers for SATA features
*/
/*
* sata registers in bar 5 which are shared on all devices
* on the channel.
*/
int nvc_intr_type; /* What type of interrupt */
int nvc_intr_cnt; /* # of intrs count returned */
int nvc_intr_cap; /* Interrupt capabilities */
/*
*/
int nvc_state; /* state flags of ctrl see below */
#ifdef SGPIO_SUPPORT
int nvc_mcp5x_flag; /* is the controller MCP51/MCP55 */
#endif
} nv_ctl_t;
struct nv_port {
/*
* nvp_slot is a pointer to an array of nv_slot
*/
/*
* NCQ flow control. During NCQ operation, no other commands
* allowed. The following are used to enforce this.
*/
int nvp_ncq_run;
int nvp_non_ncq_run;
int nvp_state; /* state of port. flags defined below */
#ifdef SGPIO_SUPPORT
#endif
};
typedef struct nv_device_table {
typedef struct nv_slot {
} nv_slot_t;
#ifdef SGPIO_SUPPORT
struct nv_sgp_cmn {
int nvs_cbp; /* SGPIO Control Block Pointer */
int nvs_taskq_delay; /* rest time for activity LED taskq */
};
struct nv_sgp_cbp2cmn {
};
#endif
/*
* nvslot_flags
*/
#define NVSLOT_COMPLETE 0x01
/*
* state values for nv_attach
*/
#define ATTACH_PROGRESS_NONE (1 << 0)
#ifdef DEBUG
#define NV_DEBUG 1
#endif /* DEBUG */
/*
* nv_debug_flags
*/
#define NVDBG_ALWAYS 0x0001
#define NVDBG_INIT 0x0002
#define NVDBG_ENTRY 0x0004
#define NVDBG_DELIVER 0x0008
#define NVDBG_EVENT 0x0010
#define NVDBG_SYNC 0x0020
#define NVDBG_PKTCOMP 0x0040
#define NVDBG_TIMEOUT 0x0080
#define NVDBG_INFO 0x0100
#define NVDBG_VERBOSE 0x0200
#define NVDBG_INTR 0x0400
#define NVDBG_ERRS 0x0800
#define NVDBG_COOKIES 0x1000
#define NVDBG_HOT 0x2000
#define NVDBG_PROBE 0x4000
#define NVDBG_ATAPI 0x8000
#ifdef DEBUG
#else
#define NVLOG(a)
#endif
#define NV_SUCCESS 0
#define NV_FAILURE -1
/*
* indicates whether nv_wait functions can sleep or not.
*/
#define NV_SLEEP 1
#define NV_NOSLEEP 2
/*
* port offsets from base address ioaddr1
*/
/*
* port offsets from base address ioaddr2
*/
/*
* device control register
*/
/*
* if either of these bits are set, when using NCQ, if no other commands are
* active while a new command is started, DMA engine can be programmed ahead
* of time to save extra interrupt. Presumably pre-programming is discarded
* if a subsequent command ends up finishing first.
*/
/*
* bit definitions to indicate which NCQ command requires
* DMA setup.
*/
#define MCP_SATA_AE_NCQ_PDEV_DMA_SETUP_TAG_SHIFT 2
#define MCP_SATA_AE_NCQ_SDEV_DMA_SETUP_TAG_SHIFT 18
#define MCP_SATA_AE_NCQ_DMA_SETUP_TAG_MASK 0x1f
/*
* Bits for NV_MCP5X_INT_CTL and NV_MCP5X_INT_STATUS
*/
/*
* Bits above that are not used for now.
*/
/*
* Bits for MCP_SATA_AE_CTL
*/
#define NV_DELAY_NSEC(wait_ns) \
{ \
}
/*
* signatures in task file registers after device reset
*/
#define NV_SIG_DISK 0x00000101
#define NV_SIG_ATAPI 0xeb140101
#define NV_SIG_PM 0x96690101
#define NV_SIG_NOTREADY 0x00000000
/*
* prefixed with NV.
*/
#define NV_SSTATUS 0x00
#define NV_SERROR 0x04
#define NV_SCTRL 0x08
#define NV_SACTIVE 0x0c
#define NV_SNOTIFICATION 0x10
#define CH0_SREG_OFFSET 0x0
#define CH1_SREG_OFFSET 0x40
/*
* The following config space offsets are needed to enable
*/
#define NV_SATA_CFG_20 0x50
#define NV_BAR5_SPACE_EN 0x04
#define NV_40BIT_PRD 0x20
/*
* ck804 interrupt status register
*/
/*
* offsets to bar 5 registers
*/
#define CK804_SATA_INT_STATUS 0x440
#define CK804_SATA_INT_EN 0x441
/*
* bit fields for int status and int enable
* registers
*/
/*
* config space offset 42
*/
#define NV_SATA_CFG_42 0xac
/*
* bit in CFG_42 which delays hotplug interrupt until
* PHY ready
*/
/*
* bar 5 offsets for SATA registers in ck804
*/
#define CK804_CH1_SSTATUS 0x00
#define CK804_CH1_SERROR 0x04
#define CK804_CH1_SCTRL 0x08
#define CK804_CH1_SACTIVE 0x0c
#define CK804_CH1_SNOTIFICATION 0x10
#define CK804_CH2_SSTATUS 0x40
#define CK804_CH2_SERROR 0x44
#define CK804_CH2_SCTRL 0x48
#define CK804_CH2_SACTIVE 0x4c
#define CK804_CH2_SNOTIFICATION 0x50
/*
*/
#define NV_ADMACTL_X 0x4C0
#define NV_ADMACTL_Y 0x5C0
/*
* Bits for NV_ADMACTL_X and NV_ADMACTL_Y
*/
/*
* bar 5 offset for ADMASTAT regs for ck804
*/
#define CK804_ADMASTAT_X 0x4C4
#define CK804_ADMASTAT_Y 0x5C4
/*
* Bits for CK804_ADMASTAT_X and CK804_ADMASTAT_Y
*/
#define CK804_HPIRQ 0x4
#define MCP05_HUIRQ 0x2
/*
* bar 4 offset to bus master command registers
*/
#define BMICX_REG 0
/*
* bit definitions for BMICX_REG
*/
/* 1=Start (Enable) */
/* 0=Start (Disable) */
/*
* NOTE: "read" and "write" are the actions of the DMA engine
* on the PCI bus, not the SATA bus. Therefore for a ATA READ
* command, program the DMA engine to "write to memory" mode
* (and vice versa).
*/
/*
* BMICX bits to preserve during updates
*/
/*
* bar 4 offset to bus master status register
*/
#define BMISX_REG 2
/*
* bit fields for bus master status register
*/
/*
* bus master status register bits to preserve
*/
#define BMISX_MASK 0xf8
/*
* bar4 offset to bus master PRD descriptor table
*/
#define BMIDTPX_REG 4
/*
* structure for a single entry in the PRD table
* (physical region descriptor table)
*/
typedef struct prde {
} prde_t;
/*
* ck804 and mcp55 both have 2 ports per controller
*/
#define NV_NUM_CPORTS 2
/*
* Number of slots to allocate in data nv_sata structures to handle
* multiple commands at once. This does not reflect the capability of
* the drive or the hardware, and in many cases will not match.
* 1 or 32 slots are allocated, so in cases where the driver has NCQ
* enabled but the drive doesn't support it, or supports fewer than
* 32 slots, here may be an over allocation of memory.
*/
#ifdef NCQ
#define NV_QUEUE_SLOTS 32
#else
#define NV_QUEUE_SLOTS 1
#endif
/*
* wait 30 seconds for signature
*/
#define NV_SIG_TIMEOUT 45
#define NV_BM_64K_BOUNDARY 0x10000ull
/*
* every 1 second
*/
#define NV_ONE_SEC 1000000
/*
* the amount of time link can be down during
* reset without taking action.
*/
#define NV_LINK_LOST_OK 2
/*
* nv_reset() flags
*/
#define NV_RESET_ATTEMPTS 3
/*
* nvp_state flags
*/
#define NV_PORT_INACTIVE 0x001
#define NV_PORT_ABORTING 0x002
#define NV_PORT_HOTREMOVED 0x004
#define NV_PORT_INIT 0x008
#define NV_PORT_FAILED 0x010
#define NV_PORT_RESET 0x020
#define NV_PORT_RESET_PROBE 0x040
#define NV_PORT_RESTORE 0x080
/*
* nvc_state flags
*/
#define NV_CTRL_SUSPEND 0x1
/*
* flags for ck804_set_intr/mcp5x_set_intr
*/
#define NV_INTR_DISABLE 0x1
#define NV_INTR_ENABLE 0x2
#define NV_INTR_CLEAR_ALL 0x4
#define NV_INTR_DISABLE_NON_BLOCKING 0x8
/*
* sizes of strings to allocate
*/
#define NV_STRING_10 10
#define NV_STRING_512 512
#define NV_BYTES_PER_SEC 512
/*
* definition labels for the BAR registers
*/
#define NV_BAR_0 0 /* chan 0 task file regs */
/*
* transform seconds to microseconds
*/
#define NV_SEC2USEC(x) x * MICROSEC
/*
* ck804 maps in task file regs into bar 5. These are
* only used to identify ck804, therefore only this reg is
* listed here.
*/
#define NV_BAR5_TRAN_LEN_CH_X 0x518
/*
* if after this many iterations through the interrupt
* processing loop, declare the interrupt wedged and
* disable.
*/
#define NV_MAX_INTR_LOOP 10
/*
* flag values for nv_copy_regs_out
*/
#ifdef SGPIO_SUPPORT
/* Pointers. Corresponds to */
/* each MCP55 and IO55 */
#define SGPIO_TQ_NAME_LEN 32
/*
* The drive number format is ccp (binary).
* cc is the controller number (0-based number)
* p is the port number (0 or 1)
*/
#define SGP_DRV_TO_PORT(d) ((d) & 1)
#define SGP_DRV_TO_CTLR(d) ((d) >> 1)
#endif
#ifdef __cplusplus
}
#endif
#endif /* _NV_SATA_H */