nv_sata.h revision a78a9fafefff1ddbaa3ef65fa09190848e704a27
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8d483882aa3390058094b043f3d62187b5d1de03mlf * CDDL HEADER END
7798b2a0723f7ed75e6d4a86f0821b4173930eb5Martin Faltesek * Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved.
8d483882aa3390058094b043f3d62187b5d1de03mlfextern "C" {
3f318a288186db82aae78875c429f248622cf19fAlan Perry * SGPIO Support
3f318a288186db82aae78875c429f248622cf19fAlan Perry * Enable SGPIO support only on x86/x64, because it is implemented using
3f318a288186db82aae78875c429f248622cf19fAlan Perry * functions that are only available on x86/x64.
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_MAX_PORTS(nvc) nvc->nvc_sata_hba_tran.sata_tran_hba_num_cports
7798b2a0723f7ed75e6d4a86f0821b4173930eb5Martin Faltesek * sizes of strings to allocate
8d483882aa3390058094b043f3d62187b5d1de03mlftypedef struct nv_ctl {
8d483882aa3390058094b043f3d62187b5d1de03mlf * Each of these are specific to the chipset in use.
8d483882aa3390058094b043f3d62187b5d1de03mlf dev_info_t *nvc_dip; /* devinfo pointer of controller */
8d483882aa3390058094b043f3d62187b5d1de03mlf struct nv_port *nvc_port; /* array of pointers to port struct */
8d483882aa3390058094b043f3d62187b5d1de03mlf * handle and base address to register space.
8d483882aa3390058094b043f3d62187b5d1de03mlf * 0: port 0 task file
8d483882aa3390058094b043f3d62187b5d1de03mlf * 1: port 0 status
8d483882aa3390058094b043f3d62187b5d1de03mlf * 2: port 1 task file
8d483882aa3390058094b043f3d62187b5d1de03mlf * 3: port 1 status
8d483882aa3390058094b043f3d62187b5d1de03mlf * 4: bus master for both ports
8d483882aa3390058094b043f3d62187b5d1de03mlf * 5: extended registers for SATA features
8d483882aa3390058094b043f3d62187b5d1de03mlf * sata registers in bar 5 which are shared on all devices
8d483882aa3390058094b043f3d62187b5d1de03mlf * on the channel.
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama uint32_t *nvc_mcp5x_ncq; /* NCQ status control bits */
8d483882aa3390058094b043f3d62187b5d1de03mlf ddi_intr_handle_t *nvc_htable; /* For array of interrupts */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama uint8_t *nvc_ck804_int_status; /* interrupt status ck804 */
8d483882aa3390058094b043f3d62187b5d1de03mlf sata_hba_tran_t nvc_sata_hba_tran; /* sata_hba_tran for ctrl */
8d483882aa3390058094b043f3d62187b5d1de03mlf * enable/disable interrupts, controller specific
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama int nvc_mcp5x_flag; /* is the controller MCP51/MCP55 */
3f318a288186db82aae78875c429f248622cf19fAlan Perry uint8_t nvc_ctlr_num; /* controller number within the part */
3f318a288186db82aae78875c429f248622cf19fAlan Perry uint32_t nvc_sgp_csr; /* SGPIO CSR i/o address */
a150bf8532245eea0ae6e08e711e1f62c0a30adcAlan Perry volatile nv_sgp_cb_t *nvc_sgp_cbp; /* SGPIO Control Block */
3f318a288186db82aae78875c429f248622cf19fAlan Perry nv_sgp_cmn_t *nvc_sgp_cmn; /* SGPIO shared data */
8d483882aa3390058094b043f3d62187b5d1de03mlf struct nv_ctl *nvp_ctlp; /* back pointer to controller */
7798b2a0723f7ed75e6d4a86f0821b4173930eb5Martin Faltesek uint8_t nvp_port_num; /* port number, ie 0 or 1 */
8d483882aa3390058094b043f3d62187b5d1de03mlf uint8_t nvp_type; /* SATA_DTYPE_{NONE,ATADISK,UNKNOWN} */
8d483882aa3390058094b043f3d62187b5d1de03mlf uint32_t nvp_signature; /* sig acquired from task file regs */
8d483882aa3390058094b043f3d62187b5d1de03mlf uchar_t *nvp_cmd_addr; /* base addr for cmd regs for port */
8d483882aa3390058094b043f3d62187b5d1de03mlf uchar_t *nvp_bm_addr; /* base addr for bus master for port */
8d483882aa3390058094b043f3d62187b5d1de03mlf uchar_t *nvp_ctl_addr; /* base addr for ctrl regs for port */
8d483882aa3390058094b043f3d62187b5d1de03mlf ddi_dma_handle_t *nvp_sg_dma_hdl; /* dma handle to prd table */
8d483882aa3390058094b043f3d62187b5d1de03mlf uint32_t *nvp_sg_paddr; /* physical address of prd table */
8d483882aa3390058094b043f3d62187b5d1de03mlf ddi_acc_handle_t *nvp_sg_acc_hdl; /* mem acc handle to the prd table */
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek kcondvar_t nvp_sync_cv; /* handshake btwn ISR and start thrd */
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek kcondvar_t nvp_reset_cv; /* when reset is synchronous */
8d483882aa3390058094b043f3d62187b5d1de03mlf * nvp_slot is a pointer to an array of nv_slot
8d483882aa3390058094b043f3d62187b5d1de03mlf * NCQ flow control. During NCQ operation, no other commands
8d483882aa3390058094b043f3d62187b5d1de03mlf * allowed. The following are used to enforce this.
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek clock_t nvp_reset_time; /* time of last reset */
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek clock_t nvp_link_event_time; /* time of last plug event */
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek clock_t nvp_wait_sig; /* wait before rechecking sig */
3f318a288186db82aae78875c429f248622cf19fAlan Perry uint8_t nvp_sgp_ioctl_mod; /* LEDs modified by ioctl */
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek * debug and statistical information
a9d5ae2e08c504913c088349c3d4c144f3c92be8Pawel Wojcik clock_t intr_duration; /* max length of port intr (ticks) */
8d483882aa3390058094b043f3d62187b5d1de03mlftypedef struct nv_device_table {
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama ushort_t type; /* chipset type, ck804 or mcp51/mcp55 */
8d483882aa3390058094b043f3d62187b5d1de03mlftypedef struct nv_slot {
8d483882aa3390058094b043f3d62187b5d1de03mlf size_t nvslot_byte_count; /* # bytes left to read/write */
3f318a288186db82aae78875c429f248622cf19fAlan Perry uint8_t nvs_in_use; /* bit-field of active ctlrs */
3f318a288186db82aae78875c429f248622cf19fAlan Perry uint8_t nvs_connected; /* port connected bit-field flag */
3f318a288186db82aae78875c429f248622cf19fAlan Perry uint8_t nvs_activity; /* port usage bit-field flag */
3f318a288186db82aae78875c429f248622cf19fAlan Perry int nvs_taskq_delay; /* rest time for activity LED taskq */
3f318a288186db82aae78875c429f248622cf19fAlan Perry kcondvar_t nvs_cv; /* condition variable for taskq wait */
a150bf8532245eea0ae6e08e711e1f62c0a30adcAlan Perry uint32_t c2cm_cbp; /* ctlr block ptr from pci cfg space */
a150bf8532245eea0ae6e08e711e1f62c0a30adcAlan Perry nv_sgp_cmn_t *c2cm_cmn; /* point to common space */
8d483882aa3390058094b043f3d62187b5d1de03mlf * nvslot_flags
b5fc475bca6525d8da80728128eefb7100aaf66bap#define NVSLOT_RQSENSE 0x04 /* processing request sense */
8d483882aa3390058094b043f3d62187b5d1de03mlf * state values for nv_attach
8d483882aa3390058094b043f3d62187b5d1de03mlf#endif /* DEBUG */
8d483882aa3390058094b043f3d62187b5d1de03mlf * nv_debug_flags
7798b2a0723f7ed75e6d4a86f0821b4173930eb5Martin Faltesek#define NVLOG(flag, nvc, nvp, fmt, args ...) \
8d483882aa3390058094b043f3d62187b5d1de03mlf * indicates whether nv_wait functions can sleep or not.
8d483882aa3390058094b043f3d62187b5d1de03mlf * port offsets from base address ioaddr1
8d483882aa3390058094b043f3d62187b5d1de03mlf * port offsets from base address ioaddr2
8d483882aa3390058094b043f3d62187b5d1de03mlf * device control register
8d483882aa3390058094b043f3d62187b5d1de03mlf#define ATDC_HOB 0x80 /* high order byte to read 48-bit values */
a9d5ae2e08c504913c088349c3d4c144f3c92be8Pawel Wojcik * MCP5x NCQ and INTR control registers
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define MCP5X_CTL 0x400 /* queuing control */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define MCP5X_INT_STATUS 0x440 /* status bits for interrupt */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define MCP5X_INT_CTL 0x444 /* enable bits for interrupt */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define MCP5X_NCQ 0x448 /* NCQ status and ctrl bits */
8d483882aa3390058094b043f3d62187b5d1de03mlf * if either of these bits are set, when using NCQ, if no other commands are
8d483882aa3390058094b043f3d62187b5d1de03mlf * active while a new command is started, DMA engine can be programmed ahead
8d483882aa3390058094b043f3d62187b5d1de03mlf * of time to save extra interrupt. Presumably pre-programming is discarded
8d483882aa3390058094b043f3d62187b5d1de03mlf * if a subsequent command ends up finishing first.
8d483882aa3390058094b043f3d62187b5d1de03mlf * bit definitions to indicate which NCQ command requires
8d483882aa3390058094b043f3d62187b5d1de03mlf * DMA setup.
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama * Bits for NV_MCP5X_INT_CTL and NV_MCP5X_INT_STATUS
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define MCP5X_INT_SNOTIFY 0x200 /* snotification set */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define MCP5X_INT_SERROR 0x100 /* serror set */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define MCP5X_INT_DMA_SETUP 0x80 /* DMA to be programmed */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define MCP5X_INT_DH_REGFIS 0x40 /* REGFIS received */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define MCP5X_INT_SDB_FIS 0x20 /* SDB FIS */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define MCP5X_INT_TX_BACKOUT 0x10 /* TX backout */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define MCP5X_INT_REM 0x08 /* device removed */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define MCP5X_INT_ADD 0x04 /* device added */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define MCP5X_INT_PM 0x02 /* power changed */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define MCP5X_INT_COMPLETE 0x01 /* device interrupt */
8d483882aa3390058094b043f3d62187b5d1de03mlf * Bits above that are not used for now.
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define MCP5X_INT_IGNORE (MCP5X_INT_DMA_SETUP|MCP5X_INT_DH_REGFIS|\
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama MCP5X_INT_SDB_FIS|MCP5X_INT_TX_BACKOUT|MCP5X_INT_PM|\
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama MCP5X_INT_SNOTIFY|MCP5X_INT_SERROR)
8d483882aa3390058094b043f3d62187b5d1de03mlf * Bits for MCP_SATA_AE_CTL
8d483882aa3390058094b043f3d62187b5d1de03mlf#define MCP_SATA_AE_CTL_PRI_SWNCQ (1 << 1) /* software NCQ chan 0 */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define MCP_SATA_AE_CTL_SEC_SWNCQ (1 << 2) /* software NCQ chan 1 */
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek * signature in task file registers after device reset
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama * These bar5 offsets are common to mcp51/mcp55/ck804 and thus
8d483882aa3390058094b043f3d62187b5d1de03mlf * prefixed with NV.
8d483882aa3390058094b043f3d62187b5d1de03mlf * The following config space offsets are needed to enable
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama * bar 5 register access in ck804/mcp51/mcp55
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama * ck804 interrupt status register
8d483882aa3390058094b043f3d62187b5d1de03mlf * offsets to bar 5 registers
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_SATA_INT_STATUS 0x440
8d483882aa3390058094b043f3d62187b5d1de03mlf * bit fields for int status and int enable
8d483882aa3390058094b043f3d62187b5d1de03mlf * registers
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_INT_PDEV_INT 0x01 /* completion interrupt */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_INT_PDEV_PM 0x02 /* power change */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_INT_PDEV_ADD 0x04 /* hot plug */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_INT_PDEV_REM 0x08 /* hot remove */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_INT_PDEV_HOT CK804_INT_PDEV_ADD|CK804_INT_PDEV_REM
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_INT_SDEV_INT 0x10 /* completion interrupt */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_INT_SDEV_PM 0x20 /* power change */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_INT_SDEV_ADD 0x40 /* hot plug */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_INT_SDEV_REM 0x80 /* hot remove */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_INT_SDEV_HOT CK804_INT_SDEV_ADD|CK804_INT_SDEV_REM
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_INT_PDEV_ALL CK804_INT_PDEV_INT|CK804_INT_PDEV_HOT|\
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_INT_SDEV_ALL CK804_INT_SDEV_INT|CK804_INT_SDEV_HOT|\
8d483882aa3390058094b043f3d62187b5d1de03mlf * config space offset 42
8d483882aa3390058094b043f3d62187b5d1de03mlf * bit in CFG_42 which delays hotplug interrupt until
8d483882aa3390058094b043f3d62187b5d1de03mlf * PHY ready
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_CFG_DELAY_HOTPLUG_INTR (0x1 << 12)
8d483882aa3390058094b043f3d62187b5d1de03mlf * bar 5 offsets for SATA registers in ck804
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_CH1_SNOTIFICATION 0x10
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_CH2_SNOTIFICATION 0x50
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama * bar 5 offsets for ADMACTL settings for both ck804/mcp51/mcp/55
8d483882aa3390058094b043f3d62187b5d1de03mlf * Bits for NV_ADMACTL_X and NV_ADMACTL_Y
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_HIRQ_EN 0x01 /* hot plug/unplug interrupt enable */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama * bar 5 offset for ADMASTAT regs for ck804
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama * Bits for CK804_ADMASTAT_X and CK804_ADMASTAT_Y
8d483882aa3390058094b043f3d62187b5d1de03mlf * bar 4 offset to bus master command registers
8d483882aa3390058094b043f3d62187b5d1de03mlf * bit definitions for BMICX_REG
8d483882aa3390058094b043f3d62187b5d1de03mlf /* 1=Start (Enable) */
8d483882aa3390058094b043f3d62187b5d1de03mlf /* 0=Start (Disable) */
8d483882aa3390058094b043f3d62187b5d1de03mlf * NOTE: "read" and "write" are the actions of the DMA engine
8d483882aa3390058094b043f3d62187b5d1de03mlf * on the PCI bus, not the SATA bus. Therefore for a ATA READ
8d483882aa3390058094b043f3d62187b5d1de03mlf * command, program the DMA engine to "write to memory" mode
8d483882aa3390058094b043f3d62187b5d1de03mlf * (and vice versa).
8d483882aa3390058094b043f3d62187b5d1de03mlf#define BMICX_RWCON_WRITE_TO_MEMORY 0x08 /* 1=Write (dev to host) */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define BMICX_RWCON_READ_FROM_MEMORY 0x00 /* 0=Read (host to dev) */
8d483882aa3390058094b043f3d62187b5d1de03mlf * BMICX bits to preserve during updates
8d483882aa3390058094b043f3d62187b5d1de03mlf * bar 4 offset to bus master status register
8d483882aa3390058094b043f3d62187b5d1de03mlf * bit fields for bus master status register
8d483882aa3390058094b043f3d62187b5d1de03mlf * bus master status register bits to preserve
8d483882aa3390058094b043f3d62187b5d1de03mlf * bar4 offset to bus master PRD descriptor table
8d483882aa3390058094b043f3d62187b5d1de03mlf * structure for a single entry in the PRD table
8d483882aa3390058094b043f3d62187b5d1de03mlf * (physical region descriptor table)
8d483882aa3390058094b043f3d62187b5d1de03mlftypedef struct prde {
8d483882aa3390058094b043f3d62187b5d1de03mlf uint32_t p_count; /* byte count, EOT in high order bit */
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek#define NV_DMA_NSEGS 257 /* at least 1MB (4KB/pg * 256) + 1 if misaligned */
8d483882aa3390058094b043f3d62187b5d1de03mlf * ck804 and mcp55 both have 2 ports per controller
8d483882aa3390058094b043f3d62187b5d1de03mlf * Number of slots to allocate in data nv_sata structures to handle
8d483882aa3390058094b043f3d62187b5d1de03mlf * multiple commands at once. This does not reflect the capability of
8d483882aa3390058094b043f3d62187b5d1de03mlf * the drive or the hardware, and in many cases will not match.
8d483882aa3390058094b043f3d62187b5d1de03mlf * 1 or 32 slots are allocated, so in cases where the driver has NCQ
8d483882aa3390058094b043f3d62187b5d1de03mlf * enabled but the drive doesn't support it, or supports fewer than
8d483882aa3390058094b043f3d62187b5d1de03mlf * 32 slots, here may be an over allocation of memory.
a9d5ae2e08c504913c088349c3d4c144f3c92be8Pawel Wojcik#define NV_MAX_INTR_PER_DEV 20 /* Empirical value */
a9d5ae2e08c504913c088349c3d4c144f3c92be8Pawel Wojcik * 1 second (in microseconds)
a9d5ae2e08c504913c088349c3d4c144f3c92be8Pawel Wojcik * 1 millisecond (in microseconds)
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek * initial wait before checking for signature, in microseconds
a9d5ae2e08c504913c088349c3d4c144f3c92be8Pawel Wojcik * Length of port reset (microseconds) - SControl bit 0 set to 1
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek * the maximum number of comresets to issue while
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek * performing link reset in nv_reset()
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek * amount of time to wait for a signature in reset, in ms, before
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek * issuing another reset
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek * the maximum number of resets to issue to gather signature
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek * before giving up
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek * amount of time (us) to wait after receiving a link event
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek * before acting on it. This is because of flakey hardware
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek * sometimes issues the wrong, multiple, or out of order link
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek * The amount of time (ms) a link can be missing
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek * before declaring it removed.
8d483882aa3390058094b043f3d62187b5d1de03mlf * nvp_state flags
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek * flags for nv_report_link_event()
8d483882aa3390058094b043f3d62187b5d1de03mlf * nvc_state flags
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama * flags for ck804_set_intr/mcp5x_set_intr
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_ATA_NUM_CMDS 256 /* max num ATA cmds possible, 8 bits */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_PRINT_INTERVAL 40 /* throttle debug msg from flooding */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define MCP5X_INT_CLEAR 0xffff /* clear all interrupts */
8d483882aa3390058094b043f3d62187b5d1de03mlf * definition labels for the BAR registers
8d483882aa3390058094b043f3d62187b5d1de03mlf * transform seconds to microseconds
8d483882aa3390058094b043f3d62187b5d1de03mlf * ck804 maps in task file regs into bar 5. These are
8d483882aa3390058094b043f3d62187b5d1de03mlf * only used to identify ck804, therefore only this reg is
8d483882aa3390058094b043f3d62187b5d1de03mlf * listed here.
8d483882aa3390058094b043f3d62187b5d1de03mlf * if after this many iterations through the interrupt
8d483882aa3390058094b043f3d62187b5d1de03mlf * processing loop, declare the interrupt wedged and
8d483882aa3390058094b043f3d62187b5d1de03mlf * disable.
8d483882aa3390058094b043f3d62187b5d1de03mlf * flag values for nv_copy_regs_out
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_COPY_COMPLETE 0x01 /* normal command completion */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_COPY_ERROR 0x02 /* error, did not complete ok */
a150bf8532245eea0ae6e08e711e1f62c0a30adcAlan Perry#define NV_MAX_CBPS 16 /* Maximum # of Control Block */
a150bf8532245eea0ae6e08e711e1f62c0a30adcAlan Perry /* Pointers. Corresponds to */
a150bf8532245eea0ae6e08e711e1f62c0a30adcAlan Perry /* each MCP55 and IO55 */
3f318a288186db82aae78875c429f248622cf19fAlan Perry#define SGPIO_LOOP_WAIT_USECS 62500 /* 1/16 second (in usecs) */
3f318a288186db82aae78875c429f248622cf19fAlan Perry * The drive number format is ccp (binary).
3f318a288186db82aae78875c429f248622cf19fAlan Perry * cc is the controller number (0-based number)
3f318a288186db82aae78875c429f248622cf19fAlan Perry * p is the port number (0 or 1)
3f318a288186db82aae78875c429f248622cf19fAlan Perry#define SGP_CTLR_PORT_TO_DRV(c, p) (((c) << 1) | ((p) & 1))
8d483882aa3390058094b043f3d62187b5d1de03mlf#endif /* _NV_SATA_H */