nv_sata.h revision 193974072f41a843678abf5f61979c748687e66b
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613a2f6ba31e891e3d947a356daf5e563d43c1ceGordon Ross * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * Use is subject to license terms.
4bff34e37def8a90f9194d81bc345c52ba20086athurlowextern "C" {
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * SGPIO Support
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * Enable SGPIO support only on x86/x64, because it is implemented using
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * functions that are only available on x86/x64.
4bff34e37def8a90f9194d81bc345c52ba20086athurlow#define NV_MAX_PORTS(nvc) nvc->nvc_sata_hba_tran.sata_tran_hba_num_cports
4bff34e37def8a90f9194d81bc345c52ba20086athurlowtypedef struct nv_ctl {
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * Each of these are specific to the chipset in use.
4bff34e37def8a90f9194d81bc345c52ba20086athurlow uint_t (*nvc_interrupt)(caddr_t arg1, caddr_t arg2);
4bff34e37def8a90f9194d81bc345c52ba20086athurlow dev_info_t *nvc_dip; /* devinfo pointer of controller */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow struct nv_port *nvc_port; /* array of pointers to port struct */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * handle and base address to register space.
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * 0: port 0 task file
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * 1: port 0 status
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * 2: port 1 task file
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * 3: port 1 status
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * 4: bus master for both ports
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * 5: extended registers for SATA features
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * sata registers in bar 5 which are shared on all devices
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * on the channel.
4bff34e37def8a90f9194d81bc345c52ba20086athurlow uint32_t *nvc_mcp55_ncq; /* NCQ status control bits */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow ddi_intr_handle_t *nvc_htable; /* For array of interrupts */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow uint8_t *nvc_mcp04_int_status; /* interrupt status mcp04 */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow sata_hba_tran_t nvc_sata_hba_tran; /* sata_hba_tran for ctrl */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * enable/disable interrupts, controller specific
4bff34e37def8a90f9194d81bc345c52ba20086athurlow int nvc_mcp55_flag; /* is the controller MCP55 or CK804 */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow uint8_t nvc_ctlr_num; /* controller number within the part */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow volatile nv_sgp_cb_t *nvc_sgp_cbp; /* SGPIO Command Block */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow struct nv_ctl *nvp_ctlp; /* back pointer to controller */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow uint8_t nvp_type; /* SATA_DTYPE_{NONE,ATADISK,UNKNOWN} */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow uint32_t nvp_signature; /* sig acquired from task file regs */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow uchar_t *nvp_cmd_addr; /* base addr for cmd regs for port */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow uchar_t *nvp_bm_addr; /* base addr for bus master for port */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow uchar_t *nvp_ctl_addr; /* base addr for ctrl regs for port */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow uchar_t *nvp_altstatus; /* alternate status (read) */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow ddi_dma_handle_t *nvp_sg_dma_hdl; /* dma handle to prd table */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow caddr_t *nvp_sg_addr; /* virtual addr of prd table */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow uint32_t *nvp_sg_paddr; /* physical address of prd table */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow ddi_acc_handle_t *nvp_sg_acc_hdl; /* mem acc handle to the prd table */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow kcondvar_t nvp_poll_cv; /* handshake cv between poll & isr */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * nvp_slot is a pointer to an array of nv_slot
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * NCQ flow control. During NCQ operation, no other commands
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * allowed. The following are used to enforce this.
4bff34e37def8a90f9194d81bc345c52ba20086athurlow clock_t nvp_link_lost_time; /* time link lost was noticed */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow int nvp_state; /* state of port. flags defined below */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow uint8_t nvp_sgp_ioctl_mod; /* LEDs modified by ioctl */
4bff34e37def8a90f9194d81bc345c52ba20086athurlowtypedef struct nv_device_table {
4bff34e37def8a90f9194d81bc345c52ba20086athurlowtypedef struct nv_slot {
4bff34e37def8a90f9194d81bc345c52ba20086athurlow size_t nvslot_byte_count; /* # bytes left to read/write */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow uint8_t nvslot_rqsense_buff[SATA_ATAPI_RQSENSE_LEN];
4bff34e37def8a90f9194d81bc345c52ba20086athurlow uint16_t nvs_magic; /* verification of valid structure */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow uint8_t nvs_connected; /* port connected bit-field flag */
613a2f6ba31e891e3d947a356daf5e563d43c1ceGordon Ross uint8_t nvs_activity; /* port usage bit-field flag */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow int nvs_taskq_delay; /* rest time for activity LED taskq */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow kcondvar_t nvs_cv; /* condition variable for taskq wait */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * nvslot_flags
4bff34e37def8a90f9194d81bc345c52ba20086athurlow#define NVSLOT_RQSENSE 0x04 /* processing request sense */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * state values for nv_attach
613a2f6ba31e891e3d947a356daf5e563d43c1ceGordon Ross#endif /* DEBUG */
613a2f6ba31e891e3d947a356daf5e563d43c1ceGordon Ross * nv_debug_flags
613a2f6ba31e891e3d947a356daf5e563d43c1ceGordon Ross * indicates whether nv_wait functions can sleep or not.
613a2f6ba31e891e3d947a356daf5e563d43c1ceGordon Ross * port offsets from base address ioaddr1
613a2f6ba31e891e3d947a356daf5e563d43c1ceGordon Ross#define NV_ERROR 0x01 /* error register (read) */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * port offsets from base address ioaddr2
4bff34e37def8a90f9194d81bc345c52ba20086athurlow#define NV_ALTSTATUS 0x02 /* alternate status (read) */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * device control register
4bff34e37def8a90f9194d81bc345c52ba20086athurlow#define ATDC_HOB 0x80 /* high order byte to read 48-bit values */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow#define MCP55_INT_STATUS 0x440 /* status bits for interrupt */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow#define MCP55_INT_CTL 0x444 /* enable bits for interrupt */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow#define MCP55_NCQ 0x448 /* NCQ status and ctrl bits */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * if either of these bits are set, when using NCQ, if no other commands are
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * active while a new command is started, DMA engine can be programmed ahead
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * of time to save extra interrupt. Presumably pre-programming is discarded
613a2f6ba31e891e3d947a356daf5e563d43c1ceGordon Ross * if a subsequent command ends up finishing first.
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * bit definitions to indicate which NCQ command requires
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * DMA setup.
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * Bits for NV_MCP55_INT_CTL and NV_MCP55_INT_STATUS
4bff34e37def8a90f9194d81bc345c52ba20086athurlow#define MCP55_INT_SNOTIFY 0x200 /* snotification set */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow#define MCP55_INT_DMA_SETUP 0x80 /* DMA to be programmed */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow#define MCP55_INT_DH_REGFIS 0x40 /* REGFIS received */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow#define MCP55_INT_COMPLETE 0x01 /* device interrupt */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * Bits above that are not used for now.
4bff34e37def8a90f9194d81bc345c52ba20086athurlow#define MCP55_INT_IGNORE (MCP55_INT_DMA_SETUP|MCP55_INT_DH_REGFIS|\
4bff34e37def8a90f9194d81bc345c52ba20086athurlow MCP55_INT_SDB_FIS|MCP55_INT_TX_BACKOUT|MCP55_INT_PM|\
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * Bits for MCP_SATA_AE_CTL
4bff34e37def8a90f9194d81bc345c52ba20086athurlow#define MCP_SATA_AE_CTL_PRI_SWNCQ (1 << 1) /* software NCQ chan 0 */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow#define MCP_SATA_AE_CTL_SEC_SWNCQ (1 << 2) /* software NCQ chan 1 */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * signatures in task file registers after device reset
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * These bar5 offsets are common to mcp55/mcp04 and thus
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * prefixed with NV.
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * The following config space offsets are needed to enable
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * bar 5 register access in mcp04/mcp55
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * mcp04 interrupt status register
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * offsets to bar 5 registers
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * bit fields for int status and int enable
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * registers
4bff34e37def8a90f9194d81bc345c52ba20086athurlow#define MCP04_INT_PDEV_INT 0x01 /* completion interrupt */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow#define MCP04_INT_PDEV_HOT MCP04_INT_PDEV_ADD|MCP04_INT_PDEV_REM
4bff34e37def8a90f9194d81bc345c52ba20086athurlow#define MCP04_INT_SDEV_INT 0x10 /* completion interrupt */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow#define MCP04_INT_SDEV_HOT MCP04_INT_SDEV_ADD|MCP04_INT_SDEV_REM
4bff34e37def8a90f9194d81bc345c52ba20086athurlow#define MCP04_INT_PDEV_ALL MCP04_INT_PDEV_INT|MCP04_INT_PDEV_HOT|\
4bff34e37def8a90f9194d81bc345c52ba20086athurlow#define MCP04_INT_SDEV_ALL MCP04_INT_SDEV_INT|MCP04_INT_SDEV_HOT|\
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * config space offset 42
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * bit in CFG_42 which delays hotplug interrupt until
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * PHY ready
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * bar 5 offsets for SATA registers in ck804
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * bar 5 offsets for ADMACTL settings for both mcp04/mcp55
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * Bits for NV_ADMACTL_X and NV_ADMACTL_Y
4bff34e37def8a90f9194d81bc345c52ba20086athurlow#define NV_HIRQ_EN 0x01 /* hot plug/unplug interrupt enable */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * bar 5 offset for ADMASTAT regs for mcp04
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * Bits for MCP04_ADMASTAT_X and MCP04_ADMASTAT_Y
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * bar 4 offset to bus master command registers
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * bit definitions for BMICX_REG
4bff34e37def8a90f9194d81bc345c52ba20086athurlow /* 1=Start (Enable) */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow /* 0=Start (Disable) */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * NOTE: "read" and "write" are the actions of the DMA engine
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * on the PCI bus, not the SATA bus. Therefore for a ATA READ
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * command, program the DMA engine to "write to memory" mode
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * (and vice versa).
4bff34e37def8a90f9194d81bc345c52ba20086athurlow#define BMICX_RWCON_WRITE_TO_MEMORY 0x08 /* 1=Write (dev to host) */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow#define BMICX_RWCON_READ_FROM_MEMORY 0x00 /* 0=Read (host to dev) */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * BMICX bits to preserve during updates
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * bar 4 offset to bus master status register
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * bit fields for bus master status register
4bff34e37def8a90f9194d81bc345c52ba20086athurlow#define BMISX_BMIDEA 0x01 /* Bus Master IDE Active */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow#define BMISX_IDEINTS 0x04 /* IDE Interrupt Status */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * bus master status register bits to preserve
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * bar4 offset to bus master PRD descriptor table
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * structure for a single entry in the PRD table
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * (physical region descriptor table)
4bff34e37def8a90f9194d81bc345c52ba20086athurlowtypedef struct prde {
4bff34e37def8a90f9194d81bc345c52ba20086athurlow uint32_t p_count; /* byte count, EOT in high order bit */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow#define NV_DMA_NSEGS 256 /* XXX DEBUG TEST change back to 257 */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * ck804 and mcp55 both have 2 ports per controller
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * Number of slots to allocate in data nv_sata structures to handle
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * multiple commands at once. This does not reflect the capability of
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * the drive or the hardware, and in many cases will not match.
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * 1 or 32 slots are allocated, so in cases where the driver has NCQ
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * enabled but the drive doesn't support it, or supports fewer than
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * 32 slots, here may be an over allocation of memory.
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * wait 30 seconds for signature
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * every 1 second
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * the amount of time link can be down during
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * reset without taking action.
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * nv_reset() flags
4bff34e37def8a90f9194d81bc345c52ba20086athurlow#define NV_RESET_SEND_EVENT 0x1 /* send reset event to sata module */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow#define NV_RESET_WAIT 0x2 /* OK to block waiting for reset */
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * nvp_state flags
4bff34e37def8a90f9194d81bc345c52ba20086athurlow * nvc_state flags
* flags for mcp04_set_intr/mcp55_set_intr
#ifdef SGPIO_SUPPORT
#ifdef __cplusplus