8d483882aa3390058094b043f3d62187b5d1de03mlf/*
8d483882aa3390058094b043f3d62187b5d1de03mlf * CDDL HEADER START
8d483882aa3390058094b043f3d62187b5d1de03mlf *
8d483882aa3390058094b043f3d62187b5d1de03mlf * The contents of this file are subject to the terms of the
8d483882aa3390058094b043f3d62187b5d1de03mlf * Common Development and Distribution License (the "License").
8d483882aa3390058094b043f3d62187b5d1de03mlf * You may not use this file except in compliance with the License.
8d483882aa3390058094b043f3d62187b5d1de03mlf *
8d483882aa3390058094b043f3d62187b5d1de03mlf * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
8d483882aa3390058094b043f3d62187b5d1de03mlf * or http://www.opensolaris.org/os/licensing.
8d483882aa3390058094b043f3d62187b5d1de03mlf * See the License for the specific language governing permissions
8d483882aa3390058094b043f3d62187b5d1de03mlf * and limitations under the License.
8d483882aa3390058094b043f3d62187b5d1de03mlf *
8d483882aa3390058094b043f3d62187b5d1de03mlf * When distributing Covered Code, include this CDDL HEADER in each
8d483882aa3390058094b043f3d62187b5d1de03mlf * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
8d483882aa3390058094b043f3d62187b5d1de03mlf * If applicable, add the following below this CDDL HEADER, with the
8d483882aa3390058094b043f3d62187b5d1de03mlf * fields enclosed by brackets "[]" replaced with your own identifying
8d483882aa3390058094b043f3d62187b5d1de03mlf * information: Portions Copyright [yyyy] [name of copyright owner]
8d483882aa3390058094b043f3d62187b5d1de03mlf *
8d483882aa3390058094b043f3d62187b5d1de03mlf * CDDL HEADER END
8d483882aa3390058094b043f3d62187b5d1de03mlf */
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
7798b2a0723f7ed75e6d4a86f0821b4173930eb5Martin Faltesek * Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved.
8d483882aa3390058094b043f3d62187b5d1de03mlf */
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf#ifndef _NV_SATA_H
8d483882aa3390058094b043f3d62187b5d1de03mlf#define _NV_SATA_H
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf#ifdef __cplusplus
8d483882aa3390058094b043f3d62187b5d1de03mlfextern "C" {
8d483882aa3390058094b043f3d62187b5d1de03mlf#endif
8d483882aa3390058094b043f3d62187b5d1de03mlf
3f318a288186db82aae78875c429f248622cf19fAlan Perry
3f318a288186db82aae78875c429f248622cf19fAlan Perry/*
3f318a288186db82aae78875c429f248622cf19fAlan Perry * SGPIO Support
3f318a288186db82aae78875c429f248622cf19fAlan Perry * Enable SGPIO support only on x86/x64, because it is implemented using
3f318a288186db82aae78875c429f248622cf19fAlan Perry * functions that are only available on x86/x64.
3f318a288186db82aae78875c429f248622cf19fAlan Perry */
3f318a288186db82aae78875c429f248622cf19fAlan Perry
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_MAX_PORTS(nvc) nvc->nvc_sata_hba_tran.sata_tran_hba_num_cports
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlftypedef struct nv_port nv_port_t;
8d483882aa3390058094b043f3d62187b5d1de03mlf
3f318a288186db82aae78875c429f248622cf19fAlan Perry#ifdef SGPIO_SUPPORT
3f318a288186db82aae78875c429f248622cf19fAlan Perrytypedef struct nv_sgp_cmn nv_sgp_cmn_t;
3f318a288186db82aae78875c429f248622cf19fAlan Perry#endif
3f318a288186db82aae78875c429f248622cf19fAlan Perry
7798b2a0723f7ed75e6d4a86f0821b4173930eb5Martin Faltesek/*
7798b2a0723f7ed75e6d4a86f0821b4173930eb5Martin Faltesek * sizes of strings to allocate
7798b2a0723f7ed75e6d4a86f0821b4173930eb5Martin Faltesek */
7798b2a0723f7ed75e6d4a86f0821b4173930eb5Martin Faltesek#define NV_STR_LEN 10
7798b2a0723f7ed75e6d4a86f0821b4173930eb5Martin Faltesek#define NV_LOGBUF_LEN 512
7798b2a0723f7ed75e6d4a86f0821b4173930eb5Martin Faltesek#define NV_REASON_LEN 30
7798b2a0723f7ed75e6d4a86f0821b4173930eb5Martin Faltesek
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek
8d483882aa3390058094b043f3d62187b5d1de03mlftypedef struct nv_ctl {
8d483882aa3390058094b043f3d62187b5d1de03mlf /*
8d483882aa3390058094b043f3d62187b5d1de03mlf * Each of these are specific to the chipset in use.
8d483882aa3390058094b043f3d62187b5d1de03mlf */
8d483882aa3390058094b043f3d62187b5d1de03mlf uint_t (*nvc_interrupt)(caddr_t arg1, caddr_t arg2);
8d483882aa3390058094b043f3d62187b5d1de03mlf void (*nvc_reg_init)(struct nv_ctl *nvc,
8d483882aa3390058094b043f3d62187b5d1de03mlf ddi_acc_handle_t pci_conf_handle);
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf dev_info_t *nvc_dip; /* devinfo pointer of controller */
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf struct nv_port *nvc_port; /* array of pointers to port struct */
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf /*
8d483882aa3390058094b043f3d62187b5d1de03mlf * handle and base address to register space.
8d483882aa3390058094b043f3d62187b5d1de03mlf *
8d483882aa3390058094b043f3d62187b5d1de03mlf * 0: port 0 task file
8d483882aa3390058094b043f3d62187b5d1de03mlf * 1: port 0 status
8d483882aa3390058094b043f3d62187b5d1de03mlf * 2: port 1 task file
8d483882aa3390058094b043f3d62187b5d1de03mlf * 3: port 1 status
8d483882aa3390058094b043f3d62187b5d1de03mlf * 4: bus master for both ports
8d483882aa3390058094b043f3d62187b5d1de03mlf * 5: extended registers for SATA features
8d483882aa3390058094b043f3d62187b5d1de03mlf */
8d483882aa3390058094b043f3d62187b5d1de03mlf ddi_acc_handle_t nvc_bar_hdl[6];
8d483882aa3390058094b043f3d62187b5d1de03mlf uchar_t *nvc_bar_addr[6];
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf /*
8d483882aa3390058094b043f3d62187b5d1de03mlf * sata registers in bar 5 which are shared on all devices
8d483882aa3390058094b043f3d62187b5d1de03mlf * on the channel.
8d483882aa3390058094b043f3d62187b5d1de03mlf */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama uint32_t *nvc_mcp5x_ctl;
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama uint32_t *nvc_mcp5x_ncq; /* NCQ status control bits */
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf kmutex_t nvc_mutex; /* ctrl level lock */
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf ddi_intr_handle_t *nvc_htable; /* For array of interrupts */
8d483882aa3390058094b043f3d62187b5d1de03mlf int nvc_intr_type; /* What type of interrupt */
8d483882aa3390058094b043f3d62187b5d1de03mlf int nvc_intr_cnt; /* # of intrs count returned */
8d483882aa3390058094b043f3d62187b5d1de03mlf size_t nvc_intr_size; /* Size of intr array to */
8d483882aa3390058094b043f3d62187b5d1de03mlf uint_t nvc_intr_pri; /* Interrupt priority */
8d483882aa3390058094b043f3d62187b5d1de03mlf int nvc_intr_cap; /* Interrupt capabilities */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama uint8_t *nvc_ck804_int_status; /* interrupt status ck804 */
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf sata_hba_tran_t nvc_sata_hba_tran; /* sata_hba_tran for ctrl */
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf /*
8d483882aa3390058094b043f3d62187b5d1de03mlf * enable/disable interrupts, controller specific
8d483882aa3390058094b043f3d62187b5d1de03mlf */
8d483882aa3390058094b043f3d62187b5d1de03mlf void (*nvc_set_intr)(nv_port_t *nvp, int flag);
8d483882aa3390058094b043f3d62187b5d1de03mlf int nvc_state; /* state flags of ctrl see below */
57454abe5526a6c53b58824f5aed89aa6ed1141bAlbert Lee uint16_t nvc_devid; /* PCI devid of device */
8d483882aa3390058094b043f3d62187b5d1de03mlf uint8_t nvc_revid; /* PCI revid of device */
742020134132bc958fa001d2bc8b5c137cadf629Guoli Shu boolean_t dma_40bit; /* 40bit DMA support */
57454abe5526a6c53b58824f5aed89aa6ed1141bAlbert Lee boolean_t nvc_mcp5x_flag; /* is the controller MCP51/MCP55 */
3f318a288186db82aae78875c429f248622cf19fAlan Perry
3f318a288186db82aae78875c429f248622cf19fAlan Perry#ifdef SGPIO_SUPPORT
3f318a288186db82aae78875c429f248622cf19fAlan Perry uint8_t nvc_ctlr_num; /* controller number within the part */
3f318a288186db82aae78875c429f248622cf19fAlan Perry uint32_t nvc_sgp_csr; /* SGPIO CSR i/o address */
a150bf8532245eea0ae6e08e711e1f62c0a30adcAlan Perry volatile nv_sgp_cb_t *nvc_sgp_cbp; /* SGPIO Control Block */
3f318a288186db82aae78875c429f248622cf19fAlan Perry nv_sgp_cmn_t *nvc_sgp_cmn; /* SGPIO shared data */
3f318a288186db82aae78875c429f248622cf19fAlan Perry#endif
8d483882aa3390058094b043f3d62187b5d1de03mlf} nv_ctl_t;
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlfstruct nv_port {
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf struct nv_ctl *nvp_ctlp; /* back pointer to controller */
8d483882aa3390058094b043f3d62187b5d1de03mlf
7798b2a0723f7ed75e6d4a86f0821b4173930eb5Martin Faltesek uint8_t nvp_port_num; /* port number, ie 0 or 1 */
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf uint8_t nvp_type; /* SATA_DTYPE_{NONE,ATADISK,UNKNOWN} */
8d483882aa3390058094b043f3d62187b5d1de03mlf uint32_t nvp_signature; /* sig acquired from task file regs */
8d483882aa3390058094b043f3d62187b5d1de03mlf uchar_t *nvp_cmd_addr; /* base addr for cmd regs for port */
8d483882aa3390058094b043f3d62187b5d1de03mlf uchar_t *nvp_bm_addr; /* base addr for bus master for port */
8d483882aa3390058094b043f3d62187b5d1de03mlf uchar_t *nvp_ctl_addr; /* base addr for ctrl regs for port */
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf ddi_acc_handle_t nvp_cmd_hdl;
8d483882aa3390058094b043f3d62187b5d1de03mlf uchar_t *nvp_data; /* data register */
8d483882aa3390058094b043f3d62187b5d1de03mlf uchar_t *nvp_error; /* error register (read) */
8d483882aa3390058094b043f3d62187b5d1de03mlf uchar_t *nvp_feature; /* features (write) */
8d483882aa3390058094b043f3d62187b5d1de03mlf uchar_t *nvp_count; /* sector count */
8d483882aa3390058094b043f3d62187b5d1de03mlf uchar_t *nvp_sect; /* sector number */
8d483882aa3390058094b043f3d62187b5d1de03mlf uchar_t *nvp_lcyl; /* cylinder low byte */
8d483882aa3390058094b043f3d62187b5d1de03mlf uchar_t *nvp_hcyl; /* cylinder high byte */
8d483882aa3390058094b043f3d62187b5d1de03mlf uchar_t *nvp_drvhd; /* drive/head register */
8d483882aa3390058094b043f3d62187b5d1de03mlf uchar_t *nvp_status; /* status/command register */
8d483882aa3390058094b043f3d62187b5d1de03mlf uchar_t *nvp_cmd; /* status/command register */
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf ddi_acc_handle_t nvp_ctl_hdl;
8d483882aa3390058094b043f3d62187b5d1de03mlf uchar_t *nvp_altstatus; /* alternate status (read) */
8d483882aa3390058094b043f3d62187b5d1de03mlf uchar_t *nvp_devctl; /* device control (write) */
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf ddi_acc_handle_t nvp_bm_hdl;
8d483882aa3390058094b043f3d62187b5d1de03mlf uchar_t *nvp_bmisx;
8d483882aa3390058094b043f3d62187b5d1de03mlf uint32_t *nvp_bmidtpx;
8d483882aa3390058094b043f3d62187b5d1de03mlf uchar_t *nvp_bmicx;
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf ddi_dma_handle_t *nvp_sg_dma_hdl; /* dma handle to prd table */
8d483882aa3390058094b043f3d62187b5d1de03mlf caddr_t *nvp_sg_addr; /* virtual addr of prd table */
8d483882aa3390058094b043f3d62187b5d1de03mlf uint32_t *nvp_sg_paddr; /* physical address of prd table */
8d483882aa3390058094b043f3d62187b5d1de03mlf ddi_acc_handle_t *nvp_sg_acc_hdl; /* mem acc handle to the prd table */
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf uint32_t *nvp_sstatus;
8d483882aa3390058094b043f3d62187b5d1de03mlf uint32_t *nvp_serror;
8d483882aa3390058094b043f3d62187b5d1de03mlf uint32_t *nvp_sctrl;
8d483882aa3390058094b043f3d62187b5d1de03mlf uint32_t *nvp_sactive;
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf kmutex_t nvp_mutex; /* main per port mutex */
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek kcondvar_t nvp_sync_cv; /* handshake btwn ISR and start thrd */
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek kcondvar_t nvp_reset_cv; /* when reset is synchronous */
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf /*
8d483882aa3390058094b043f3d62187b5d1de03mlf * nvp_slot is a pointer to an array of nv_slot
8d483882aa3390058094b043f3d62187b5d1de03mlf */
8d483882aa3390058094b043f3d62187b5d1de03mlf struct nv_slot *nvp_slot;
8d483882aa3390058094b043f3d62187b5d1de03mlf uint32_t nvp_sactive_cache; /* cache of SACTIVE */
8d483882aa3390058094b043f3d62187b5d1de03mlf uint8_t nvp_queue_depth;
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf /*
8d483882aa3390058094b043f3d62187b5d1de03mlf * NCQ flow control. During NCQ operation, no other commands
8d483882aa3390058094b043f3d62187b5d1de03mlf * allowed. The following are used to enforce this.
8d483882aa3390058094b043f3d62187b5d1de03mlf */
8d483882aa3390058094b043f3d62187b5d1de03mlf int nvp_ncq_run;
8d483882aa3390058094b043f3d62187b5d1de03mlf int nvp_non_ncq_run;
7798b2a0723f7ed75e6d4a86f0821b4173930eb5Martin Faltesek int nvp_seq;
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf timeout_id_t nvp_timeout_id;
8d483882aa3390058094b043f3d62187b5d1de03mlf
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek clock_t nvp_reset_time; /* time of last reset */
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek clock_t nvp_link_event_time; /* time of last plug event */
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek int nvp_reset_retry_count;
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek clock_t nvp_wait_sig; /* wait before rechecking sig */
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf int nvp_state; /* state of port. flags defined below */
8d483882aa3390058094b043f3d62187b5d1de03mlf
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama uint16_t *nvp_mcp5x_int_status;
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama uint16_t *nvp_mcp5x_int_ctl;
3f318a288186db82aae78875c429f248622cf19fAlan Perry
3f318a288186db82aae78875c429f248622cf19fAlan Perry#ifdef SGPIO_SUPPORT
3f318a288186db82aae78875c429f248622cf19fAlan Perry uint8_t nvp_sgp_ioctl_mod; /* LEDs modified by ioctl */
3f318a288186db82aae78875c429f248622cf19fAlan Perry#endif
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek clock_t nvp_timeout_duration;
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek /*
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek * debug and statistical information
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek */
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek clock_t nvp_rem_time;
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek clock_t nvp_add_time;
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek clock_t nvp_trans_link_time;
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek int nvp_trans_link_count;
a9d5ae2e08c504913c088349c3d4c144f3c92be8Pawel Wojcik
a9d5ae2e08c504913c088349c3d4c144f3c92be8Pawel Wojcik uint8_t nvp_last_cmd;
a9d5ae2e08c504913c088349c3d4c144f3c92be8Pawel Wojcik uint8_t nvp_previous_cmd;
a9d5ae2e08c504913c088349c3d4c144f3c92be8Pawel Wojcik int nvp_reset_count;
7798b2a0723f7ed75e6d4a86f0821b4173930eb5Martin Faltesek char nvp_first_reset_reason[NV_REASON_LEN];
7798b2a0723f7ed75e6d4a86f0821b4173930eb5Martin Faltesek char nvp_reset_reason[NV_REASON_LEN];
a9d5ae2e08c504913c088349c3d4c144f3c92be8Pawel Wojcik clock_t intr_duration; /* max length of port intr (ticks) */
a9d5ae2e08c504913c088349c3d4c144f3c92be8Pawel Wojcik clock_t intr_start_time;
a9d5ae2e08c504913c088349c3d4c144f3c92be8Pawel Wojcik int intr_loop_cnt;
8d483882aa3390058094b043f3d62187b5d1de03mlf};
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlftypedef struct nv_device_table {
8d483882aa3390058094b043f3d62187b5d1de03mlf ushort_t vendor_id; /* vendor id */
8d483882aa3390058094b043f3d62187b5d1de03mlf ushort_t device_id; /* device id */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama ushort_t type; /* chipset type, ck804 or mcp51/mcp55 */
8d483882aa3390058094b043f3d62187b5d1de03mlf} nv_device_table_t;
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlftypedef struct nv_slot {
8d483882aa3390058094b043f3d62187b5d1de03mlf caddr_t nvslot_v_addr; /* I/O buffer address */
8d483882aa3390058094b043f3d62187b5d1de03mlf size_t nvslot_byte_count; /* # bytes left to read/write */
8d483882aa3390058094b043f3d62187b5d1de03mlf sata_pkt_t *nvslot_spkt;
b5fc475bca6525d8da80728128eefb7100aaf66bap uint8_t nvslot_rqsense_buff[SATA_ATAPI_RQSENSE_LEN];
8d483882aa3390058094b043f3d62187b5d1de03mlf clock_t nvslot_stime;
8d483882aa3390058094b043f3d62187b5d1de03mlf int (*nvslot_start)(nv_port_t *nvp, int queue);
8d483882aa3390058094b043f3d62187b5d1de03mlf void (*nvslot_intr)(nv_port_t *nvp,
8d483882aa3390058094b043f3d62187b5d1de03mlf struct nv_slot *nv_slotp);
8d483882aa3390058094b043f3d62187b5d1de03mlf uint32_t nvslot_flags;
8d483882aa3390058094b043f3d62187b5d1de03mlf} nv_slot_t;
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf
3f318a288186db82aae78875c429f248622cf19fAlan Perry#ifdef SGPIO_SUPPORT
3f318a288186db82aae78875c429f248622cf19fAlan Perrystruct nv_sgp_cmn {
3f318a288186db82aae78875c429f248622cf19fAlan Perry uint8_t nvs_in_use; /* bit-field of active ctlrs */
3f318a288186db82aae78875c429f248622cf19fAlan Perry uint8_t nvs_connected; /* port connected bit-field flag */
3f318a288186db82aae78875c429f248622cf19fAlan Perry uint8_t nvs_activity; /* port usage bit-field flag */
a150bf8532245eea0ae6e08e711e1f62c0a30adcAlan Perry int nvs_cbp; /* SGPIO Control Block Pointer */
3f318a288186db82aae78875c429f248622cf19fAlan Perry int nvs_taskq_delay; /* rest time for activity LED taskq */
3f318a288186db82aae78875c429f248622cf19fAlan Perry kmutex_t nvs_slock; /* lock for shared data */
3f318a288186db82aae78875c429f248622cf19fAlan Perry kmutex_t nvs_tlock; /* lock for taskq */
3f318a288186db82aae78875c429f248622cf19fAlan Perry kcondvar_t nvs_cv; /* condition variable for taskq wait */
3f318a288186db82aae78875c429f248622cf19fAlan Perry ddi_taskq_t *nvs_taskq; /* activity LED taskq */
3f318a288186db82aae78875c429f248622cf19fAlan Perry};
a150bf8532245eea0ae6e08e711e1f62c0a30adcAlan Perry
a150bf8532245eea0ae6e08e711e1f62c0a30adcAlan Perrystruct nv_sgp_cbp2cmn {
a150bf8532245eea0ae6e08e711e1f62c0a30adcAlan Perry uint32_t c2cm_cbp; /* ctlr block ptr from pci cfg space */
a150bf8532245eea0ae6e08e711e1f62c0a30adcAlan Perry nv_sgp_cmn_t *c2cm_cmn; /* point to common space */
a150bf8532245eea0ae6e08e711e1f62c0a30adcAlan Perry};
3f318a288186db82aae78875c429f248622cf19fAlan Perry#endif
3f318a288186db82aae78875c429f248622cf19fAlan Perry
3f318a288186db82aae78875c429f248622cf19fAlan Perry
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
8d483882aa3390058094b043f3d62187b5d1de03mlf * nvslot_flags
8d483882aa3390058094b043f3d62187b5d1de03mlf */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NVSLOT_COMPLETE 0x01
b5fc475bca6525d8da80728128eefb7100aaf66bap#define NVSLOT_NCQ 0x02 /* NCQ is active */
b5fc475bca6525d8da80728128eefb7100aaf66bap#define NVSLOT_RQSENSE 0x04 /* processing request sense */
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
8d483882aa3390058094b043f3d62187b5d1de03mlf * state values for nv_attach
8d483882aa3390058094b043f3d62187b5d1de03mlf */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define ATTACH_PROGRESS_NONE (1 << 0)
8d483882aa3390058094b043f3d62187b5d1de03mlf#define ATTACH_PROGRESS_STATEP_ALLOC (1 << 1)
8d483882aa3390058094b043f3d62187b5d1de03mlf#define ATTACH_PROGRESS_PCI_HANDLE (1 << 2)
8d483882aa3390058094b043f3d62187b5d1de03mlf#define ATTACH_PROGRESS_BARS (1 << 3)
8d483882aa3390058094b043f3d62187b5d1de03mlf#define ATTACH_PROGRESS_INTR_ADDED (1 << 4)
8d483882aa3390058094b043f3d62187b5d1de03mlf#define ATTACH_PROGRESS_MUTEX_INIT (1 << 5)
8d483882aa3390058094b043f3d62187b5d1de03mlf#define ATTACH_PROGRESS_CTL_SETUP (1 << 6)
8d483882aa3390058094b043f3d62187b5d1de03mlf#define ATTACH_PROGRESS_TRAN_SETUP (1 << 7)
8d483882aa3390058094b043f3d62187b5d1de03mlf#define ATTACH_PROGRESS_COUNT (1 << 8)
8d483882aa3390058094b043f3d62187b5d1de03mlf#define ATTACH_PROGRESS_CONF_HANDLE (1 << 9)
8d483882aa3390058094b043f3d62187b5d1de03mlf#define ATTACH_PROGRESS_SATA_MODULE (1 << 10)
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf#ifdef DEBUG
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_DEBUG 1
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf#endif /* DEBUG */
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
8d483882aa3390058094b043f3d62187b5d1de03mlf * nv_debug_flags
8d483882aa3390058094b043f3d62187b5d1de03mlf */
7798b2a0723f7ed75e6d4a86f0821b4173930eb5Martin Faltesek#define NVDBG_ALWAYS 0x00001
7798b2a0723f7ed75e6d4a86f0821b4173930eb5Martin Faltesek#define NVDBG_INIT 0x00002
7798b2a0723f7ed75e6d4a86f0821b4173930eb5Martin Faltesek#define NVDBG_ENTRY 0x00004
7798b2a0723f7ed75e6d4a86f0821b4173930eb5Martin Faltesek#define NVDBG_DELIVER 0x00008
7798b2a0723f7ed75e6d4a86f0821b4173930eb5Martin Faltesek#define NVDBG_EVENT 0x00010
7798b2a0723f7ed75e6d4a86f0821b4173930eb5Martin Faltesek#define NVDBG_SYNC 0x00020
7798b2a0723f7ed75e6d4a86f0821b4173930eb5Martin Faltesek#define NVDBG_PKTCOMP 0x00040
7798b2a0723f7ed75e6d4a86f0821b4173930eb5Martin Faltesek#define NVDBG_TIMEOUT 0x00080
7798b2a0723f7ed75e6d4a86f0821b4173930eb5Martin Faltesek#define NVDBG_INFO 0x00100
7798b2a0723f7ed75e6d4a86f0821b4173930eb5Martin Faltesek#define NVDBG_VERBOSE 0x00200
7798b2a0723f7ed75e6d4a86f0821b4173930eb5Martin Faltesek#define NVDBG_INTR 0x00400
7798b2a0723f7ed75e6d4a86f0821b4173930eb5Martin Faltesek#define NVDBG_ERRS 0x00800
7798b2a0723f7ed75e6d4a86f0821b4173930eb5Martin Faltesek#define NVDBG_COOKIES 0x01000
7798b2a0723f7ed75e6d4a86f0821b4173930eb5Martin Faltesek#define NVDBG_HOT 0x02000
7798b2a0723f7ed75e6d4a86f0821b4173930eb5Martin Faltesek#define NVDBG_RESET 0x04000
7798b2a0723f7ed75e6d4a86f0821b4173930eb5Martin Faltesek#define NVDBG_ATAPI 0x08000
7798b2a0723f7ed75e6d4a86f0821b4173930eb5Martin Faltesek
7798b2a0723f7ed75e6d4a86f0821b4173930eb5Martin Faltesek#define NVLOG(flag, nvc, nvp, fmt, args ...) \
7798b2a0723f7ed75e6d4a86f0821b4173930eb5Martin Faltesek if (nv_debug_flags & (flag)) { \
7798b2a0723f7ed75e6d4a86f0821b4173930eb5Martin Faltesek nv_log(nvc, nvp, fmt, ## args); \
7798b2a0723f7ed75e6d4a86f0821b4173930eb5Martin Faltesek }
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_SUCCESS 0
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_FAILURE -1
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
8d483882aa3390058094b043f3d62187b5d1de03mlf * indicates whether nv_wait functions can sleep or not.
8d483882aa3390058094b043f3d62187b5d1de03mlf */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_SLEEP 1
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_NOSLEEP 2
8d483882aa3390058094b043f3d62187b5d1de03mlf
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
8d483882aa3390058094b043f3d62187b5d1de03mlf * port offsets from base address ioaddr1
8d483882aa3390058094b043f3d62187b5d1de03mlf */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_DATA 0x00 /* data register */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_ERROR 0x01 /* error register (read) */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_FEATURE 0x01 /* features (write) */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_COUNT 0x02 /* sector count */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_SECT 0x03 /* sector number */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_LCYL 0x04 /* cylinder low byte */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_HCYL 0x05 /* cylinder high byte */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_DRVHD 0x06 /* drive/head register */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_STATUS 0x07 /* status/command register */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_CMD 0x07 /* status/command register */
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
8d483882aa3390058094b043f3d62187b5d1de03mlf * port offsets from base address ioaddr2
8d483882aa3390058094b043f3d62187b5d1de03mlf */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_ALTSTATUS 0x02 /* alternate status (read) */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_DEVCTL 0x02 /* device control (write) */
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
8d483882aa3390058094b043f3d62187b5d1de03mlf * device control register
8d483882aa3390058094b043f3d62187b5d1de03mlf */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define ATDC_NIEN 0x02 /* disable interrupts */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define ATDC_SRST 0x04 /* controller reset */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define ATDC_D3 0x08 /* mysterious bit */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define ATDC_HOB 0x80 /* high order byte to read 48-bit values */
8d483882aa3390058094b043f3d62187b5d1de03mlf
a9d5ae2e08c504913c088349c3d4c144f3c92be8Pawel Wojcik/*
a9d5ae2e08c504913c088349c3d4c144f3c92be8Pawel Wojcik * MCP5x NCQ and INTR control registers
a9d5ae2e08c504913c088349c3d4c144f3c92be8Pawel Wojcik */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define MCP5X_CTL 0x400 /* queuing control */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define MCP5X_INT_STATUS 0x440 /* status bits for interrupt */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define MCP5X_INT_CTL 0x444 /* enable bits for interrupt */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define MCP5X_NCQ 0x448 /* NCQ status and ctrl bits */
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
8d483882aa3390058094b043f3d62187b5d1de03mlf * if either of these bits are set, when using NCQ, if no other commands are
8d483882aa3390058094b043f3d62187b5d1de03mlf * active while a new command is started, DMA engine can be programmed ahead
8d483882aa3390058094b043f3d62187b5d1de03mlf * of time to save extra interrupt. Presumably pre-programming is discarded
8d483882aa3390058094b043f3d62187b5d1de03mlf * if a subsequent command ends up finishing first.
8d483882aa3390058094b043f3d62187b5d1de03mlf */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define MCP_SATA_AE_NCQ_PDEV_FIRST_CMD (1 << 7)
8d483882aa3390058094b043f3d62187b5d1de03mlf#define MCP_SATA_AE_NCQ_SDEV_FIRST_CMD (1 << 23)
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
8d483882aa3390058094b043f3d62187b5d1de03mlf * bit definitions to indicate which NCQ command requires
8d483882aa3390058094b043f3d62187b5d1de03mlf * DMA setup.
8d483882aa3390058094b043f3d62187b5d1de03mlf */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define MCP_SATA_AE_NCQ_PDEV_DMA_SETUP_TAG_SHIFT 2
8d483882aa3390058094b043f3d62187b5d1de03mlf#define MCP_SATA_AE_NCQ_SDEV_DMA_SETUP_TAG_SHIFT 18
8d483882aa3390058094b043f3d62187b5d1de03mlf#define MCP_SATA_AE_NCQ_DMA_SETUP_TAG_MASK 0x1f
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama * Bits for NV_MCP5X_INT_CTL and NV_MCP5X_INT_STATUS
8d483882aa3390058094b043f3d62187b5d1de03mlf */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define MCP5X_INT_SNOTIFY 0x200 /* snotification set */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define MCP5X_INT_SERROR 0x100 /* serror set */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define MCP5X_INT_DMA_SETUP 0x80 /* DMA to be programmed */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define MCP5X_INT_DH_REGFIS 0x40 /* REGFIS received */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define MCP5X_INT_SDB_FIS 0x20 /* SDB FIS */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define MCP5X_INT_TX_BACKOUT 0x10 /* TX backout */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define MCP5X_INT_REM 0x08 /* device removed */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define MCP5X_INT_ADD 0x04 /* device added */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define MCP5X_INT_PM 0x02 /* power changed */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define MCP5X_INT_COMPLETE 0x01 /* device interrupt */
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
8d483882aa3390058094b043f3d62187b5d1de03mlf * Bits above that are not used for now.
8d483882aa3390058094b043f3d62187b5d1de03mlf */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define MCP5X_INT_IGNORE (MCP5X_INT_DMA_SETUP|MCP5X_INT_DH_REGFIS|\
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama MCP5X_INT_SDB_FIS|MCP5X_INT_TX_BACKOUT|MCP5X_INT_PM|\
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama MCP5X_INT_SNOTIFY|MCP5X_INT_SERROR)
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
8d483882aa3390058094b043f3d62187b5d1de03mlf * Bits for MCP_SATA_AE_CTL
8d483882aa3390058094b043f3d62187b5d1de03mlf */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define MCP_SATA_AE_CTL_PRI_SWNCQ (1 << 1) /* software NCQ chan 0 */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define MCP_SATA_AE_CTL_SEC_SWNCQ (1 << 2) /* software NCQ chan 1 */
8d483882aa3390058094b043f3d62187b5d1de03mlf
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek#define NV_DELAY_NSEC(wait_ns) \
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek{ \
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek hrtime_t start, end; \
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek start = end = gethrtime(); \
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek while ((end - start) < wait_ns) \
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek end = gethrtime(); \
8d483882aa3390058094b043f3d62187b5d1de03mlf}
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek * signature in task file registers after device reset
8d483882aa3390058094b043f3d62187b5d1de03mlf */
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek#define NV_DISK_SIG 0x00000101
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek#define NV_ATAPI_SIG 0xeb140101
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek#define NV_PM_SIG 0x96690101
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek#define NV_NO_SIG 0x00000000
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama * These bar5 offsets are common to mcp51/mcp55/ck804 and thus
8d483882aa3390058094b043f3d62187b5d1de03mlf * prefixed with NV.
8d483882aa3390058094b043f3d62187b5d1de03mlf */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_SSTATUS 0x00
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_SERROR 0x04
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_SCTRL 0x08
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_SACTIVE 0x0c
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_SNOTIFICATION 0x10
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf#define CH0_SREG_OFFSET 0x0
8d483882aa3390058094b043f3d62187b5d1de03mlf#define CH1_SREG_OFFSET 0x40
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
8d483882aa3390058094b043f3d62187b5d1de03mlf * The following config space offsets are needed to enable
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama * bar 5 register access in ck804/mcp51/mcp55
8d483882aa3390058094b043f3d62187b5d1de03mlf */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_SATA_CFG_20 0x50
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_BAR5_SPACE_EN 0x04
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_40BIT_PRD 0x20
8d483882aa3390058094b043f3d62187b5d1de03mlf
f8a5505bcdd439e9b2cc56a9798b1db3a5933afaMartin Faltesek#define NV_SATA_CFG_23 0x60
f8a5505bcdd439e9b2cc56a9798b1db3a5933afaMartin Faltesek
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama * ck804 interrupt status register
8d483882aa3390058094b043f3d62187b5d1de03mlf */
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
8d483882aa3390058094b043f3d62187b5d1de03mlf * offsets to bar 5 registers
8d483882aa3390058094b043f3d62187b5d1de03mlf */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_SATA_INT_STATUS 0x440
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_SATA_INT_EN 0x441
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
8d483882aa3390058094b043f3d62187b5d1de03mlf * bit fields for int status and int enable
8d483882aa3390058094b043f3d62187b5d1de03mlf * registers
8d483882aa3390058094b043f3d62187b5d1de03mlf */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_INT_PDEV_INT 0x01 /* completion interrupt */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_INT_PDEV_PM 0x02 /* power change */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_INT_PDEV_ADD 0x04 /* hot plug */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_INT_PDEV_REM 0x08 /* hot remove */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_INT_PDEV_HOT CK804_INT_PDEV_ADD|CK804_INT_PDEV_REM
8d483882aa3390058094b043f3d62187b5d1de03mlf
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_INT_SDEV_INT 0x10 /* completion interrupt */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_INT_SDEV_PM 0x20 /* power change */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_INT_SDEV_ADD 0x40 /* hot plug */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_INT_SDEV_REM 0x80 /* hot remove */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_INT_SDEV_HOT CK804_INT_SDEV_ADD|CK804_INT_SDEV_REM
8d483882aa3390058094b043f3d62187b5d1de03mlf
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_INT_PDEV_ALL CK804_INT_PDEV_INT|CK804_INT_PDEV_HOT|\
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama CK804_INT_PDEV_PM
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_INT_SDEV_ALL CK804_INT_SDEV_INT|CK804_INT_SDEV_HOT|\
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama CK804_INT_SDEV_PM
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
8d483882aa3390058094b043f3d62187b5d1de03mlf * config space offset 42
8d483882aa3390058094b043f3d62187b5d1de03mlf */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_SATA_CFG_42 0xac
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
8d483882aa3390058094b043f3d62187b5d1de03mlf * bit in CFG_42 which delays hotplug interrupt until
8d483882aa3390058094b043f3d62187b5d1de03mlf * PHY ready
8d483882aa3390058094b043f3d62187b5d1de03mlf */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_CFG_DELAY_HOTPLUG_INTR (0x1 << 12)
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
8d483882aa3390058094b043f3d62187b5d1de03mlf * bar 5 offsets for SATA registers in ck804
8d483882aa3390058094b043f3d62187b5d1de03mlf */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_CH1_SSTATUS 0x00
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_CH1_SERROR 0x04
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_CH1_SCTRL 0x08
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_CH1_SACTIVE 0x0c
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_CH1_SNOTIFICATION 0x10
8d483882aa3390058094b043f3d62187b5d1de03mlf
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_CH2_SSTATUS 0x40
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_CH2_SERROR 0x44
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_CH2_SCTRL 0x48
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_CH2_SACTIVE 0x4c
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_CH2_SNOTIFICATION 0x50
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama * bar 5 offsets for ADMACTL settings for both ck804/mcp51/mcp/55
8d483882aa3390058094b043f3d62187b5d1de03mlf */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_ADMACTL_X 0x4C0
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_ADMACTL_Y 0x5C0
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
8d483882aa3390058094b043f3d62187b5d1de03mlf * Bits for NV_ADMACTL_X and NV_ADMACTL_Y
8d483882aa3390058094b043f3d62187b5d1de03mlf */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_HIRQ_EN 0x01 /* hot plug/unplug interrupt enable */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_CH_RST 0x04 /* reset channel */
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama * bar 5 offset for ADMASTAT regs for ck804
8d483882aa3390058094b043f3d62187b5d1de03mlf */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_ADMASTAT_X 0x4C4
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_ADMASTAT_Y 0x5C4
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama * Bits for CK804_ADMASTAT_X and CK804_ADMASTAT_Y
8d483882aa3390058094b043f3d62187b5d1de03mlf */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define CK804_HPIRQ 0x4
8d483882aa3390058094b043f3d62187b5d1de03mlf#define MCP05_HUIRQ 0x2
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
8d483882aa3390058094b043f3d62187b5d1de03mlf * bar 4 offset to bus master command registers
8d483882aa3390058094b043f3d62187b5d1de03mlf */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define BMICX_REG 0
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
8d483882aa3390058094b043f3d62187b5d1de03mlf * bit definitions for BMICX_REG
8d483882aa3390058094b043f3d62187b5d1de03mlf */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define BMICX_SSBM 0x01 /* Start/Stop Bus Master */
8d483882aa3390058094b043f3d62187b5d1de03mlf /* 1=Start (Enable) */
8d483882aa3390058094b043f3d62187b5d1de03mlf /* 0=Start (Disable) */
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
8d483882aa3390058094b043f3d62187b5d1de03mlf * NOTE: "read" and "write" are the actions of the DMA engine
8d483882aa3390058094b043f3d62187b5d1de03mlf * on the PCI bus, not the SATA bus. Therefore for a ATA READ
8d483882aa3390058094b043f3d62187b5d1de03mlf * command, program the DMA engine to "write to memory" mode
8d483882aa3390058094b043f3d62187b5d1de03mlf * (and vice versa).
8d483882aa3390058094b043f3d62187b5d1de03mlf */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define BMICX_RWCON 0x08 /* Read/Write Control */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define BMICX_RWCON_WRITE_TO_MEMORY 0x08 /* 1=Write (dev to host) */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define BMICX_RWCON_READ_FROM_MEMORY 0x00 /* 0=Read (host to dev) */
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
8d483882aa3390058094b043f3d62187b5d1de03mlf * BMICX bits to preserve during updates
8d483882aa3390058094b043f3d62187b5d1de03mlf */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define BMICX_MASK (~(BMICX_SSBM | BMICX_RWCON))
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
8d483882aa3390058094b043f3d62187b5d1de03mlf * bar 4 offset to bus master status register
8d483882aa3390058094b043f3d62187b5d1de03mlf */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define BMISX_REG 2
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
8d483882aa3390058094b043f3d62187b5d1de03mlf * bit fields for bus master status register
8d483882aa3390058094b043f3d62187b5d1de03mlf */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define BMISX_BMIDEA 0x01 /* Bus Master IDE Active */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define BMISX_IDERR 0x02 /* IDE DMA Error */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define BMISX_IDEINTS 0x04 /* IDE Interrupt Status */
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
8d483882aa3390058094b043f3d62187b5d1de03mlf * bus master status register bits to preserve
8d483882aa3390058094b043f3d62187b5d1de03mlf */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define BMISX_MASK 0xf8
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
8d483882aa3390058094b043f3d62187b5d1de03mlf * bar4 offset to bus master PRD descriptor table
8d483882aa3390058094b043f3d62187b5d1de03mlf */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define BMIDTPX_REG 4
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
8d483882aa3390058094b043f3d62187b5d1de03mlf * structure for a single entry in the PRD table
8d483882aa3390058094b043f3d62187b5d1de03mlf * (physical region descriptor table)
8d483882aa3390058094b043f3d62187b5d1de03mlf */
8d483882aa3390058094b043f3d62187b5d1de03mlftypedef struct prde {
8d483882aa3390058094b043f3d62187b5d1de03mlf uint32_t p_address; /* physical address */
8d483882aa3390058094b043f3d62187b5d1de03mlf uint32_t p_count; /* byte count, EOT in high order bit */
8d483882aa3390058094b043f3d62187b5d1de03mlf} prde_t;
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf#define PRDE_EOT ((uint_t)0x80000000)
8d483882aa3390058094b043f3d62187b5d1de03mlf
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek#define NV_DMA_NSEGS 257 /* at least 1MB (4KB/pg * 256) + 1 if misaligned */
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
8d483882aa3390058094b043f3d62187b5d1de03mlf * ck804 and mcp55 both have 2 ports per controller
8d483882aa3390058094b043f3d62187b5d1de03mlf */
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek#define NV_NUM_PORTS 2
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
8d483882aa3390058094b043f3d62187b5d1de03mlf * Number of slots to allocate in data nv_sata structures to handle
8d483882aa3390058094b043f3d62187b5d1de03mlf * multiple commands at once. This does not reflect the capability of
8d483882aa3390058094b043f3d62187b5d1de03mlf * the drive or the hardware, and in many cases will not match.
8d483882aa3390058094b043f3d62187b5d1de03mlf * 1 or 32 slots are allocated, so in cases where the driver has NCQ
8d483882aa3390058094b043f3d62187b5d1de03mlf * enabled but the drive doesn't support it, or supports fewer than
8d483882aa3390058094b043f3d62187b5d1de03mlf * 32 slots, here may be an over allocation of memory.
8d483882aa3390058094b043f3d62187b5d1de03mlf */
8d483882aa3390058094b043f3d62187b5d1de03mlf#ifdef NCQ
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_QUEUE_SLOTS 32
8d483882aa3390058094b043f3d62187b5d1de03mlf#else
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_QUEUE_SLOTS 1
8d483882aa3390058094b043f3d62187b5d1de03mlf#endif
8d483882aa3390058094b043f3d62187b5d1de03mlf
a9d5ae2e08c504913c088349c3d4c144f3c92be8Pawel Wojcik#define NV_BM_64K_BOUNDARY 0x10000ull
a9d5ae2e08c504913c088349c3d4c144f3c92be8Pawel Wojcik
a9d5ae2e08c504913c088349c3d4c144f3c92be8Pawel Wojcik#define NV_MAX_INTR_PER_DEV 20 /* Empirical value */
a9d5ae2e08c504913c088349c3d4c144f3c92be8Pawel Wojcik
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
a9d5ae2e08c504913c088349c3d4c144f3c92be8Pawel Wojcik * 1 second (in microseconds)
8d483882aa3390058094b043f3d62187b5d1de03mlf */
a9d5ae2e08c504913c088349c3d4c144f3c92be8Pawel Wojcik#define NV_ONE_SEC 1000000
8d483882aa3390058094b043f3d62187b5d1de03mlf
a9d5ae2e08c504913c088349c3d4c144f3c92be8Pawel Wojcik/*
a9d5ae2e08c504913c088349c3d4c144f3c92be8Pawel Wojcik * 1 millisecond (in microseconds)
a9d5ae2e08c504913c088349c3d4c144f3c92be8Pawel Wojcik */
a9d5ae2e08c504913c088349c3d4c144f3c92be8Pawel Wojcik#define NV_ONE_MSEC 1000
8d483882aa3390058094b043f3d62187b5d1de03mlf
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek/*
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek * initial wait before checking for signature, in microseconds
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek */
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek#define NV_WAIT_SIG 2500
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
a9d5ae2e08c504913c088349c3d4c144f3c92be8Pawel Wojcik * Length of port reset (microseconds) - SControl bit 0 set to 1
8d483882aa3390058094b043f3d62187b5d1de03mlf */
a9d5ae2e08c504913c088349c3d4c144f3c92be8Pawel Wojcik#define NV_RESET_LENGTH 1000
8d483882aa3390058094b043f3d62187b5d1de03mlf
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek/*
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek * the maximum number of comresets to issue while
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek * performing link reset in nv_reset()
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek */
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek#define NV_COMRESET_ATTEMPTS 3
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek * amount of time to wait for a signature in reset, in ms, before
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek * issuing another reset
8d483882aa3390058094b043f3d62187b5d1de03mlf */
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek#define NV_RETRY_RESET_SIG 5000
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek * the maximum number of resets to issue to gather signature
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek * before giving up
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek */
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek#define NV_MAX_RESET_RETRY 8
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek/*
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek * amount of time (us) to wait after receiving a link event
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek * before acting on it. This is because of flakey hardware
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek * sometimes issues the wrong, multiple, or out of order link
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek * events.
8d483882aa3390058094b043f3d62187b5d1de03mlf */
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek#define NV_LINK_EVENT_SETTLE 500000
8d483882aa3390058094b043f3d62187b5d1de03mlf
a9d5ae2e08c504913c088349c3d4c144f3c92be8Pawel Wojcik/*
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek * The amount of time (ms) a link can be missing
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek * before declaring it removed.
a9d5ae2e08c504913c088349c3d4c144f3c92be8Pawel Wojcik */
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek#define NV_LINK_EVENT_DOWN 200
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
8d483882aa3390058094b043f3d62187b5d1de03mlf * nvp_state flags
8d483882aa3390058094b043f3d62187b5d1de03mlf */
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek#define NV_DEACTIVATED 0x001
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek#define NV_ABORTING 0x002
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek#define NV_FAILED 0x004
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek#define NV_RESET 0x008
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek#define NV_RESTORE 0x010
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek#define NV_LINK_EVENT 0x020
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek#define NV_ATTACH 0x040
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek#define NV_HOTPLUG 0x080
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek/*
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek * flags for nv_report_link_event()
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek */
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek#define NV_ADD_DEV 0
a78a9fafefff1ddbaa3ef65fa09190848e704a27Martin Faltesek#define NV_REM_DEV 1
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
8d483882aa3390058094b043f3d62187b5d1de03mlf * nvc_state flags
8d483882aa3390058094b043f3d62187b5d1de03mlf */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_CTRL_SUSPEND 0x1
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama * flags for ck804_set_intr/mcp5x_set_intr
8d483882aa3390058094b043f3d62187b5d1de03mlf */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_INTR_DISABLE 0x1
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_INTR_ENABLE 0x2
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_INTR_CLEAR_ALL 0x4
193974072f41a843678abf5f61979c748687e66bSherry Moore#define NV_INTR_DISABLE_NON_BLOCKING 0x8
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_BYTES_PER_SEC 512
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_WAIT_REG_CHECK 10 /* 10 microseconds */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_ATA_NUM_CMDS 256 /* max num ATA cmds possible, 8 bits */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_PRINT_INTERVAL 40 /* throttle debug msg from flooding */
5b439bed8ee42c491cb436bb64d1c1d62c61ea1aPraveen Kumar Dasaraju Rama#define MCP5X_INT_CLEAR 0xffff /* clear all interrupts */
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
8d483882aa3390058094b043f3d62187b5d1de03mlf * definition labels for the BAR registers
8d483882aa3390058094b043f3d62187b5d1de03mlf */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_BAR_0 0 /* chan 0 task file regs */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_BAR_1 1 /* chan 0 status reg */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_BAR_2 2 /* chan 1 task file regs */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_BAR_3 3 /* chan 1 status reg */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_BAR_4 4 /* bus master regs */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_BAR_5 5 /* extra regs mostly SATA related */
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
8d483882aa3390058094b043f3d62187b5d1de03mlf * transform seconds to microseconds
8d483882aa3390058094b043f3d62187b5d1de03mlf */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_SEC2USEC(x) x * MICROSEC
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
8d483882aa3390058094b043f3d62187b5d1de03mlf * ck804 maps in task file regs into bar 5. These are
8d483882aa3390058094b043f3d62187b5d1de03mlf * only used to identify ck804, therefore only this reg is
8d483882aa3390058094b043f3d62187b5d1de03mlf * listed here.
8d483882aa3390058094b043f3d62187b5d1de03mlf */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_BAR5_TRAN_LEN_CH_X 0x518
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
8d483882aa3390058094b043f3d62187b5d1de03mlf * if after this many iterations through the interrupt
8d483882aa3390058094b043f3d62187b5d1de03mlf * processing loop, declare the interrupt wedged and
8d483882aa3390058094b043f3d62187b5d1de03mlf * disable.
8d483882aa3390058094b043f3d62187b5d1de03mlf */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_MAX_INTR_LOOP 10
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf/*
8d483882aa3390058094b043f3d62187b5d1de03mlf * flag values for nv_copy_regs_out
8d483882aa3390058094b043f3d62187b5d1de03mlf */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_COPY_COMPLETE 0x01 /* normal command completion */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_COPY_ERROR 0x02 /* error, did not complete ok */
8d483882aa3390058094b043f3d62187b5d1de03mlf#define NV_COPY_SSREGS 0x04 /* SS port registers */
8d483882aa3390058094b043f3d62187b5d1de03mlf
3f318a288186db82aae78875c429f248622cf19fAlan Perry#ifdef SGPIO_SUPPORT
a150bf8532245eea0ae6e08e711e1f62c0a30adcAlan Perry#define NV_MAX_CBPS 16 /* Maximum # of Control Block */
a150bf8532245eea0ae6e08e711e1f62c0a30adcAlan Perry /* Pointers. Corresponds to */
a150bf8532245eea0ae6e08e711e1f62c0a30adcAlan Perry /* each MCP55 and IO55 */
3f318a288186db82aae78875c429f248622cf19fAlan Perry#define SGPIO_LOOP_WAIT_USECS 62500 /* 1/16 second (in usecs) */
3f318a288186db82aae78875c429f248622cf19fAlan Perry#define SGPIO_TQ_NAME_LEN 32
3f318a288186db82aae78875c429f248622cf19fAlan Perry
3f318a288186db82aae78875c429f248622cf19fAlan Perry/*
3f318a288186db82aae78875c429f248622cf19fAlan Perry * The drive number format is ccp (binary).
3f318a288186db82aae78875c429f248622cf19fAlan Perry * cc is the controller number (0-based number)
3f318a288186db82aae78875c429f248622cf19fAlan Perry * p is the port number (0 or 1)
3f318a288186db82aae78875c429f248622cf19fAlan Perry */
3f318a288186db82aae78875c429f248622cf19fAlan Perry#define SGP_DRV_TO_PORT(d) ((d) & 1)
3f318a288186db82aae78875c429f248622cf19fAlan Perry#define SGP_DRV_TO_CTLR(d) ((d) >> 1)
3f318a288186db82aae78875c429f248622cf19fAlan Perry#define SGP_CTLR_PORT_TO_DRV(c, p) (((c) << 1) | ((p) & 1))
3f318a288186db82aae78875c429f248622cf19fAlan Perry#endif
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf#ifdef __cplusplus
8d483882aa3390058094b043f3d62187b5d1de03mlf}
8d483882aa3390058094b043f3d62187b5d1de03mlf#endif
8d483882aa3390058094b043f3d62187b5d1de03mlf
8d483882aa3390058094b043f3d62187b5d1de03mlf#endif /* _NV_SATA_H */