ahcivar.h revision f8a673ad9145b262edb65a98fb3fb92027d23a05
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2008 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _AHCIVAR_H
#define _AHCIVAR_H
#ifdef __cplusplus
extern "C" {
#endif
/* Type for argument of event handler */
typedef struct ahci_event_arg {
void *ahciea_ctlp;
void *ahciea_portp;
/* Warlock annotation */
/*
* flags for ahciport_flags
*
* AHCI_PORT_FLAG_SPINUP: this flag will be set when a HBA which supports
* staggered spin-up needs to do a spin-up.
*
* AHCI_PORT_FLAG_MOPPING: this flag will be set when the HBA is stopped,
* and all the outstanding commands need to be aborted and sent to upper
* layers.
*
* AHCI_PORT_FLAG_POLLING: this flag will be set when the interrupt is
* disabled, and the command is executed in POLLING mode.
*
* AHCI_PORT_FLAG_RQSENSE: this flag will be set when a REQUEST SENSE which
* is used to retrieve sense data is being executed.
*
* AHCI_PORT_FLAG_STARTED: this flag will be set when the port is started,
* that is PxCMD.ST is set with '1', and be cleared when the port is put into
* idle, that is PxCMD.ST is changed from '1' to '0'.
*
* AHCI_PORT_FLAG_RDLOGEXT: this flag will be set when a READ LOG EXT which
* is used to retrieve NCQ failure context is being executed.
*
* AHCI_PORT_FLAG_NODEV: this flag will be set when a device is found gone
* during ahci_restart_port_wait_till_ready process.
*/
#define AHCI_PORT_FLAG_SPINUP 0x01
#define AHCI_PORT_FLAG_MOPPING 0x02
#define AHCI_PORT_FLAG_POLLING 0x04
#define AHCI_PORT_FLAG_RQSENSE 0x08
#define AHCI_PORT_FLAG_STARTED 0x10
#define AHCI_PORT_FLAG_RDLOGEXT 0x20
#define AHCI_PORT_FLAG_NODEV 0x40
typedef struct ahci_port {
/* The physical port number */
/* Type of the device attached to the port */
/* State of the port */
/*
* AHCI_PORT_FLAG_SPINUP
* AHCI_PORT_FLAG_MOPPING
* AHCI_PORT_FLAG_POLLING
* AHCI_PORT_FLAG_RQSENSE
* AHCI_PORT_FLAG_STARTED
* AHCI_PORT_FLAG_RDLOGEXT
* AHCI_PORT_FLAG_NODEV
*/
int ahciport_flags;
/* Pointer to received FIS structure */
/* Pointer to command list structure */
/* Pointer to cmmand table structure */
/* Condition variable used for sync mode commands */
/* The whole mutex for the port structure */
/* The maximum number of tags for native queuing command transfers */
/* Keep the tags of all pending non-ncq commands */
/*
* Keep the tags of all pending ncq commands
*/
/* Keep all the pending sata packets */
/* Keep the byte count of all PRD entries for every sata packet */
uint32_t \
/* Keep the error retrieval sata packet */
/*
* SATA HBA driver is supposed to remember and maintain device
* reset state. While the reset is in progress, it doesn't accept
* any more commands until receiving the command with
* SATA_CLEAR_DEV_RESET_STATE flag and SATA_IGNORE_DEV_RESET_STATE.
*/
/* Taskq for handling event */
/* This is for error recovery handler */
/* This is to calculate how many mops are in progress */
} ahci_port_t;
/* Warlock annotation */
typedef struct ahci_ctl {
/* To map port number to cport number */
/* To map cport number to port number */
/* Number of controller ports */
int ahcictl_num_ports;
/* Number of command slots */
/* Number of implemented ports */
/* Bit map to indicate which port is implemented */
int ahcictl_flags;
int ahcictl_power_level;
/*
* AHCI_CAP_PIO_MDRQ
* AHCI_CAP_NO_MCMDLIST_NONQUEUE
* AHCI_CAP_NCQ
* AHCI_CAP_PM
* AHCI_CAP_32BIT_DMA
*/
int ahcictl_cap;
/* Pci configuration space handle */
/* Mapping into bar 5 - AHCI base address */
/* Pointer used for sata hba framework registration */
struct sata_hba_tran *ahcictl_sata_hba_tran;
/* DMA attributes for the data buffer */
/* DMA attributes for the rcvd FIS */
/* DMA attributes for the command list */
/* DMA attributes for command tables */
/* Used for watchdog handler */
/* Per controller mutex */
/* Components for interrupt */
int ahcictl_intr_type; /* What type of interrupt */
int ahcictl_intr_cnt; /* # of intrs returned */
int ahcictl_intr_cap; /* Intr capabilities */
} ahci_ctl_t;
/* Warlock annotation */
#define AHCI_SUCCESS (0) /* Successful return */
/* Flags for ahcictl_flags */
#define AHCI_ATTACH 0x1
#define AHCI_DETACH 0x2
#define AHCI_SUSPEND 0x4
/* Values for ahcictl_cap */
/* PIO Multiple DRQ Block */
#define AHCI_CAP_PIO_MDRQ 0x1
/*
* Multiple command slots in the command list cannot be used for
* non-queued commands
*/
#define AHCI_CAP_NO_MCMDLIST_NONQUEUE 0x2
/* Native Command Queuing (NCQ) */
#define AHCI_CAP_NCQ 0x4
/* Power Management (PM) */
#define AHCI_CAP_PM 0x8
/* 32-bit DMA addressing */
#define AHCI_CAP_32BIT_DMA 0x10
/* Flags controlling the restart port behavior */
#define ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) \
(ahci_portp->ahciport_flags & \
#define NON_NCQ_CMD_IN_PROGRESS(ahci_portp) \
(!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) && \
ahci_portp->ahciport_pending_tags != 0 && \
#define NCQ_CMD_IN_PROGRESS(ahci_portp) \
(!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) && \
/* Command type for ahci_claim_free_slot routine */
#define AHCI_NON_NCQ_CMD 0x0
#define AHCI_NCQ_CMD 0x1
#define AHCI_ERR_RETRI_CMD 0x2
/* State values for ahci_attach */
#define AHCI_ATTACH_STATE_NONE (0x1 << 0)
/* Interval used for delay */
/*
* The following values are the numbers of times to retry polled requests.
*/
#define AHCI_POLLRATE_HBA_RESET 100
#define AHCI_POLLRATE_PORT_SSTATUS 10
#define AHCI_POLLRATE_PORT_TFD_ERROR 1100
#define AHCI_POLLRATE_PORT_IDLE 50
#define AHCI_POLLRATE_PORT_SOFTRESET 100
#define AHCI_POLLRATE_GET_SPKT 100
/* Clearing & setting the n'th bit in a given tag */
#if DEBUG
#define AHCI_DEBUG 1
#define AHCIDBG_INIT 0x0001
#define AHCIDBG_ENTRY 0x0002
#define AHCIDBG_PRDT 0x0004
#define AHCIDBG_EVENT 0x0008
#define AHCIDBG_POLL_LOOP 0x0010
#define AHCIDBG_PKTCOMP 0x0020
#define AHCIDBG_TIMEOUT 0x0040
#define AHCIDBG_INFO 0x0080
#define AHCIDBG_VERBOSE 0x0100
#define AHCIDBG_INTR 0x0200
#define AHCIDBG_ERRS 0x0400
#define AHCIDBG_ATACMD 0x0800
#define AHCIDBG_ATAPICMD 0x1000
#define AHCIDBG_SENSEDATA 0x2000
#define AHCIDBG_NCQ 0x4000
#define AHCIDBG_PM 0x8000
#define AHCIDBG_UNDERFLOW 0x10000
extern int ahci_debug_flag;
if (ahci_debug_flags & (flag)) { \
}
if (ahci_debug_flags & (flag)) { \
}
if (ahci_debug_flags & (flag)) { \
}
if (ahci_debug_flags & (flag)) { \
}
if (ahci_debug_flags & (flag)) { \
}
if (ahci_debug_flags & (flag)) { \
}
#else
#endif /* DEBUG */
#ifdef __cplusplus
}
#endif
#endif /* _AHCIVAR_H */