pcie_impl.h revision eae2e508a8e70b1ec407b10bd068c080651bbe5c
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2008 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_PCIE_IMPL_H
#define _SYS_PCIE_IMPL_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
#define PCI_GET_BDF(dip) \
#define PCI_GET_SEC_BUS(dip) \
#define PCI_GET_PCIE2PCI_SECBUS(dip) \
#define DEVI_PORT_TYPE_PCI \
#define PCIE_DIP2BUS(dip) \
PCIE_DIP2UPBUS(dip) : \
#define PCIE_DIP2UPBUS(dip) \
#define PCIE_DIP2DOWNBUS(dip) \
#define PCIE_IS_PCI(bus_p) \
/* IS_ROOT = is RC or RP */
/*
* This is a pseudo pcie "device type", but it's needed to explain describe
* nodes such as PX and NPE, which aren't really PCI devices but do control or
* interaction with PCI error handling.
*/
#define PCIE_IS_RC(bus_p) \
#define PCIE_IS_RP(bus_p) \
#define PCIE_IS_SW(bus_p) \
#define PCIE_IS_PCI_BDG(bus_p) \
#define PCIE_IS_PCIE_BDG(bus_p) \
#define PCIE_IS_PCIE_SEC(bus_p) \
#define PCIX_ECC_VERSION_CHECK(bus_p) \
val)
val)
val)
/* Translate PF error return values to DDI_FM values */
#define PF_ERR2DDIFM_ERR(sts) \
/*
* The following flag is used for Broadcom 5714/5715 bridge prefetch issue.
* This flag will be used both by px and px_pci nexus drivers.
*/
#define PX_DMAI_FLAGS_MAP_BUFZONE 0x40000
/*
* PCI(e/-X) structures used to to gather and report errors detected by
* PCI(e/-X) compliant devices. These registers only contain "dynamic" data.
* Static data such as Capability Offsets and Version #s is saved in the parent
* private data.
*/
#define PCIE_ADV_BDG_REG(pfd_p) \
#define PCIE_ADV_RP_REG(pfd_p) \
typedef struct pf_pci_bdg_err_regs {
typedef struct pf_pci_err_regs {
typedef struct pf_pcix_ecc_regs {
typedef struct pf_pcix_err_regs {
typedef struct pf_pcix_bdg_err_regs {
typedef struct pf_pcie_adv_bdg_err_regs {
typedef struct pf_pcie_adv_rp_err_regs {
typedef struct pf_pcie_adv_err_regs {
union {
} pcie_ext;
typedef struct pf_pcie_rp_err_regs {
typedef struct pf_pcie_err_regs {
typedef struct pf_root_fault {
typedef struct pcie_bus {
int bus_addr_entries; /* number of range prop */
int bus_assigned_entries; /* number of prop entries */
/* Cache of last fault data */
} pcie_bus_t;
struct pf_data {
union {
} pe_ext;
};
/* Information used while handling errors in the fabric. */
typedef struct pf_impl {
} pf_impl_t;
/* bus_fm_flags field */
/*
* PCIe fabric handle lookup address flags. Used to define what type of
* transaction the address is for. These same value are defined again in
* fabric-xlate FM module. Do not modify these variables, without modifying
* those.
*/
#define PF_ADDR_DMA (1 << 0)
/* PCIe fabric error scanning status flags */
#define PF_SCAN_SUCCESS (1 << 0)
/* PCIe fabric error handling severity return flags */
#define PF_HDL_FOUND 1
#define PF_HDL_NOTFOUND 2
#define PCIE_PCIECAP_DEV_TYPE_RC_PSEUDO 0x100
/* PCIe Friendly Functions */
extern uint32_t pcie_get_aer_uce_mask();
extern uint32_t pcie_get_aer_ce_mask();
extern uint32_t pcie_get_aer_suce_mask();
extern uint32_t pcie_get_serr_mask();
/* PCIe error handling functions */
#ifdef __cplusplus
}
#endif
#endif /* _SYS_PCIE_IMPL_H */