nxge_zcp_hw.h revision 6f45ec7b0b964c3be967c4880e8867ac1e7763a5
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2006 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_NXGE_NXGE_ZCP_HW_H
#define _SYS_NXGE_NXGE_ZCP_HW_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
#include <nxge_defs.h>
/*
* Neptune Zerocopy Hardware definitions
* Updated to reflect PRM-0.8.
*/
#define ZCP_RESET_CFIFO_MASK 0x0F
#define ZCP_CFIFIO_RESET_WAIT 10
#define ZCP_P0_P1_CFIFO_DEPTH 2048
#define ZCP_P2_P3_CFIFO_DEPTH 1024
#define ZCP_NIU_CFIFO_DEPTH 1024
typedef union _zcp_reset_cfifo {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
/* NOTE: Same as RX_LOG_PAGE_HDL */
/* Data Structures */
typedef union zcp_config_reg_u {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
#define ZCP_DEBUG_SEL_BITS 0xFF
#define ZCP_DEBUG_SEL_SHIFT 16
#define RDMA_TH_BITS 0x7FF
#define RDMA_TH_SHIFT 5
#define ZC_ENABLE (1 << 0)
typedef union zcp_int_stat_reg_u {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
#define CFIFO_ECC0 (1 << 0)
typedef union zcp_bam_region_reg_u {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
typedef union zcp_dst_region_reg_u {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
typedef enum tbuf_size_e {
TBUF_4K = 0,
} tbuf_size_t;
typedef enum tbuf_num_e {
TBUF_NUM_4 = 0,
} tbuf_num_t;
typedef enum tmode_e {
TMODE_BASIC = 0,
TMODE_AUTO_UNMAP = 1,
TMODE_AUTO_ADV = 3
} tmode_t;
typedef struct tte_sflow_attr_s {
union {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
} qw0;
union {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
} qw1;
union {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
} qw2;
union {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
} qw3;
union {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
} qw4;
#define TTE_RDC_TBL_SFLOW_BITS_EN 0x0001
#define TTE_BUF_SIZE_BITS_EN 0x0002
#define TTE_NUM_BUF_BITS_EN 0x0002
#define TTE_ULP_END_BITS_EN 0x003E
#define TTE_ULP_END_EN_BITS_EN 0x0020
#define TTE_UNMAP_ALL_BITS_EN 0x0020
#define TTE_TMODE_BITS_EN 0x0040
#define TTE_SKIP_BITS_EN 0x0040
#define TTE_RING_BASE_ADDR_BITS_EN 0x0FC0
#define TTE_RING_SIZE_BITS_EN 0x0800
#define TTE_BUSY_BITS_EN 0x0800
#define TTE_TOQ_BITS_EN 0x3000
#define TTE_MAPPED_IN_BITS_EN 0x0000F
#define TTE_ANCHOR_SEQ_BITS_EN 0x000F0
#define TTE_ANCHOR_OFFSET_BITS_EN 0x00700
#define TTE_ANCHOR_BUFFER_BITS_EN 0x00800
#define TTE_ANCHOR_BUF_FLAG_BITS_EN 0x00800
#define TTE_UNMAP_ON_LEFT_BITS_EN 0x00800
#define TTE_ULP_END_REACHED_BITS_EN 0x00800
#define TTE_ERR_STAT_BITS_EN 0x01000
#define TTE_WR_PTR_BITS_EN 0x01000
#define TTE_HOQ_BITS_EN 0x0E000
#define TTE_PREFETCH_ON_BITS_EN 0x08000
typedef enum tring_size_e {
TRING_SIZE_8 = 0,
} tring_size_t;
typedef struct tte_dflow_attr_s {
union {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
} qw0;
union {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
} qw1;
union {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
} qw2;
union {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
} qw3;
union {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
} qw4;
#define MAX_BAM_BANKS 8
typedef struct zcp_ram_unit_s {
typedef enum dmaw_type_e {
DMAW_NO_CROSS_BUF = 0,
} dmaw_type_t;
typedef union zcp_ram_data_u {
typedef union zcp_ram_access_u {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
#define ZCP_RAM_WR 0
#define ZCP_RAM_RD 1
#define ZCP_RAM_SEL_BAM0 0
#define ZCP_RAM_SEL_BAM1 0x1
#define ZCP_RAM_SEL_BAM2 0x2
#define ZCP_RAM_SEL_BAM3 0x3
#define ZCP_RAM_SEL_BAM4 0x4
#define ZCP_RAM_SEL_BAM5 0x5
#define ZCP_RAM_SEL_BAM6 0x6
#define ZCP_RAM_SEL_BAM7 0x7
#define ZCP_RAM_SEL_TT_STATIC 0x8
#define ZCP_RAM_SEL_TT_DYNAMIC 0x9
#define ZCP_RAM_SEL_CFIFO0 0x10
#define ZCP_RAM_SEL_CFIFO1 0x11
#define ZCP_RAM_SEL_CFIFO2 0x12
#define ZCP_RAM_SEL_CFIFO3 0x13
typedef union zcp_ram_benable_u {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
typedef union zcp_training_vector_u {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
typedef union zcp_state_machine_u {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#endif
} ldw;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
typedef struct zcp_hdr_s {
} zcp_hdr_t;
typedef union _zcp_ecc_ctrl {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#if defined(_BIT_FIELDS_HTOL)
#elif defined(_BIT_FIELDS_LTOH)
#else
#endif
} w0;
#if !defined(_BIG_ENDIAN)
#endif
} bits;
#ifdef __cplusplus
}
#endif
#endif /* _SYS_NXGE_NXGE_ZCP_HW_H */