nxge_impl.h revision cb9d3ae6bc674fba238a0c4ce5a5548c9e35423a
849N/A/*
849N/A * CDDL HEADER START
849N/A *
849N/A * The contents of this file are subject to the terms of the
849N/A * Common Development and Distribution License (the "License").
849N/A * You may not use this file except in compliance with the License.
849N/A *
849N/A * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
849N/A * or http://www.opensolaris.org/os/licensing.
849N/A * See the License for the specific language governing permissions
849N/A * and limitations under the License.
849N/A *
849N/A * When distributing Covered Code, include this CDDL HEADER in each
849N/A * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
849N/A * If applicable, add the following below this CDDL HEADER, with the
849N/A * fields enclosed by brackets "[]" replaced with your own identifying
849N/A * information: Portions Copyright [yyyy] [name of copyright owner]
849N/A *
873N/A * CDDL HEADER END
849N/A */
849N/A/*
849N/A * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
849N/A * Use is subject to license terms.
849N/A */
3232N/A
849N/A#ifndef _SYS_NXGE_NXGE_IMPL_H
849N/A#define _SYS_NXGE_NXGE_IMPL_H
849N/A
849N/A#pragma ident "%Z%%M% %I% %E% SMI"
849N/A
849N/A#ifdef __cplusplus
849N/Aextern "C" {
849N/A#endif
849N/A
849N/A/*
849N/A * NIU HV API version definitions.
849N/A */
849N/A#define NIU_MAJOR_VER 1
849N/A#define NIU_MINOR_VER 1
849N/A
1008N/A/*
1008N/A * NIU HV API v1.0 definitions
1008N/A */
1008N/A#define N2NIU_RX_LP_CONF 0x142
1008N/A#define N2NIU_RX_LP_INFO 0x143
849N/A#define N2NIU_TX_LP_CONF 0x144
849N/A#define N2NIU_TX_LP_INFO 0x145
849N/A
849N/A#ifndef _ASM
849N/A
849N/A#include <sys/types.h>
849N/A#include <sys/byteorder.h>
849N/A#include <sys/debug.h>
849N/A#include <sys/stropts.h>
849N/A#include <sys/stream.h>
849N/A#include <sys/strlog.h>
849N/A#ifndef COSIM
849N/A#include <sys/strsubr.h>
849N/A#endif
849N/A#include <sys/cmn_err.h>
849N/A#include <sys/vtrace.h>
849N/A#include <sys/kmem.h>
849N/A#include <sys/ddi.h>
849N/A#include <sys/sunddi.h>
849N/A#include <sys/strsun.h>
849N/A#include <sys/stat.h>
849N/A#include <sys/cpu.h>
849N/A#include <sys/kstat.h>
849N/A#include <inet/common.h>
849N/A#include <inet/ip.h>
849N/A#include <sys/dlpi.h>
849N/A#include <inet/nd.h>
849N/A#include <netinet/in.h>
849N/A#include <sys/ethernet.h>
849N/A#include <sys/vlan.h>
849N/A#include <sys/pci.h>
849N/A#include <sys/taskq.h>
849N/A#include <sys/atomic.h>
849N/A
849N/A#include <sys/nxge/nxge_defs.h>
849N/A#include <sys/nxge/nxge_hw.h>
849N/A#include <sys/nxge/nxge_mac.h>
849N/A#include <sys/nxge/nxge_mii.h>
849N/A#include <sys/nxge/nxge_fm.h>
849N/A#if !defined(IODIAG)
849N/A#include <sys/netlb.h>
849N/A#endif
849N/A
849N/A#include <sys/ddi_intr.h>
849N/A
849N/A#if defined(_KERNEL)
849N/A#include <sys/mac.h>
849N/A#include <sys/mac_impl.h>
849N/A#include <sys/mac_ether.h>
849N/A#endif
849N/A
849N/A#if defined(sun4v)
849N/A#include <sys/hypervisor_api.h>
849N/A#include <sys/machsystm.h>
849N/A#include <sys/hsvc.h>
849N/A#endif
849N/A
849N/A/*
2624N/A * Handy macros (taken from bge driver)
849N/A */
2624N/A#define RBR_SIZE 4
849N/A#define DMA_COMMON_CHANNEL(area) ((area.dma_channel))
849N/A#define DMA_COMMON_VPTR(area) ((area.kaddrp))
849N/A#define DMA_COMMON_VPTR_INDEX(area, index) \
849N/A (((char *)(area.kaddrp)) + \
849N/A (index * RBR_SIZE))
849N/A#define DMA_COMMON_HANDLE(area) ((area.dma_handle))
849N/A#define DMA_COMMON_ACC_HANDLE(area) ((area.acc_handle))
2624N/A#define DMA_COMMON_IOADDR(area) ((area.dma_cookie.dmac_laddress))
849N/A#define DMA_COMMON_IOADDR_INDEX(area, index) \
2624N/A ((area.dma_cookie.dmac_laddress) + \
2624N/A (index * RBR_SIZE))
849N/A
849N/A#define DMA_NPI_HANDLE(area) ((area.npi_handle)
849N/A
849N/A#define DMA_COMMON_SYNC(area, flag) ((void) ddi_dma_sync((area).dma_handle,\
849N/A (area).offset, (area).alength, \
849N/A (flag)))
849N/A#define DMA_COMMON_SYNC_OFFSET(area, bufoffset, len, flag) \
2624N/A ((void) ddi_dma_sync((area).dma_handle,\
849N/A (area.offset + bufoffset), len, \
2624N/A (flag)))
2624N/A
849N/A#define DMA_COMMON_SYNC_RBR_DESC(area, index, flag) \
849N/A ((void) ddi_dma_sync((area).dma_handle,\
849N/A (index * RBR_SIZE), RBR_SIZE, \
849N/A (flag)))
849N/A
849N/A#define DMA_COMMON_SYNC_RBR_DESC_MULTI(area, index, count, flag) \
849N/A ((void) ddi_dma_sync((area).dma_handle,\
2624N/A (index * RBR_SIZE), count * RBR_SIZE, \
849N/A (flag)))
2624N/A#define DMA_COMMON_SYNC_ENTRY(area, index, flag) \
2624N/A ((void) ddi_dma_sync((area).dma_handle,\
849N/A (index * (area).block_size), \
849N/A (area).block_size, \
849N/A (flag)))
849N/A
849N/A#define NEXT_ENTRY(index, wrap) ((index + 1) & wrap)
849N/A#define NEXT_ENTRY_PTR(ptr, first, last) \
849N/A ((ptr == last) ? first : (ptr + 1))
2624N/A
849N/A/*
2624N/A * NPI related macros
2624N/A */
849N/A#define NXGE_DEV_NPI_HANDLE(nxgep) (nxgep->npi_handle)
849N/A
849N/A#define NPI_PCI_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_pci_handle.regh = ah)
849N/A#define NPI_PCI_ADD_HANDLE_SET(nxgep, ap) (nxgep->npi_pci_handle.regp = ap)
849N/A
849N/A#define NPI_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_handle.regh = ah)
849N/A#define NPI_ADD_HANDLE_SET(nxgep, ap) \
2624N/A nxgep->npi_handle.is_vraddr = B_FALSE; \
849N/A nxgep->npi_handle.function.instance = nxgep->instance; \
2624N/A nxgep->npi_handle.function.function = nxgep->function_num; \
2624N/A nxgep->npi_handle.nxgep = (void *) nxgep; \
2624N/A nxgep->npi_handle.regp = ap;
849N/A
849N/A#define NPI_REG_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_reg_handle.regh = ah)
849N/A#define NPI_REG_ADD_HANDLE_SET(nxgep, ap) \
849N/A nxgep->npi_reg_handle.is_vraddr = B_FALSE; \
849N/A nxgep->npi_handle.function.instance = nxgep->instance; \
849N/A nxgep->npi_handle.function.function = nxgep->function_num; \
849N/A nxgep->npi_reg_handle.nxgep = (void *) nxgep; \
2624N/A nxgep->npi_reg_handle.regp = ap;
849N/A
2624N/A#define NPI_MSI_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_msi_handle.regh = ah)
2624N/A#define NPI_MSI_ADD_HANDLE_SET(nxgep, ap) (nxgep->npi_msi_handle.regp = ap)
2624N/A
849N/A#define NPI_VREG_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_vreg_handle.regh = ah)
849N/A#define NPI_VREG_ADD_HANDLE_SET(nxgep, ap) \
849N/A nxgep->npi_vreg_handle.is_vraddr = B_TRUE; \
849N/A nxgep->npi_handle.function.instance = nxgep->instance; \
849N/A nxgep->npi_handle.function.function = nxgep->function_num; \
849N/A nxgep->npi_vreg_handle.nxgep = (void *) nxgep; \
849N/A nxgep->npi_vreg_handle.regp = ap;
2624N/A
849N/A#define NPI_V2REG_ACC_HANDLE_SET(nxgep, ah) (nxgep->npi_v2reg_handle.regh = ah)
2624N/A#define NPI_V2REG_ADD_HANDLE_SET(nxgep, ap) \
2624N/A nxgep->npi_v2reg_handle.is_vraddr = B_TRUE; \
2624N/A nxgep->npi_handle.function.instance = nxgep->instance; \
849N/A nxgep->npi_handle.function.function = nxgep->function_num; \
849N/A nxgep->npi_v2reg_handle.nxgep = (void *) nxgep; \
849N/A nxgep->npi_v2reg_handle.regp = ap;
849N/A
849N/A#define NPI_PCI_ACC_HANDLE_GET(nxgep) (nxgep->npi_pci_handle.regh)
849N/A#define NPI_PCI_ADD_HANDLE_GET(nxgep) (nxgep->npi_pci_handle.regp)
849N/A#define NPI_ACC_HANDLE_GET(nxgep) (nxgep->npi_handle.regh)
849N/A#define NPI_ADD_HANDLE_GET(nxgep) (nxgep->npi_handle.regp)
849N/A#define NPI_REG_ACC_HANDLE_GET(nxgep) (nxgep->npi_reg_handle.regh)
849N/A#define NPI_REG_ADD_HANDLE_GET(nxgep) (nxgep->npi_reg_handle.regp)
849N/A#define NPI_MSI_ACC_HANDLE_GET(nxgep) (nxgep->npi_msi_handle.regh)
849N/A#define NPI_MSI_ADD_HANDLE_GET(nxgep) (nxgep->npi_msi_handle.regp)
849N/A#define NPI_VREG_ACC_HANDLE_GET(nxgep) (nxgep->npi_vreg_handle.regh)
849N/A#define NPI_VREG_ADD_HANDLE_GET(nxgep) (nxgep->npi_vreg_handle.regp)
849N/A#define NPI_V2REG_ACC_HANDLE_GET(nxgep) (nxgep->npi_v2reg_handle.regh)
849N/A#define NPI_V2REG_ADD_HANDLE_GET(nxgep) (nxgep->npi_v2reg_handle.regp)
849N/A
849N/A#define NPI_DMA_ACC_HANDLE_SET(dmap, ah) (dmap->npi_handle.regh = ah)
849N/A#define NPI_DMA_ACC_HANDLE_GET(dmap) (dmap->npi_handle.regh)
849N/A
849N/A/*
849N/A * DMA handles.
849N/A */
849N/A#define NXGE_DESC_D_HANDLE_GET(desc) (desc.dma_handle)
849N/A#define NXGE_DESC_D_IOADD_GET(desc) (desc.dma_cookie.dmac_laddress)
849N/A#define NXGE_DMA_IOADD_GET(dma_cookie) (dma_cookie.dmac_laddress)
849N/A#define NXGE_DMA_AREA_IOADD_GET(dma_area) (dma_area.dma_cookie.dmac_laddress)
1008N/A
1008N/A#define LDV_ON(ldv, vector) ((vector >> ldv) & 0x1)
1008N/A#define LDV2_ON_1(ldv, vector) ((vector >> (ldv - 64)) & 0x1)
1008N/A#define LDV2_ON_2(ldv, vector) (((vector >> 5) >> (ldv - 64)) & 0x1)
849N/A
849N/Atypedef uint32_t nxge_status_t;
849N/A
1008N/Atypedef enum {
849N/A IDLE,
849N/A PROGRESS,
849N/A CONFIGURED
849N/A} dev_func_shared_t;
849N/A
849N/Atypedef enum {
849N/A DVMA,
849N/A DMA,
849N/A SDMA
849N/A} dma_method_t;
849N/A
849N/Atypedef enum {
849N/A BKSIZE_4K,
849N/A BKSIZE_8K,
849N/A BKSIZE_16K,
849N/A BKSIZE_32K
849N/A} nxge_rx_block_size_t;
849N/A
849N/A#ifdef TX_ONE_BUF
849N/A#define TX_BCOPY_MAX 1514
849N/A#else
849N/A#if defined(sun4v) && defined(NIU_LP_WORKAROUND)
849N/A#define TX_BCOPY_MAX 4096
849N/A#define TX_BCOPY_SIZE 4096
849N/A#else
849N/A#define TX_BCOPY_MAX 2048
849N/A#define TX_BCOPY_SIZE 2048
849N/A#endif
849N/A#endif
849N/A
849N/A#define TX_STREAM_MIN 512
849N/A#define TX_FASTDVMA_MIN 1024
849N/A
849N/A/*
849N/A * Send repeated FMA ereports or display messages about some non-fatal
849N/A * hardware errors only the the first NXGE_ERROR_SHOW_MAX -1 times
849N/A */
849N/A#define NXGE_ERROR_SHOW_MAX 2
849N/A
3634N/A
849N/A/*
849N/A * Defaults
849N/A */
849N/A#define NXGE_RDC_RCR_THRESHOLD 8
849N/A#define NXGE_RDC_RCR_TIMEOUT 16
849N/A
849N/A#define NXGE_RDC_RCR_THRESHOLD_MAX 1024
849N/A#define NXGE_RDC_RCR_TIMEOUT_MAX 64
849N/A#define NXGE_RDC_RCR_THRESHOLD_MIN 1
849N/A#define NXGE_RDC_RCR_TIMEOUT_MIN 1
849N/A#define NXGE_RCR_FULL_HEADER 1
849N/A
849N/A#define NXGE_IS_VLAN_PACKET(ptr) \
849N/A ((((struct ether_vlan_header *)ptr)->ether_tpid) == \
849N/A htons(VLAN_ETHERTYPE))
849N/A
849N/Atypedef enum {
849N/A NONE,
849N/A SMALL,
849N/A MEDIUM,
849N/A LARGE
849N/A} dma_size_t;
849N/A
849N/Atypedef enum {
849N/A USE_NONE,
849N/A USE_BCOPY,
849N/A USE_DVMA,
849N/A USE_DMA,
849N/A USE_SDMA
849N/A} dma_type_t;
849N/A
849N/Atypedef enum {
849N/A NOT_IN_USE,
849N/A HDR_BUF,
849N/A MTU_BUF,
849N/A RE_ASSEMBLY_BUF,
849N/A FREE_BUF
849N/A} rx_page_state_t;
849N/A
849N/Astruct _nxge_block_mv_t {
849N/A uint32_t msg_type;
849N/A dma_type_t dma_type;
849N/A};
849N/A
849N/Atypedef struct _nxge_block_mv_t nxge_block_mv_t, *p_nxge_block_mv_t;
849N/A
849N/Atypedef enum {
849N/A NIU_TYPE_NONE = 0,
849N/A
849N/A NEPTUNE_4_1GC =
849N/A (NXGE_PORT_1G_COPPER |
849N/A (NXGE_PORT_1G_COPPER << 4) |
849N/A (NXGE_PORT_1G_COPPER << 8) |
849N/A (NXGE_PORT_1G_COPPER << 12)),
849N/A
849N/A NEPTUNE_2_10GF =
849N/A (NXGE_PORT_10G_FIBRE |
849N/A (NXGE_PORT_10G_FIBRE << 4) |
849N/A (NXGE_PORT_NONE << 8) |
849N/A (NXGE_PORT_NONE << 12)),
3634N/A
849N/A NEPTUNE_2_10GF_2_1GC =
849N/A (NXGE_PORT_10G_FIBRE |
849N/A (NXGE_PORT_10G_FIBRE << 4) |
849N/A (NXGE_PORT_1G_COPPER << 8) |
849N/A (NXGE_PORT_1G_COPPER << 12)),
849N/A
849N/A NEPTUNE_1_10GF_3_1GC =
849N/A (NXGE_PORT_10G_FIBRE |
849N/A (NXGE_PORT_1G_COPPER << 4) |
849N/A (NXGE_PORT_1G_COPPER << 8) |
849N/A (NXGE_PORT_1G_COPPER << 12)),
849N/A
849N/A NEPTUNE_1_1GC_1_10GF_2_1GC =
849N/A (NXGE_PORT_1G_COPPER |
849N/A (NXGE_PORT_10G_FIBRE << 4) |
849N/A (NXGE_PORT_1G_COPPER << 8) |
849N/A (NXGE_PORT_1G_COPPER << 12)),
849N/A
849N/A N2_NIU =
849N/A (NXGE_PORT_RSVD |
849N/A (NXGE_PORT_RSVD << 4) |
849N/A (NXGE_PORT_RSVD << 8) |
849N/A (NXGE_PORT_RSVD << 12))
849N/A
849N/A} niu_type_t;
849N/A
849N/Atypedef enum {
849N/A P_NEPTUNE_NONE,
849N/A P_NEPTUNE_ATLAS_2PORT,
849N/A P_NEPTUNE_ATLAS_4PORT,
849N/A P_NEPTUNE_MARAMBA_P0,
849N/A P_NEPTUNE_MARAMBA_P1,
849N/A P_NEPTUNE_ALONSO,
849N/A P_NEPTUNE_NIU
849N/A} platform_type_t;
849N/A
849N/A#define NXGE_IS_VALID_NEPTUNE_TYPE(nxgep) \
849N/A (((nxgep->platform_type) == P_NEPTUNE_ATLAS_2PORT) || \
849N/A ((nxgep->platform_type) == P_NEPTUNE_ATLAS_4PORT) || \
849N/A ((nxgep->platform_type) == P_NEPTUNE_MARAMBA_P0) || \
849N/A ((nxgep->platform_type) == P_NEPTUNE_MARAMBA_P1) || \
849N/A ((nxgep->platform_type) == P_NEPTUNE_ALONSO))
849N/A
849N/A#define NXGE_IS_XAUI_PLATFORM(nxgep) \
849N/A (((nxgep->platform_type) == P_NEPTUNE_NIU) || \
849N/A ((nxgep->platform_type) == P_NEPTUNE_MARAMBA_P0) || \
849N/A ((nxgep->platform_type) == P_NEPTUNE_MARAMBA_P1))
849N/A
849N/A
849N/Atypedef enum {
849N/A CFG_DEFAULT = 0, /* default cfg */
849N/A CFG_EQUAL, /* Equal */
849N/A CFG_FAIR, /* Equal */
849N/A CFG_CLASSIFY,
849N/A CFG_L2_CLASSIFY,
849N/A CFG_L3_CLASSIFY,
849N/A CFG_L3_DISTRIBUTE,
849N/A CFG_L3_WEB,
849N/A CFG_L3_TCAM,
849N/A CFG_NOT_SPECIFIED,
849N/A CFG_CUSTOM /* Custom */
3634N/A} cfg_type_t;
849N/A
849N/Atypedef enum {
849N/A NO_MSG = 0x0, /* No message output or storage. */
849N/A CONSOLE = 0x1, /* Messages are go to the console. */
849N/A BUFFER = 0x2, /* Messages are go to the system buffer. */
849N/A CON_BUF = 0x3, /* Messages are go to the console and */
849N/A /* system buffer. */
849N/A VERBOSE = 0x4 /* Messages are go out only in VERBOSE node. */
849N/A} out_msg_t, *p_out_msg_t;
849N/A
849N/Atypedef enum {
849N/A DBG_NO_MSG = 0x0, /* No message output or storage. */
849N/A DBG_CONSOLE = 0x1, /* Messages are go to the console. */
849N/A DBG_BUFFER = 0x2, /* Messages are go to the system buffer. */
849N/A DBG_CON_BUF = 0x3, /* Messages are go to the console and */
849N/A /* system buffer. */
849N/A STR_LOG = 4 /* Sessage sent to streams logging driver. */
849N/A} out_dbgmsg_t, *p_out_dbgmsg_t;
849N/A
849N/A
849N/A
849N/A#if defined(_KERNEL) || defined(COSIM)
849N/A
849N/Atypedef struct ether_addr ether_addr_st, *p_ether_addr_t;
849N/Atypedef struct ether_header ether_header_t, *p_ether_header_t;
849N/Atypedef queue_t *p_queue_t;
849N/A
849N/A#if !defined(IODIAG)
849N/Atypedef mblk_t *p_mblk_t;
849N/A#endif
849N/A
849N/A/*
849N/A * Generic phy table to support different phy types.
849N/A */
849N/Atypedef struct _nxge_xcvr_table {
849N/A nxge_status_t (*serdes_init) (); /* Serdes init routine */
849N/A nxge_status_t (*xcvr_init) (); /* xcvr init routine */
849N/A nxge_status_t (*link_intr_stop) (); /* Link intr disable routine */
849N/A nxge_status_t (*link_intr_start) (); /* Link intr enable routine */
849N/A nxge_status_t (*check_link) (); /* Link check routine */
849N/A
849N/A uint32_t xcvr_inuse;
849N/A uint32_t xcvr_addr;
849N/A} nxge_xcvr_table_t, *p_nxge_xcvr_table_t;
849N/A
849N/A/*
849N/A * Common DMA data elements.
849N/A */
849N/Astruct _nxge_dma_common_t {
849N/A uint16_t dma_channel;
849N/A void *kaddrp;
849N/A void *first_kaddrp;
849N/A void *last_kaddrp;
849N/A void *ioaddr_pp;
849N/A void *first_ioaddr_pp;
849N/A void *last_ioaddr_pp;
849N/A ddi_dma_cookie_t dma_cookie;
849N/A uint32_t ncookies;
3634N/A
849N/A nxge_block_mv_t msg_dma_flags;
849N/A ddi_dma_handle_t dma_handle;
849N/A nxge_os_acc_handle_t acc_handle;
849N/A npi_handle_t npi_handle;
849N/A
849N/A size_t block_size;
849N/A uint32_t nblocks;
849N/A size_t alength;
849N/A uint_t offset;
849N/A uint_t dma_chunk_index;
849N/A void *orig_ioaddr_pp;
849N/A uint64_t orig_vatopa;
849N/A void *orig_kaddrp;
849N/A size_t orig_alength;
849N/A boolean_t contig_alloc_type;
849N/A};
849N/A
849N/Atypedef struct _nxge_t nxge_t, *p_nxge_t;
849N/Atypedef struct _nxge_dma_common_t nxge_dma_common_t, *p_nxge_dma_common_t;
849N/A
849N/Atypedef struct _nxge_dma_pool_t {
849N/A p_nxge_dma_common_t *dma_buf_pool_p;
849N/A uint32_t ndmas;
849N/A uint32_t *num_chunks;
849N/A boolean_t buf_allocated;
849N/A} nxge_dma_pool_t, *p_nxge_dma_pool_t;
849N/A
849N/A/*
849N/A * Each logical device (69):
849N/A * - LDG #
849N/A * - flag bits
849N/A * - masks.
849N/A * - interrupt handler function.
849N/A *
849N/A * Generic system interrupt handler with two arguments:
849N/A * (nxge_sys_intr_t)
849N/A * Per device instance data structure
849N/A * Logical group data structure.
849N/A *
849N/A * Logical device interrupt handler with two arguments:
849N/A * (nxge_ldv_intr_t)
849N/A * Per device instance data structure
849N/A * Logical device number
849N/A */
849N/Atypedef struct _nxge_ldg_t nxge_ldg_t, *p_nxge_ldg_t;
849N/Atypedef struct _nxge_ldv_t nxge_ldv_t, *p_nxge_ldv_t;
849N/Atypedef uint_t (*nxge_sys_intr_t)(void *arg1, void *arg2);
849N/Atypedef uint_t (*nxge_ldv_intr_t)(void *arg1, void *arg2);
849N/A
849N/A/*
849N/A * Each logical device Group (64) needs to have the following
849N/A * configurations:
849N/A * - timer counter (6 bits)
849N/A * - timer resolution (20 bits, number of system clocks)
849N/A * - system data (7 bits)
849N/A */
849N/Astruct _nxge_ldg_t {
849N/A uint8_t ldg; /* logical group number */
849N/A uint8_t vldg_index;
849N/A boolean_t arm;
849N/A boolean_t interrupted;
849N/A uint16_t ldg_timer; /* counter */
849N/A uint8_t func;
849N/A uint8_t vector;
849N/A uint8_t intdata;
849N/A uint8_t nldvs;
849N/A p_nxge_ldv_t ldvp;
849N/A nxge_sys_intr_t sys_intr_handler;
3634N/A uint_t (*ih_cb_func)(caddr_t, caddr_t);
849N/A p_nxge_t nxgep;
849N/A};
849N/A
849N/Astruct _nxge_ldv_t {
849N/A uint8_t ldg_assigned;
849N/A uint8_t ldv;
849N/A boolean_t is_rxdma;
849N/A boolean_t is_txdma;
849N/A boolean_t is_mif;
849N/A boolean_t is_mac;
849N/A boolean_t is_syserr;
849N/A boolean_t use_timer;
849N/A uint8_t channel;
849N/A uint8_t vdma_index;
849N/A uint8_t func;
849N/A p_nxge_ldg_t ldgp;
849N/A uint8_t ldv_flags;
849N/A boolean_t is_leve;
849N/A boolean_t is_edge;
849N/A uint8_t ldv_ldf_masks;
849N/A nxge_ldv_intr_t ldv_intr_handler;
849N/A uint_t (*ih_cb_func)(caddr_t, caddr_t);
849N/A p_nxge_t nxgep;
849N/A};
849N/A#endif
849N/A
849N/Atypedef struct _nxge_logical_page_t {
849N/A uint16_t dma;
849N/A uint16_t page;
849N/A boolean_t valid;
849N/A uint64_t mask;
849N/A uint64_t value;
849N/A uint64_t reloc;
849N/A uint32_t handle;
849N/A} nxge_logical_page_t, *p_nxge_logical_page_t;
849N/A
849N/A/*
849N/A * (Internal) return values from ioctl subroutines.
849N/A */
849N/Aenum nxge_ioc_reply {
849N/A IOC_INVAL = -1, /* bad, NAK with EINVAL */
849N/A IOC_DONE, /* OK, reply sent */
849N/A IOC_ACK, /* OK, just send ACK */
849N/A IOC_REPLY, /* OK, just send reply */
849N/A IOC_RESTART_ACK, /* OK, restart & ACK */
849N/A IOC_RESTART_REPLY /* OK, restart & reply */
849N/A};
849N/A
849N/Atypedef struct _pci_cfg_t {
849N/A uint16_t vendorid;
849N/A uint16_t devid;
849N/A uint16_t command;
849N/A uint16_t status;
849N/A uint8_t revid;
849N/A uint8_t res0;
849N/A uint16_t junk1;
849N/A uint8_t cache_line;
849N/A uint8_t latency;
849N/A uint8_t header;
849N/A uint8_t bist;
3634N/A uint32_t base;
849N/A uint32_t base14;
849N/A uint32_t base18;
849N/A uint32_t base1c;
849N/A uint32_t base20;
849N/A uint32_t base24;
849N/A uint32_t base28;
849N/A uint32_t base2c;
849N/A uint32_t base30;
849N/A uint32_t res1[2];
849N/A uint8_t int_line;
849N/A uint8_t int_pin;
849N/A uint8_t min_gnt;
849N/A uint8_t max_lat;
849N/A} pci_cfg_t, *p_pci_cfg_t;
849N/A
849N/A#if defined(_KERNEL) || defined(COSIM)
849N/A
849N/Atypedef struct _dev_regs_t {
849N/A nxge_os_acc_handle_t nxge_pciregh; /* PCI config DDI IO handle */
849N/A p_pci_cfg_t nxge_pciregp; /* mapped PCI registers */
849N/A
849N/A nxge_os_acc_handle_t nxge_regh; /* device DDI IO (BAR 0) */
849N/A void *nxge_regp; /* mapped device registers */
849N/A
849N/A nxge_os_acc_handle_t nxge_msix_regh; /* MSI/X DDI handle (BAR 2) */
849N/A void *nxge_msix_regp; /* MSI/X register */
849N/A
849N/A nxge_os_acc_handle_t nxge_vir_regh; /* virtualization (BAR 4) */
849N/A unsigned char *nxge_vir_regp; /* virtualization register */
849N/A
849N/A nxge_os_acc_handle_t nxge_vir2_regh; /* second virtualization */
849N/A unsigned char *nxge_vir2_regp; /* second virtualization */
849N/A
849N/A nxge_os_acc_handle_t nxge_romh; /* fcode rom handle */
849N/A unsigned char *nxge_romp; /* fcode pointer */
849N/A} dev_regs_t, *p_dev_regs_t;
849N/A
2624N/A
849N/Atypedef struct _nxge_mac_addr_t {
849N/A ether_addr_t addr;
849N/A uint_t flags;
849N/A} nxge_mac_addr_t;
849N/A
849N/A/*
849N/A * The hardware supports 1 unique MAC and 16 alternate MACs (num_mmac)
849N/A * for each XMAC port and supports 1 unique MAC and 7 alternate MACs
849N/A * for each BMAC port. The number of MACs assigned by the factory is
849N/A * different and is as follows,
849N/A * BMAC port: num_factory_mmac = num_mmac = 7
849N/A * XMAC port on a 2-port NIC: num_factory_mmac = num_mmac - 1 = 15
849N/A * XMAC port on a 4-port NIC: num_factory_mmac = 7
849N/A * So num_factory_mmac is smaller than num_mmac. nxge_m_mmac_add uses
849N/A * num_mmac and nxge_m_mmac_reserve uses num_factory_mmac.
849N/A *
849N/A * total_factory_macs is the total number of factory MACs, including
849N/A * the unique MAC, assigned to a Neptune based NIC card, it is 32.
849N/A */
849N/Atypedef struct _nxge_mmac_t {
849N/A uint8_t total_factory_macs;
849N/A uint8_t num_mmac;
849N/A uint8_t num_factory_mmac;
849N/A nxge_mac_addr_t mac_pool[XMAC_MAX_ADDR_ENTRY];
849N/A ether_addr_t factory_mac_pool[XMAC_MAX_ADDR_ENTRY];
849N/A uint8_t naddrfree; /* number of alt mac addr available */
849N/A} nxge_mmac_t;
849N/A
849N/A/*
849N/A * mmac stats structure
849N/A */
849N/Atypedef struct _nxge_mmac_stats_t {
849N/A uint8_t mmac_max_cnt;
849N/A uint8_t mmac_avail_cnt;
849N/A struct ether_addr mmac_avail_pool[16];
849N/A} nxge_mmac_stats_t, *p_nxge_mmac_stats_t;
849N/A
849N/A#define NXGE_MAX_MMAC_ADDRS 32
849N/A#define NXGE_NUM_MMAC_ADDRS 8
849N/A#define NXGE_NUM_OF_PORTS_QUAD 4
849N/A#define NXGE_NUM_OF_PORTS_DUAL 2
849N/A
849N/A#define NXGE_QGC_LP_BM_STR "501-7606"
849N/A#define NXGE_2XGF_LP_BM_STR "501-7283"
849N/A#define NXGE_QGC_PEM_BM_STR "501-7765"
849N/A#define NXGE_2XGF_PEM_BM_STR "501-7626"
849N/A#define NXGE_ALONSO_BM_STR "373-0202-01"
849N/A#define NXGE_ALONSO_MODEL_STR "SUNW,CP3220"
849N/A#define NXGE_EROM_LEN 1048576
849N/A
849N/A#endif
849N/A
849N/A#include <sys/nxge/nxge_common_impl.h>
849N/A#include <sys/nxge/nxge_common.h>
849N/A#include <sys/nxge/nxge_txc.h>
849N/A#include <sys/nxge/nxge_rxdma.h>
849N/A#include <sys/nxge/nxge_txdma.h>
849N/A#include <sys/nxge/nxge_fflp.h>
849N/A#include <sys/nxge/nxge_ipp.h>
849N/A#include <sys/nxge/nxge_zcp.h>
849N/A#include <sys/nxge/nxge_fzc.h>
849N/A#include <sys/nxge/nxge_flow.h>
849N/A#include <sys/nxge/nxge_virtual.h>
849N/A
849N/A#include <npi_espc.h>
849N/A#include <npi_vir.h>
849N/A
849N/A#include <sys/nxge/nxge.h>
849N/A
849N/A#include <sys/modctl.h>
849N/A#include <sys/pattr.h>
849N/A
849N/Aextern int secpolicy_net_config(const cred_t *, boolean_t);
849N/Aextern void nxge_fm_report_error(p_nxge_t, uint8_t,
849N/A uint8_t, nxge_fm_ereport_id_t);
849N/Aextern int fm_check_acc_handle(ddi_acc_handle_t);
849N/Aextern int fm_check_dma_handle(ddi_dma_handle_t);
849N/A
849N/A/* nxge_classify.c */
849N/Anxge_status_t nxge_classify_init(p_nxge_t);
849N/Anxge_status_t nxge_classify_uninit(p_nxge_t);
849N/Anxge_status_t nxge_set_hw_classify_config(p_nxge_t);
849N/Anxge_status_t nxge_classify_exit_sw(p_nxge_t);
849N/A
849N/A/* nxge_fflp.c */
849N/Avoid nxge_put_tcam(p_nxge_t, p_mblk_t);
849N/Avoid nxge_get_tcam(p_nxge_t, p_mblk_t);
849N/Anxge_status_t nxge_classify_init_hw(p_nxge_t);
849N/Anxge_status_t nxge_classify_init_sw(p_nxge_t);
849N/Anxge_status_t nxge_fflp_ip_class_config_all(p_nxge_t);
849N/Anxge_status_t nxge_fflp_ip_class_config(p_nxge_t, tcam_class_t,
849N/A uint32_t);
849N/A
849N/Anxge_status_t nxge_fflp_ip_class_config_get(p_nxge_t,
849N/A tcam_class_t,
849N/A uint32_t *);
849N/A
849N/Anxge_status_t nxge_cfg_ip_cls_flow_key(p_nxge_t, tcam_class_t,
849N/A uint32_t);
849N/A
849N/Anxge_status_t nxge_fflp_ip_usr_class_config(p_nxge_t, tcam_class_t,
849N/A uint32_t);
849N/A
849N/Auint64_t nxge_classify_get_cfg_value(p_nxge_t, uint8_t, uint8_t);
849N/Anxge_status_t nxge_add_flow(p_nxge_t, flow_resource_t *);
849N/Anxge_status_t nxge_fflp_config_tcam_enable(p_nxge_t);
849N/Anxge_status_t nxge_fflp_config_tcam_disable(p_nxge_t);
849N/A
849N/Anxge_status_t nxge_fflp_config_hash_lookup_enable(p_nxge_t);
849N/Anxge_status_t nxge_fflp_config_hash_lookup_disable(p_nxge_t);
849N/A
849N/Anxge_status_t nxge_fflp_config_llc_snap_enable(p_nxge_t);
849N/Anxge_status_t nxge_fflp_config_llc_snap_disable(p_nxge_t);
849N/A
849N/Anxge_status_t nxge_logical_mac_assign_rdc_table(p_nxge_t, uint8_t);
849N/Anxge_status_t nxge_fflp_config_vlan_table(p_nxge_t, uint16_t);
849N/A
849N/Anxge_status_t nxge_fflp_set_hash1(p_nxge_t, uint32_t);
849N/A
849N/Anxge_status_t nxge_fflp_set_hash2(p_nxge_t, uint16_t);
849N/A
849N/Anxge_status_t nxge_fflp_init_hostinfo(p_nxge_t);
849N/A
849N/Avoid nxge_handle_tcam_fragment_bug(p_nxge_t);
849N/Anxge_status_t nxge_fflp_hw_reset(p_nxge_t);
849N/Anxge_status_t nxge_fflp_handle_sys_errors(p_nxge_t);
849N/Anxge_status_t nxge_zcp_handle_sys_errors(p_nxge_t);
849N/A
849N/A/* nxge_kstats.c */
849N/Avoid nxge_init_statsp(p_nxge_t);
849N/Avoid nxge_setup_kstats(p_nxge_t);
849N/Avoid nxge_destroy_kstats(p_nxge_t);
2624N/Aint nxge_port_kstat_update(kstat_t *, int);
849N/Avoid nxge_save_cntrs(p_nxge_t);
849N/A
849N/Aint nxge_m_stat(void *arg, uint_t, uint64_t *);
849N/A
849N/A/* nxge_hw.c */
849N/Avoid
849N/Anxge_hw_ioctl(p_nxge_t, queue_t *, mblk_t *, struct iocblk *);
849N/Avoid nxge_loopback_ioctl(p_nxge_t, queue_t *, mblk_t *, struct iocblk *);
849N/Avoid nxge_global_reset(p_nxge_t);
849N/Auint_t nxge_intr(void *, void *);
849N/Avoid nxge_intr_enable(p_nxge_t);
849N/Avoid nxge_intr_disable(p_nxge_t);
849N/Avoid nxge_hw_blank(void *arg, time_t, uint_t);
849N/Avoid nxge_hw_id_init(p_nxge_t);
849N/Avoid nxge_hw_init_niu_common(p_nxge_t);
849N/Avoid nxge_intr_hw_enable(p_nxge_t);
849N/Avoid nxge_intr_hw_disable(p_nxge_t);
849N/Avoid nxge_hw_stop(p_nxge_t);
849N/Avoid nxge_global_reset(p_nxge_t);
849N/Avoid nxge_check_hw_state(p_nxge_t);
849N/A
849N/Avoid nxge_rxdma_channel_put64(nxge_os_acc_handle_t,
849N/A void *, uint32_t, uint16_t,
849N/A uint64_t);
849N/Auint64_t nxge_rxdma_channel_get64(nxge_os_acc_handle_t, void *,
2624N/A uint32_t, uint16_t);
849N/A
849N/A
849N/Avoid nxge_get32(p_nxge_t, p_mblk_t);
849N/Avoid nxge_put32(p_nxge_t, p_mblk_t);
849N/A
849N/Avoid nxge_hw_set_mac_modes(p_nxge_t);
849N/A
849N/A/* nxge_send.c. */
849N/Auint_t nxge_reschedule(caddr_t);
849N/A
849N/A/* nxge_rxdma.c */
849N/Anxge_status_t nxge_rxdma_cfg_rdcgrp_default_rdc(p_nxge_t,
849N/A uint8_t, uint8_t);
849N/A
849N/Anxge_status_t nxge_rxdma_cfg_port_default_rdc(p_nxge_t,
849N/A uint8_t, uint8_t);
849N/Anxge_status_t nxge_rxdma_cfg_rcr_threshold(p_nxge_t, uint8_t,
849N/A uint16_t);
849N/Anxge_status_t nxge_rxdma_cfg_rcr_timeout(p_nxge_t, uint8_t,
849N/A uint16_t, uint8_t);
849N/A
849N/A/* nxge_ndd.c */
849N/Avoid nxge_get_param_soft_properties(p_nxge_t);
849N/Avoid nxge_copy_hw_default_to_param(p_nxge_t);
849N/Avoid nxge_copy_param_hw_to_config(p_nxge_t);
849N/Avoid nxge_setup_param(p_nxge_t);
849N/Avoid nxge_init_param(p_nxge_t);
2624N/Avoid nxge_destroy_param(p_nxge_t);
849N/Aboolean_t nxge_check_rxdma_rdcgrp_member(p_nxge_t, uint8_t, uint8_t);
849N/Aboolean_t nxge_check_rxdma_port_member(p_nxge_t, uint8_t);
849N/Aboolean_t nxge_check_rdcgrp_port_member(p_nxge_t, uint8_t);
849N/A
849N/Aboolean_t nxge_check_txdma_port_member(p_nxge_t, uint8_t);
849N/A
849N/Aint nxge_param_get_generic(p_nxge_t, queue_t *, mblk_t *, caddr_t);
849N/Aint nxge_param_set_generic(p_nxge_t, queue_t *, mblk_t *, char *, caddr_t);
849N/Aint nxge_get_default(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
849N/Aint nxge_set_default(p_nxge_t, queue_t *, p_mblk_t, char *, caddr_t);
849N/Aint nxge_nd_get_names(p_nxge_t, queue_t *, p_mblk_t, caddr_t);
849N/Aint nxge_mk_mblk_tail_space(p_mblk_t, p_mblk_t *, size_t);
849N/Along nxge_strtol(char *, char **, int);
849N/Aboolean_t nxge_param_get_instance(queue_t *, mblk_t *);
849N/Avoid nxge_param_ioctl(p_nxge_t, queue_t *, mblk_t *, struct iocblk *);
849N/Aboolean_t nxge_nd_load(caddr_t *, char *, pfi_t, pfi_t, caddr_t);
849N/Avoid nxge_nd_free(caddr_t *);
849N/Aint nxge_nd_getset(p_nxge_t, queue_t *, caddr_t, p_mblk_t);
849N/A
849N/Avoid nxge_set_lb_normal(p_nxge_t);
849N/Aboolean_t nxge_set_lb(p_nxge_t, queue_t *, p_mblk_t);
849N/A
849N/A/* nxge_virtual.c */
849N/Anxge_status_t nxge_cntlops(dev_info_t *, nxge_ctl_enum_t, void *, void *);
849N/Avoid nxge_common_lock_get(p_nxge_t);
849N/Avoid nxge_common_lock_free(p_nxge_t);
849N/A
849N/Anxge_status_t nxge_get_config_properties(p_nxge_t);
849N/Avoid nxge_get_xcvr_properties(p_nxge_t);
849N/Avoid nxge_init_vlan_config(p_nxge_t);
849N/Avoid nxge_init_mac_config(p_nxge_t);
849N/A
849N/A
849N/Avoid nxge_init_logical_devs(p_nxge_t);
849N/Aint nxge_init_ldg_intrs(p_nxge_t);
849N/A
849N/Avoid nxge_set_ldgimgmt(p_nxge_t, uint32_t, boolean_t,
849N/A uint32_t);
849N/A
849N/Avoid nxge_init_fzc_txdma_channels(p_nxge_t);
849N/A
2624N/Anxge_status_t nxge_init_fzc_txdma_channel(p_nxge_t, uint16_t,
849N/A p_tx_ring_t, p_tx_mbox_t);
849N/Anxge_status_t nxge_init_fzc_txdma_port(p_nxge_t);
849N/A
849N/Anxge_status_t nxge_init_fzc_rxdma_channel(p_nxge_t, uint16_t,
849N/A p_rx_rbr_ring_t, p_rx_rcr_ring_t, p_rx_mbox_t);
849N/A
849N/Anxge_status_t nxge_init_fzc_rdc_tbl(p_nxge_t);
849N/Anxge_status_t nxge_init_fzc_rx_common(p_nxge_t);
849N/Anxge_status_t nxge_init_fzc_rxdma_port(p_nxge_t);
849N/A
849N/Anxge_status_t nxge_init_fzc_rxdma_channel_pages(p_nxge_t,
849N/A uint16_t, p_rx_rbr_ring_t);
849N/Anxge_status_t nxge_init_fzc_rxdma_channel_red(p_nxge_t,
849N/A uint16_t, p_rx_rcr_ring_t);
849N/A
849N/Anxge_status_t nxge_init_fzc_rxdma_channel_clrlog(p_nxge_t,
849N/A uint16_t, p_rx_rbr_ring_t);
849N/A
849N/A
849N/Anxge_status_t nxge_init_fzc_txdma_channel_pages(p_nxge_t,
849N/A uint16_t, p_tx_ring_t);
849N/A
849N/Anxge_status_t nxge_init_fzc_txdma_channel_drr(p_nxge_t, uint16_t,
p_tx_ring_t);
nxge_status_t nxge_init_fzc_txdma_port(p_nxge_t);
void nxge_init_fzc_ldg_num(p_nxge_t);
void nxge_init_fzc_sys_int_data(p_nxge_t);
void nxge_init_fzc_ldg_int_timer(p_nxge_t);
nxge_status_t nxge_intr_mask_mgmt_set(p_nxge_t, boolean_t on);
/* MAC functions */
nxge_status_t nxge_mac_init(p_nxge_t);
nxge_status_t nxge_link_init(p_nxge_t);
nxge_status_t nxge_xif_init(p_nxge_t);
nxge_status_t nxge_pcs_init(p_nxge_t);
nxge_status_t nxge_mac_ctrl_init(p_nxge_t);
nxge_status_t nxge_serdes_init(p_nxge_t);
nxge_status_t nxge_serdes_reset(p_nxge_t);
nxge_status_t nxge_xcvr_find(p_nxge_t);
nxge_status_t nxge_get_xcvr_type(p_nxge_t);
nxge_status_t nxge_setup_xcvr_table(p_nxge_t);
nxge_status_t nxge_xcvr_init(p_nxge_t);
nxge_status_t nxge_tx_mac_init(p_nxge_t);
nxge_status_t nxge_rx_mac_init(p_nxge_t);
nxge_status_t nxge_tx_mac_enable(p_nxge_t);
nxge_status_t nxge_tx_mac_disable(p_nxge_t);
nxge_status_t nxge_rx_mac_enable(p_nxge_t);
nxge_status_t nxge_rx_mac_disable(p_nxge_t);
nxge_status_t nxge_tx_mac_reset(p_nxge_t);
nxge_status_t nxge_rx_mac_reset(p_nxge_t);
nxge_status_t nxge_link_intr(p_nxge_t, link_intr_enable_t);
nxge_status_t nxge_mii_xcvr_init(p_nxge_t);
nxge_status_t nxge_mii_xcvr_fiber_init(p_nxge_t);
nxge_status_t nxge_mii_read(p_nxge_t, uint8_t,
uint8_t, uint16_t *);
nxge_status_t nxge_mii_write(p_nxge_t, uint8_t,
uint8_t, uint16_t);
nxge_status_t nxge_mdio_read(p_nxge_t, uint8_t, uint8_t,
uint16_t, uint16_t *);
nxge_status_t nxge_mdio_write(p_nxge_t, uint8_t,
uint8_t, uint16_t, uint16_t);
nxge_status_t nxge_mii_check(p_nxge_t, mii_bmsr_t,
mii_bmsr_t, nxge_link_state_t *);
nxge_status_t nxge_pcs_check(p_nxge_t, uint8_t portn, nxge_link_state_t *);
nxge_status_t nxge_add_mcast_addr(p_nxge_t, struct ether_addr *);
nxge_status_t nxge_del_mcast_addr(p_nxge_t, struct ether_addr *);
nxge_status_t nxge_set_mac_addr(p_nxge_t, struct ether_addr *);
nxge_status_t nxge_check_bcm8704_link(p_nxge_t, boolean_t *);
void nxge_link_is_down(p_nxge_t);
void nxge_link_is_up(p_nxge_t);
nxge_status_t nxge_link_monitor(p_nxge_t, link_mon_enable_t);
uint32_t crc32_mchash(p_ether_addr_t);
nxge_status_t nxge_set_promisc(p_nxge_t, boolean_t);
nxge_status_t nxge_mac_handle_sys_errors(p_nxge_t);
nxge_status_t nxge_10g_link_led_on(p_nxge_t);
nxge_status_t nxge_10g_link_led_off(p_nxge_t);
nxge_status_t nxge_scan_ports_phy(p_nxge_t, p_nxge_hw_list_t);
boolean_t nxge_is_valid_local_mac(ether_addr_st);
/* espc (sprom) prototypes */
nxge_status_t nxge_espc_mac_addrs_get(p_nxge_t);
nxge_status_t nxge_espc_num_macs_get(p_nxge_t, uint8_t *);
nxge_status_t nxge_espc_num_ports_get(p_nxge_t);
nxge_status_t nxge_espc_phy_type_get(p_nxge_t);
nxge_status_t nxge_espc_verify_chksum(p_nxge_t);
void nxge_espc_get_next_mac_addr(uint8_t *, uint8_t, struct ether_addr *);
void nxge_vpd_info_get(p_nxge_t);
void nxge_debug_msg(p_nxge_t, uint64_t, char *, ...);
int nxge_get_nports(p_nxge_t);
uint64_t hv_niu_rx_logical_page_conf(uint64_t, uint64_t,
uint64_t, uint64_t);
#pragma weak hv_niu_rx_logical_page_conf
uint64_t hv_niu_rx_logical_page_info(uint64_t, uint64_t,
uint64_t *, uint64_t *);
#pragma weak hv_niu_rx_logical_page_info
uint64_t hv_niu_tx_logical_page_conf(uint64_t, uint64_t,
uint64_t, uint64_t);
#pragma weak hv_niu_tx_logical_page_conf
uint64_t hv_niu_tx_logical_page_info(uint64_t, uint64_t,
uint64_t *, uint64_t *);
#pragma weak hv_niu_tx_logical_page_info
#ifdef NXGE_DEBUG
char *nxge_dump_packet(char *, int);
#endif
#endif /* !_ASM */
#ifdef __cplusplus
}
#endif
#endif /* _SYS_NXGE_NXGE_IMPL_H */