nxge_impl.h revision 330cd344428055700fc03c465aa794ab0344c63d
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2008 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_NXGE_NXGE_IMPL_H
#define _SYS_NXGE_NXGE_IMPL_H
#ifdef __cplusplus
extern "C" {
#endif
/*
* NIU HV API version definitions.
*/
#define NIU_MAJOR_VER 1
#define NIU_MINOR_VER 1
/*
* NIU HV API v1.0 definitions
*/
#define N2NIU_RX_LP_CONF 0x142
#define N2NIU_RX_LP_INFO 0x143
#define N2NIU_TX_LP_CONF 0x144
#define N2NIU_TX_LP_INFO 0x145
#ifndef _ASM
#include <sys/byteorder.h>
#include <sys/ethernet.h>
#include <sys/ddi_intr.h>
#include <sys/mac_impl.h>
#include <sys/mac_ether.h>
#if defined(sun4v)
#include <sys/hypervisor_api.h>
#include <sys/machsystm.h>
#endif
/*
* Handy macros (taken from bge driver)
*/
#define RBR_SIZE 4
(flag)))
(flag)))
(flag)))
(flag)))
(area).block_size, \
(flag)))
/*
* NPI related macros
*/
/*
* DMA handles.
*/
typedef uint32_t nxge_status_t;
typedef enum {
IDLE,
typedef enum {
DVMA,
DMA,
} dma_method_t;
typedef enum {
#ifdef TX_ONE_BUF
#define TX_BCOPY_MAX 1514
#else
#if defined(sun4v) && defined(NIU_LP_WORKAROUND)
#define TX_BCOPY_MAX 4096
#define TX_BCOPY_SIZE 4096
#else
#define TX_BCOPY_MAX 2048
#define TX_BCOPY_SIZE 2048
#endif
#endif
#define TX_STREAM_MIN 512
#define TX_FASTDVMA_MIN 1024
/*
* Send repeated FMA ereports or display messages about some non-fatal
* hardware errors only the the first NXGE_ERROR_SHOW_MAX -1 times
*/
#define NXGE_ERROR_SHOW_MAX 2
/*
* Defaults
*/
#define NXGE_RDC_RCR_THRESHOLD 8
#define NXGE_RDC_RCR_TIMEOUT 16
#define NXGE_RDC_RCR_THRESHOLD_MAX 1024
#define NXGE_RDC_RCR_TIMEOUT_MAX 64
#define NXGE_RDC_RCR_THRESHOLD_MIN 1
#define NXGE_RDC_RCR_TIMEOUT_MIN 1
#define NXGE_RCR_FULL_HEADER 1
#define NXGE_IS_VLAN_PACKET(ptr) \
typedef enum {
NONE,
} dma_size_t;
typedef enum {
} dma_type_t;
typedef enum {
struct _nxge_block_mv_t {
};
typedef enum {
NIU_TYPE_NONE = 0,
/* QGC NIC */
(NXGE_PORT_1G_COPPER << 4) |
(NXGE_PORT_1G_COPPER << 8) |
(NXGE_PORT_1G_COPPER << 12)),
/* Huron: 2 fiber XAUI cards */
(NXGE_PORT_10G_FIBRE << 4) |
(NXGE_PORT_NONE << 8) |
(NXGE_PORT_NONE << 12)),
/* Huron: port0 is a TN1010 copper XAUI */
(NXGE_PORT_NONE << 4) |
(NXGE_PORT_NONE << 8) |
(NXGE_PORT_NONE << 12)),
/* Huron: port1 is a TN1010 copper XAUI */
(NXGE_PORT_TN1010 << 4) |
(NXGE_PORT_NONE << 8) |
(NXGE_PORT_NONE << 12)),
/* Huron: 2 TN1010 copper XAUI cards */
(NXGE_PORT_TN1010 << 4) |
(NXGE_PORT_NONE << 8) |
(NXGE_PORT_NONE << 12)),
/* Huron: port0 is fiber XAUI, port1 is copper XAUI */
(NXGE_PORT_TN1010 << 4) |
(NXGE_PORT_NONE << 8) |
(NXGE_PORT_NONE << 12)),
/* Huron: port0 is copper XAUI, port1 is fiber XAUI */
(NXGE_PORT_10G_FIBRE << 4) |
(NXGE_PORT_NONE << 8) |
(NXGE_PORT_NONE << 12)),
/* Maramba: port0 and port1 are fiber XAUIs */
(NXGE_PORT_10G_FIBRE << 4) |
(NXGE_PORT_1G_COPPER << 8) |
(NXGE_PORT_1G_COPPER << 12)),
/* Maramba: port0 and port1 are copper TN1010 XAUIs */
(NXGE_PORT_TN1010 << 4) |
(NXGE_PORT_1G_COPPER << 8) |
(NXGE_PORT_1G_COPPER << 12)),
/* Maramba: port0 is copper XAUI, port1 is Fiber XAUI */
(NXGE_PORT_10G_FIBRE << 4) |
(NXGE_PORT_1G_COPPER << 8) |
(NXGE_PORT_1G_COPPER << 12)),
/* Maramba: port0 is fiber XAUI, port1 is copper XAUI */
(NXGE_PORT_TN1010 << 4) |
(NXGE_PORT_1G_COPPER << 8) |
(NXGE_PORT_1G_COPPER << 12)),
/* Maramba: port0 is fiber XAUI */
(NXGE_PORT_1G_COPPER << 4) |
(NXGE_PORT_1G_COPPER << 8) |
(NXGE_PORT_1G_COPPER << 12)),
/* Maramba: port0 is TN1010 copper XAUI */
(NXGE_PORT_1G_COPPER << 4) |
(NXGE_PORT_1G_COPPER << 8) |
(NXGE_PORT_1G_COPPER << 12)),
/* Maramba: port1 is fiber XAUI */
(NXGE_PORT_10G_FIBRE << 4) |
(NXGE_PORT_1G_COPPER << 8) |
(NXGE_PORT_1G_COPPER << 12)),
/* Maramba: port1 is TN1010 copper XAUI */
(NXGE_PORT_TN1010 << 4) |
(NXGE_PORT_1G_COPPER << 8) |
(NXGE_PORT_1G_COPPER << 12)),
(NXGE_PORT_NONE << 4) |
(NXGE_PORT_1G_RGMII_FIBER << 8) |
(NXGE_PORT_1G_RGMII_FIBER << 12)),
(NXGE_PORT_10G_FIBRE << 4) |
(NXGE_PORT_1G_RGMII_FIBER << 8) |
(NXGE_PORT_1G_RGMII_FIBER << 12)),
N2_NIU =
(NXGE_PORT_RSVD << 4) |
(NXGE_PORT_RSVD << 8) |
(NXGE_PORT_RSVD << 12))
} niu_type_t;
/*
* P_NEPTUNE_GENERIC:
* The cover-all case for Neptune (as opposed to NIU) where we do not
* care the exact platform as we do not do anything that is platform
* specific.
* P_NEPTUNE_ATLAS_2PORT:
* Dual Port Fiber Neptune based NIC (2XGF)
* P_NEPTUNE_ATLAS_4PORT:
* Quad Port Copper Neptune based NIC (QGC)
* P_NEPTUNE_NIU:
* This is NIU. Could be Huron, Glendale, Monza or any other NIU based
* platform.
*/
typedef enum {
#define NXGE_IS_VALID_NEPTUNE_TYPE(nxgep) \
#define NXGE_IS_XAUI_PLATFORM(nxgep) \
typedef enum {
CFG_DEFAULT = 0, /* default cfg */
CFG_EQUAL, /* Equal */
CFG_FAIR, /* Equal */
CFG_CUSTOM /* Custom */
} cfg_type_t;
typedef enum {
/* system buffer. */
} out_msg_t, *p_out_msg_t;
typedef enum {
/* system buffer. */
typedef enum {
DDI_MEM_ALLOC, /* default (use ddi_dma_mem_alloc) */
KMEM_ALLOC, /* use kmem_alloc(). */
CONTIG_MEM_ALLOC /* use contig_mem_alloc() (N2/NIU only) */
#define BUF_ALLOCATED 0x00000001
#define BUF_ALLOCATED_WAIT_FREE 0x00000002
/*
* Generic phy table to support different phy types.
*
* The argument for check_link is nxgep, which is passed to check_link
* as an argument to the timer routine.
*/
typedef struct _nxge_xcvr_table {
/*
* Common DMA data elements.
*/
struct _nxge_dma_common_t {
void *kaddrp;
void *last_kaddrp;
void *ioaddr_pp;
void *first_ioaddr_pp;
void *last_ioaddr_pp;
void *orig_ioaddr_pp;
void *orig_kaddrp;
/*
* Receive buffers may be allocated using
* kmem_alloc(). The buffer free function
* depends on its allocation function.
*/
};
struct _nxge_dma_pool_t {
};
/*
* Each logical device (69):
* - LDG #
* - flag bits
* - masks.
* - interrupt handler function.
*
* Generic system interrupt handler with two arguments:
* (nxge_sys_intr_t)
* Per device instance data structure
* Logical group data structure.
*
* Logical device interrupt handler with two arguments:
* (nxge_ldv_intr_t)
* Per device instance data structure
* Logical device number
*/
/*
* Each logical device Group (64) needs to have the following
* configurations:
* - timer counter (6 bits)
* - timer resolution (20 bits, number of system clocks)
* - system data (7 bits)
*/
struct _nxge_ldg_t {
};
struct _nxge_ldv_t {
};
typedef struct _nxge_logical_page_t {
/*
* (Internal) return values from ioctl subroutines.
*/
enum nxge_ioc_reply {
IOC_DONE, /* OK, reply sent */
IOC_ACK, /* OK, just send ACK */
IOC_REPLY, /* OK, just send reply */
IOC_RESTART_ACK, /* OK, restart & ACK */
IOC_RESTART_REPLY /* OK, restart & reply */
};
typedef struct _pci_cfg_t {
} pci_cfg_t, *p_pci_cfg_t;
typedef struct _dev_regs_t {
void *nxge_regp; /* mapped device registers */
void *nxge_msix_regp; /* MSI/X register */
unsigned char *nxge_vir_regp; /* virtualization register */
unsigned char *nxge_vir2_regp; /* second virtualization */
unsigned char *nxge_romp; /* fcode pointer */
} dev_regs_t, *p_dev_regs_t;
typedef struct _nxge_mac_addr_t {
/*
* The hardware supports 1 unique MAC and 16 alternate MACs (num_mmac)
* for each XMAC port and supports 1 unique MAC and 7 alternate MACs
* for each BMAC port. The number of MACs assigned by the factory is
* different and is as follows,
* BMAC port: num_factory_mmac = num_mmac = 7
* XMAC port on a 2-port NIC: num_factory_mmac = num_mmac - 1 = 15
* XMAC port on a 4-port NIC: num_factory_mmac = 7
* So num_factory_mmac is smaller than num_mmac. nxge_m_mmac_add uses
* num_mmac and nxge_m_mmac_reserve uses num_factory_mmac.
*
* total_factory_macs is the total number of factory MACs, including
* the unique MAC, assigned to a Neptune based NIC card, it is 32.
*/
typedef struct _nxge_mmac_t {
} nxge_mmac_t;
/*
* mmac stats structure
*/
typedef struct _nxge_mmac_stats_t {
#define NXGE_MAX_MMAC_ADDRS 32
#define NXGE_NUM_MMAC_ADDRS 8
#define NXGE_NUM_OF_PORTS_QUAD 4
#define NXGE_NUM_OF_PORTS_DUAL 2
#define NXGE_QGC_LP_BM_STR "501-7606"
#define NXGE_2XGF_LP_BM_STR "501-7283"
#define NXGE_QGC_PEM_BM_STR "501-7765"
#define NXGE_2XGF_PEM_BM_STR "501-7626"
#define NXGE_ALONSO_BM_STR "373-0202-01"
#define NXGE_ALONSO_MODEL_STR "SUNW,CP3220"
#define NXGE_RFEM_BM_STR "501-7961-01"
#define NXGE_RFEM_MODEL_STR "SUNW,pcie-rfem"
#define NXGE_ARTM_BM_STR "375-3544-01"
#define NXGE_ARTM_MODEL_STR "SUNW,pcie-artm"
/* ROCK OBP creates a compatible property for ROCK */
#define NXGE_ROCK_COMPATIBLE "SUNW,rock-pciex108e,abcd"
#define NXGE_EROM_LEN 1048576
#include <npi_espc.h>
#include <npi_vir.h>
extern int fm_check_acc_handle(ddi_acc_handle_t);
extern int fm_check_dma_handle(ddi_dma_handle_t);
/* nxge_classify.c */
/* nxge_fflp.c */
uint32_t);
uint32_t *);
uint32_t);
uint32_t);
/* nxge_kstats.c */
void nxge_init_statsp(p_nxge_t);
void nxge_setup_kstats(p_nxge_t);
void nxge_setup_rdc_kstats(p_nxge_t, int);
void nxge_setup_tdc_kstats(p_nxge_t, int);
void nxge_destroy_kstats(p_nxge_t);
int nxge_port_kstat_update(kstat_t *, int);
void nxge_save_cntrs(p_nxge_t);
/* nxge_hw.c */
void
void nxge_intr_enable(p_nxge_t);
void nxge_intr_disable(p_nxge_t);
void nxge_hw_id_init(p_nxge_t);
void nxge_hw_init_niu_common(p_nxge_t);
void nxge_intr_hw_enable(p_nxge_t);
void nxge_intr_hw_disable(p_nxge_t);
void nxge_hw_stop(p_nxge_t);
void nxge_check_hw_state(p_nxge_t);
uint64_t);
void nxge_hw_set_mac_modes(p_nxge_t);
/* nxge_send.c. */
/* nxge_rxdma.c */
uint16_t);
/* nxge_ndd.c */
void nxge_setup_param(p_nxge_t);
void nxge_init_param(p_nxge_t);
void nxge_destroy_param(p_nxge_t);
long nxge_strtol(char *, char **, int);
void nxge_nd_free(caddr_t *);
/* nxge_virtual.c */
void nxge_common_lock_get(p_nxge_t);
void nxge_common_lock_free(p_nxge_t);
void nxge_get_xcvr_properties(p_nxge_t);
void nxge_init_vlan_config(p_nxge_t);
void nxge_init_mac_config(p_nxge_t);
void nxge_init_logical_devs(p_nxge_t);
int nxge_init_ldg_intrs(p_nxge_t);
uint32_t);
void nxge_init_fzc_ldg_num(p_nxge_t);
/* MAC functions */
void nxge_link_is_down(p_nxge_t);
void nxge_link_is_up(p_nxge_t);
/* espc (sprom) prototypes */
void nxge_vpd_info_get(p_nxge_t);
int nxge_get_nports(p_nxge_t);
#pragma weak hv_niu_rx_logical_page_conf
#pragma weak hv_niu_rx_logical_page_info
#pragma weak hv_niu_tx_logical_page_conf
#pragma weak hv_niu_tx_logical_page_info
#pragma weak hv_niu_vr_assign
#pragma weak hv_niu_vr_unassign
#pragma weak hv_niu_vr_getinfo
#pragma weak hv_niu_vr_get_rxmap
#pragma weak hv_niu_vr_get_txmap
#pragma weak hv_niu_rx_dma_assign
#pragma weak hv_niu_rx_dma_unassign
#pragma weak hv_niu_tx_dma_assign
#pragma weak hv_niu_tx_dma_unassign
#pragma weak hv_niu_vrrx_logical_page_conf
#pragma weak hv_niu_vrrx_logical_page_info
#pragma weak hv_niu_vrtx_logical_page_conf
#pragma weak hv_niu_vrtx_logical_page_info
//
// NIU-specific interrupt API
//
#pragma weak hv_niu_vrrx_getinfo
#pragma weak hv_niu_vrtx_getinfo
#pragma weak hv_niu_vrrx_to_logical_dev
#pragma weak hv_niu_vrtx_to_logical_dev
#ifdef NXGE_DEBUG
char *nxge_dump_packet(char *, int);
#endif
#endif /* !_ASM */
#ifdef __cplusplus
}
#endif
#endif /* _SYS_NXGE_NXGE_IMPL_H */