nxge_fflp_hw.h revision 4df55fde49134f9735f84011f23a767c75e393c7
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_NXGE_NXGE_FFLP_HW_H
#define _SYS_NXGE_NXGE_FFLP_HW_H
#ifdef __cplusplus
extern "C" {
#endif
#include <nxge_defs.h>
/* FZC_FFLP Offsets */
/* defines for FFLP_ENET_VLAN_TBL */
#define ENET_VLAN_TBL_VLANRDCTBLN0_MASK 0x0000000000000003ULL
#define ENET_VLAN_TBL_VLANRDCTBLN0_SHIFT 0
#define ENET_VLAN_TBL_VPR0_MASK 0x00000000000000008ULL
#define ENET_VLAN_TBL_VPR0_SHIFT 3
#define ENET_VLAN_TBL_VLANRDCTBLN1_MASK 0x0000000000000030ULL
#define ENET_VLAN_TBL_VLANRDCTBLN1_SHIFT 4
#define ENET_VLAN_TBL_VPR1_MASK 0x00000000000000080ULL
#define ENET_VLAN_TBL_VPR1_SHIFT 7
#define ENET_VLAN_TBL_VLANRDCTBLN2_MASK 0x0000000000000300ULL
#define ENET_VLAN_TBL_VLANRDCTBLN2_SHIFT 8
#define ENET_VLAN_TBL_VPR2_MASK 0x00000000000000800ULL
#define ENET_VLAN_TBL_VPR2_SHIFT 11
#define ENET_VLAN_TBL_VLANRDCTBLN3_MASK 0x0000000000003000ULL
#define ENET_VLAN_TBL_VLANRDCTBLN3_SHIFT 12
#define ENET_VLAN_TBL_VPR3_MASK 0x0000000000008000ULL
#define ENET_VLAN_TBL_VPR3_SHIFT 15
#define ENET_VLAN_TBL_PARITY0_MASK 0x0000000000010000ULL
#define ENET_VLAN_TBL_PARITY0_SHIFT 16
#define ENET_VLAN_TBL_PARITY1_MASK 0x0000000000020000ULL
#define ENET_VLAN_TBL_PARITY1_SHIFT 17
typedef union _fflp_enet_vlan_tbl_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} ldw;
#ifndef _BIG_ENDIAN
#endif
} bits;
typedef union _tcam_class_prg_ether_t {
#define TCAM_ENET_USR_CLASS_ENABLE 0x1
#define TCAM_ENET_USR_CLASS_DISABLE 0x0
struct {
#ifdef _BIG_ENDIAN
#endif
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} ldw;
#ifndef _BIG_ENDIAN
#endif
} bits;
typedef union _tcam_class_prg_ip_t {
#define TCAM_IP_USR_CLASS_ENABLE 0x1
#define TCAM_IP_USR_CLASS_DISABLE 0x0
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} ldw;
#ifndef _BIG_ENDIAN
#endif
} bits;
/*
* New fields added to the L3 programmable class register for RF-NIU
* and Neptune-L.
*/
#define L3_UCLS_TOS_SH 0
#define L3_UCLS_TOS_MSK 0xff
#define L3_UCLS_TOSM_SH 8
#define L3_UCLS_TOSM_MSK 0xff
#define L3_UCLS_PID_SH 16
#define L3_UCLS_PID_MSK 0xff
#define L3_UCLS_VALID_SH 25
#define L3_UCLS_VALID_MSK 0x01
#define L3_UCLS_L4B23_SEL_SH 26
#define L3_UCLS_L4B23_SEL_MSK 0x01
#define L3_UCLS_L4B23_VAL_SH 27
#define L3_UCLS_L4B23_VAL_MSK 0xffff
#define L3_UCLS_L4B0_MASK_SH 43
#define L3_UCLS_L4B0_MASK_MSK 0xff
#define L3_UCLS_L4B0_VAL_SH 51
#define L3_UCLS_L4B0_VAL_MSK 0xff
#define L3_UCLS_L4_MODE_SH 59
#define L3_UCLS_L4_MODE_MSK 0x01
/* define the classes which use the above structure */
typedef enum fflp_tcam_class {
TCAM_CLASS_INVALID = 0,
TCAM_CLASS_DUMMY = 1,
TCAM_CLASS_ETYPE_1 = 2,
TCAM_CLASS_IPV6_FRAG = 0x1F
} tcam_class_t;
#define TCAM_CLASS_MAX TCAM_CLASS_IPV6_FRAG
/*
* Specify how to build TCAM key for L3
* IP Classes. Both User configured and
* hardwired IP services are included.
* These are the supported 12 classes.
*/
typedef union _tcam_class_key_ip_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} ldw;
#ifndef _BIG_ENDIAN
#endif
} bits;
/* bit defines for FFLP_TCAM_CTL register */
#define TCAM_CTL_TCAM_WR 0x0ULL
#define TCAM_CTL_TCAM_RD 0x040000ULL
#define TCAM_CTL_TCAM_CMP 0x080000ULL
#define TCAM_CTL_RAM_WR 0x100000ULL
#define TCAM_CTL_RAM_RD 0x140000ULL
#define TCAM_CTL_RWC_STAT 0x0020000ULL
#define TCAM_CTL_RWC_MATCH 0x0010000ULL
typedef union _tcam_ctl_t {
#define TCAM_CTL_RWC_TCAM_WR 0x0
#define TCAM_CTL_RWC_TCAM_RD 0x1
#define TCAM_CTL_RWC_TCAM_CMP 0x2
#define TCAM_CTL_RWC_RAM_WR 0x4
#define TCAM_CTL_RWC_RAM_RD 0x5
#define TCAM_CTL_RWC_RWC_STAT 0x1
#define TCAM_CTL_RWC_RWC_MATCH 0x1
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} ldw;
#ifndef _BIG_ENDIAN
#endif
} bits;
} tcam_ctl_t, *p_tcam_ctl_t;
/* Bit defines for TCAM ASC RAM */
typedef union _tcam_res_t {
struct {
#if defined(_BIG_ENDIAN)
struct {
} hdw;
#endif
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} ldw;
#ifndef _BIG_ENDIAN
struct {
} hdw;
#endif
} bits;
} tcam_res_t, *p_tcam_res_t;
#define TCAM_ASC_DATA_AGE 0x0000000000000001ULL
#define TCAM_ASC_DATA_AGE_SHIFT 0x0
#define TCAM_ASC_DATA_ZFVLD 0x0000000000000002ULL
#define TCAM_ASC_DATA_ZFVLD_SHIFT 1
#define TCAM_ASC_DATA_OFFSET_MASK 0x000000000000007CULL
#define TCAM_ASC_DATA_OFFSET_SHIFT 2
#define TCAM_ASC_DATA_RDCTBL_MASK 0x0000000000000038ULL
#define TCAM_ASC_DATA_RDCTBL_SHIFT 7
#define TCAM_ASC_DATA_TRES_MASK 0x0000000000000C00ULL
#define TRES_CONT_USE_L2RDC 0x00
#define TRES_TERM_USE_OFFSET 0x01
#define TRES_CONT_OVRD_L2RDC 0x02
#define TRES_TERM_OVRD_L2RDC 0x03
#define TCAM_ASC_DATA_TRES_SHIFT 10
#define TCAM_TRES_CONT_USE_L2RDC \
(0x0000000000000000ULL << TCAM_ASC_DATA_TRES_SHIFT)
#define TCAM_TRES_TERM_USE_OFFSET \
(0x0000000000000001ULL << TCAM_ASC_DATA_TRES_SHIFT)
#define TCAM_TRES_CONT_OVRD_L2RDC \
(0x0000000000000002ULL << TCAM_ASC_DATA_TRES_SHIFT)
#define TCAM_TRES_TERM_OVRD_L2RDC \
(0x0000000000000003ULL << TCAM_ASC_DATA_TRES_SHIFT)
#define TCAM_ASC_DATA_DISC_MASK 0x0000000000001000ULL
#define TCAM_ASC_DATA_DISC_SHIFT 12
#define TCAM_ASC_DATA_V4_ECC_OK_MASK 0x0000000000002000ULL
#define TCAM_ASC_DATA_V4_ECC_OK_SHIFT 13
#define TCAM_ASC_DATA_V4_ECC_OK \
(0x0000000000000001ULL << TCAM_ASC_DATA_V4_ECC_OK_MASK_SHIFT)
#define TCAM_ASC_DATA_ZFID_MASK 0x0000000003FF3000ULL
#define TCAM_ASC_DATA_ZFID_SHIFT 14
#define TCAM_ASC_DATA_ZFID(value) \
#define TCAM_ASC_DATA_SYNDR_MASK 0x000003FFF3000000ULL
#define TCAM_ASC_DATA_SYNDR_SHIFT 26
#define TCAM_ASC_DATA_SYNDR(value) \
/* error registers */
typedef union _vlan_par_err_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} ldw;
#ifndef _BIG_ENDIAN
#endif
} bits;
typedef union _tcam_err_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} ldw;
#ifndef _BIG_ENDIAN
#endif
} bits;
} tcam_err_t, *p_tcam_err_t;
#define TCAM_ERR_SYNDROME_MASK 0x000000000000FFFFULL
#define TCAM_ERR_MULT_SHIFT 29
#define TCAM_ERR_MULT 0x0000000020000000ULL
#define TCAM_ERR_P_ECC 0x0000000040000000ULL
#define TCAM_ERR_ERR 0x0000000080000000ULL
typedef union _hash_lookup_err_log1_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} ldw;
#ifndef _BIG_ENDIAN
#endif
} bits;
typedef union _hash_lookup_err_log2_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} ldw;
#ifndef _BIG_ENDIAN
#endif
} bits;
typedef union _fcram_err_tst0_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} ldw;
#ifndef _BIG_ENDIAN
#endif
} bits;
typedef union _fcram_err_tst_t {
struct {
#if defined(_BIG_ENDIAN)
struct {
} hdw;
#endif
struct {
} ldw;
#ifndef _BIG_ENDIAN
struct {
} hdw;
#endif
} bits;
typedef union _fflp_err_mask_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} ldw;
#ifndef _BIG_ENDIAN
#endif
} bits;
#define FFLP_ERR_VLAN_MASK 0x00000001ULL
#define FFLP_ERR_VLAN 0x00000001ULL
#define FFLP_ERR_VLAN_SHIFT 0x0
#define FFLP_ERR_TCAM_MASK 0x00000002ULL
#define FFLP_ERR_TCAM 0x00000001ULL
#define FFLP_ERR_TCAM_SHIFT 0x1
#define FFLP_ERR_HASH_TBL_LKUP_MASK 0x00000004ULL
#define FFLP_ERR_HASH_TBL_LKUP 0x00000001ULL
#define FFLP_ERR_HASH_TBL_LKUP_SHIFT 0x2
#define FFLP_ERR_HASH_TBL_DAT_MASK 0x00000007F8ULL
#define FFLP_ERR_HASH_TBL_DAT 0x0000000FFULL
#define FFLP_ERR_HASH_TBL_DAT_SHIFT 0x3
typedef union _fflp_cfg_1_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} ldw;
#ifndef _BIG_ENDIAN
#endif
} bits;
typedef enum fflp_fcram_output_drive {
FCRAM_OUTDR_NORMAL = 0x0,
FCRAM_OUTDR_STRONG = 0x5,
FCRAM_OUTDR_WEAK = 0xa
typedef enum fflp_fcram_qs {
FCRAM_QS_MODE_QS = 0x0,
FCRAM_QS_MODE_FREE = 0x1
#define FCRAM_PIO_HIGH_PRI 0xf
#define FCRAM_PIO_MED_PRI 0xa
#define FCRAM_LOOKUP_HIGH_PRI 0x0
#define FCRAM_LOOKUP_HIGH_PRI 0x0
#define TCAM_PIO_HIGH_PRI 0xf
#define TCAM_PIO_MED_PRI 0xa
#define TCAM_LOOKUP_HIGH_PRI 0x0
#define TCAM_LOOKUP_HIGH_PRI 0x0
#define TCAM_IO_DEFAULT_PRI TCAM_PIO_MED_PRI
#define TCAM_DEFAULT_LATENCY 0x4
typedef union _fflp_dbg_train_vct_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} ldw;
#ifndef _BIG_ENDIAN
#endif
} bits;
typedef union _tcp_cflag_mask_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} ldw;
#ifndef _BIG_ENDIAN
#endif
} bits;
typedef union _fcram_ref_tmr_t {
#define FCRAM_REFRESH_DEFAULT_MAX_TIME 0x200
#define FCRAM_REFRESH_DEFAULT_MIN_TIME 0x200
#define FCRAM_REFRESH_DEFAULT_SYS_TIME 0x200
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} ldw;
#ifndef _BIG_ENDIAN
#endif
} bits;
typedef union _fcram_fio_addr_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} ldw;
#ifndef _BIG_ENDIAN
#endif
} bits;
typedef union _fcram_fio_dat_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} ldw;
#ifndef _BIG_ENDIAN
#endif
} bits;
typedef union _fcram_phy_rd_lat_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} ldw;
#ifndef _BIG_ENDIAN
#endif
} bits;
/*
* Specify how to build a flow key for IP
* classes, both programmable and hardwired
*/
/*
* New FLOW KEY register added for IPV6 Fragments for RF-NIU
* and Neptune-L.
*/
#define FL_KEY_USR_L4XOR_MSK 0x03ff
typedef union _flow_class_key_ip_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#ifdef _BIT_FIELDS_HTOL
/* These bits added for L3 programmable classes in RF-NIU and Neptune-L */
/* This bit added for SNORT support in RF-NIU and Neptune-L */
#else
#endif
} ldw;
#ifndef _BIG_ENDIAN
#endif
} bits;
typedef union _hash_h1poly_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
} ldw;
#ifndef _BIG_ENDIAN
#endif
} bits;
typedef union _hash_h2poly_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} ldw;
#ifndef _BIG_ENDIAN
#endif
} bits;
typedef union _flow_prt_sel_t {
#define FFLP_FCRAM_MAX_PARTITION 8
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} ldw;
#ifndef _BIG_ENDIAN
#endif
} bits;
/* FFLP Offsets */
typedef union _hash_tbl_addr_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} ldw;
#ifndef _BIG_ENDIAN
#endif
} bits;
typedef union _hash_tbl_data_t {
struct {
#ifdef _BIG_ENDIAN
#else
#endif
} bits;
typedef union _hash_tbl_data_log_t {
struct {
#if defined(_BIG_ENDIAN)
#endif
struct {
#ifdef _BIT_FIELDS_HTOL
#else
#endif
} ldw;
#ifndef _BIG_ENDIAN
#endif
} bits;
typedef struct tcam_ipv4 {
#if defined(_BIG_ENDIAN)
#else
#endif
} tcam_ipv4_t;
typedef struct tcam_reg {
#if defined(_BIG_ENDIAN)
#else
#endif
} tcam_reg_t;
typedef struct tcam_ether {
#if defined(_BIG_ENDIAN)
#else
#endif
} tcam_ether_t;
typedef struct tcam_ipv6 {
#if defined(_BIG_ENDIAN)
#else
#endif
} tcam_ipv6_t;
typedef struct tcam_entry {
union _tcam_entry {
} tcam_entry_t;
/*
* flow template structure
* The flow header is passed through the hash function
* which generates the H1 (and the H2 ) hash value.
* Hash computation is started at the 22 zeros.
*
* Since this structure uses the ip address fields,
* before this header file.
* Need to move these includes to impl files ...
*/
typedef union flow_template {
struct {
#if defined(_BIG_ENDIAN)
union {
struct {
} ip6_addr;
struct {
} ip4_addr;
} ipaddr;
union {
struct {
}l2_bits;
}l2;
#else
union {
struct {
} ip6_addr;
struct {
} ip4_addr;
} ipaddr;
union {
struct {
}l2_bits;
}l2;
#endif
} bits;
typedef struct _flow_key_cfg_t {
/* The following 3 bit fields added for RF-NIU and Neptune-L */
typedef struct _tcam_key_cfg_t {
/*
* FCRAM Entry Formats
*
* ip6 and ip4 entries, the first 64 bits layouts are identical
* optimistic entry has only 64 bit layout
* The first three bits, fmt, ext and valid are the same
* accoross all the entries
*/
typedef union hash_optim {
struct _bits {
#if defined(_BIG_ENDIAN)
#else
#endif
} bits;
} hash_optim_t;
typedef union _hash_hdr {
struct _exact_hdr {
#if defined(_BIG_ENDIAN)
#else
#endif
} exact_hdr;
} hash_hdr_t;
typedef union _hash_ports {
struct _ports_bits {
#if defined(_BIG_ENDIAN)
#else
#endif
} ports_bits;
} hash_ports_t;
typedef union _hash_match_action {
struct _action_bits {
#if defined(_BIG_ENDIAN)
#else
#endif
} action_bits;
typedef struct _ipaddr6 {
} ip6_addr_t;
typedef struct _ipaddr4 {
#if defined(_BIG_ENDIAN)
#else
#endif
} ip4_addr_t;
/* ipv4 has 32 byte layout */
typedef struct hash_ipv4 {
} hash_ipv4_t;
/* ipv4 has 56 byte layout */
typedef struct hash_ipv6 {
} hash_ipv6_t;
typedef union fcram_entry {
#define HASH_ENTRY_EXACT(fc) \
#define HASH_ENTRY_OPTIM(fc) \
#define HASH_ENTRY_EXACT_IP6(fc) \
#define HASH_ENTRY_EXACT_IP4(fc) \
#define HASH_ENTRY_TYPE(fc) \
typedef enum fcram_entry_format {
FCRAM_ENTRY_OPTIM = 0x0,
FCRAM_ENTRY_EX_IP4 = 0x2,
FCRAM_ENTRY_EX_IP6 = 0x3,
FCRAM_ENTRY_UNKOWN = 0x1
/* error xxx formats */
typedef struct _hash_lookup_err_log {
typedef struct _hash_pio_err_log {
typedef struct _tcam_err_log {
typedef struct _vlan_tbl_err_log {
#define NEPTUNE_TCAM_SIZE 0x100
#define NIU_TCAM_SIZE 0x80
#define FCRAM_SIZE 0x100000
#ifdef __cplusplus
}
#endif
#endif /* _SYS_NXGE_NXGE_FFLP_HW_H */