lom_ebuscodes.h revision 7c478bd95313f5f23a4c958a745db2134aa03244
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 1999-2002 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_LOM_EBUSCODES_H
#define _SYS_LOM_EBUSCODES_H
#pragma ident "%Z%%M% %I% %E% SMI"
/*
* This file enumerates the virtual registers exported by the microcontroller.
* It cannot be changed without also revising the firwmare.
*/
#ifdef __cplusplus
extern "C" {
#endif
/* boot script */
/*
* Read only values
*/
/* RESERVED 0x0d */
/* RESERVED 0x0e */
/* RESERVED 0x0f */
/*
* We currently don't have a virtual register to indicate the end of the log.
* We cannot assume the log runs to the end of the EEPROM because the EEPROM
* is logically partitioned into a Log portion (first 8K) and then a FRUID
* portion (next 8K). For the moment we therefore need to use a hardcoded
* value to represent the end of the event log.
*/
#define EBUS_LOG_END 0x2000
/* RESERVED 0x16 */
/* RESERVED 0x17 */
#define EBUS_IDX_TEMP2 0x19
#define EBUS_IDX_TEMP3 0x1A
#define EBUS_IDX_TEMP4 0x1B
#define EBUS_IDX_TEMP5 0x1C
#define EBUS_IDX_TEMP6 0x1D
#define EBUS_IDX_TEMP7 0x1E
#define EBUS_IDX_TEMP8 0x1F
#define EBUS_IDX_ALARMNEW 0x20
#define EBUS_IDX_CBREAK_STATUS 0x23
#define EBUS_IDX_OTEMP_STATUS 0x24
#define EBUS_IDX_LED1_STATUS 0x25
#define EBUS_IDX_LED2_STATUS 0x26
#define EBUS_IDX_LED3_STATUS 0x27
#define EBUS_IDX_LED4_STATUS 0x28
#define EBUS_IDX_LED5_STATUS 0x29
#define EBUS_IDX_LED6_STATUS 0x2a
#define EBUS_IDX_LED7_STATUS 0x2b
#define EBUS_IDX_LED8_STATUS 0x2c
/* RESERVED 0x2d */
#define EBUS_IDX_CPU_IDENT 0x2e
#define EBUS_IDX_EVENT_DETAIL 0x2f
/*
*/
#define EBUS_IDX_SER_BAUD 0x33
#define EBUS_IDX_SER_CHARMODE 0x34
#define EBUS_IDX_SER_FLOWCTL 0x35
#define EBUS_IDX_SER_MODEMTYPE 0x36
#define EBUS_IDX_EEPROM_PAGESEL 0x37
#define EBUS_IDX_HNAME_LENGTH 0x38
#define EBUS_IDX_HNAME_CHAR 0x39
#define EBUS_IDX_TIME0 0x3b
#define EBUS_IDX_TIME1 0x3c
#define EBUS_IDX_TIME2 0x3d
#define EBUS_IDX_TIME3 0x3e
#define EBUS_IDX_SELFTEST0 0x41
#define EBUS_IDX_SELFTEST1 0x42
#define EBUS_IDX_SELFTEST2 0x43
#define EBUS_IDX_SELFTEST3 0x44
#define EBUS_IDX_SELFTEST4 0x45
#define EBUS_IDX_SELFTEST5 0x46
#define EBUS_IDX_SELFTEST6 0x47
#define EBUS_IDX_SELFTEST7 0x48
#define EBUS_IDX_ESCAPE_LEN 0x49
#define EBUS_IDX_SER_TIMEOUT 0x4a
#define EBUS_IDX_EVENT_FILTER 0x4b
#define EBUS_IDX_POWERON_DELAY 0x4c
/* RESERVED 0x4f */
#define EBUS_IDX_MODEL_ID2 0x51
#define EBUS_IDX_MODEL_ID3 0x52
#define EBUS_IDX_MODEL_ID4 0x53
#define EBUS_IDX_MODEL_ID5 0x54
#define EBUS_IDX_MODEL_ID6 0x55
#define EBUS_IDX_MODEL_ID7 0x56
#define EBUS_IDX_MODEL_ID8 0x57
#define EBUS_IDX_MODEL_ID9 0x58
#define EBUS_IDX_MODEL_ID10 0x59
#define EBUS_IDX_MODEL_ID11 0x5a
#define EBUS_IDX_MODEL_ID12 0x5b
/* RESERVED 0x6c */
/* RESERVED 0x6d */
/* RESERVED 0x6e */
/* RESERVED 0x6f */
/* RESERVED 0x70 */
/* RESERVED 0x71 */
/* RESERVED 0x72 */
/* RESERVED 0x73 */
/* RESERVED 0x74 */
/* RESERVED 0x75 */
/* RESERVED 0x76 */
/* RESERVED 0x77 */
/* RESERVED 0x78 */
/* RESERVED 0x79 */
/* RESERVED 0x7a */
/*
* Capability bits:
*
* Register starting from 0x7e and downward are used to describe various
* capabilities that the LOM firmware has. A capability is present if the
* corresponding bit returns '1'.
*/
#define EBUS_FIRST_READONLY EBUS_IDX_FW_REV
/*
* Register for special address spaces
*/
#define EBUS_IDX1_CONS_BUF_START 0x00
#define EBUS_IDX1_CONS_BUF_END 0xff
#define EBUS_IDX2_SUPPLY_ENABLE_MASK1 0x01
#define EBUS_IDX2_SUPPLY_ENABLE_MASK2 0x02
#define EBUS_IDX2_SUPPLY_FATAL_MASK1 0x03
#define EBUS_IDX2_SUPPLY_FATAL_MASK2 0x04
#define EBUS_IDX2_SUPPLY_FINE_TOL 0x05
#define EBUS_IDX2_SUPPLY_GROSS_TOL 0x06
#define EBUS_IDX2_SUPPLY_READING1 0x10
#define EBUS_IDX2_SUPPLY_READING2 0x11
#define EBUS_IDX2_SUPPLY_READING3 0x12
#define EBUS_IDX2_SUPPLY_READING4 0x13
#define EBUS_IDX2_SUPPLY_READING5 0x14
#define EBUS_IDX2_SUPPLY_READING6 0x15
#define EBUS_IDX2_SUPPLY_READING7 0x16
#define EBUS_IDX2_SUPPLY_READING8 0x17
#define EBUS_IDX2_SUPPLY_READING9 0x18
#define EBUS_IDX2_SUPPLY_READING10 0x19
#define EBUS_IDX2_SUPPLY_READING11 0x1a
#define EBUS_IDX2_SUPPLY_READING12 0x1b
#define EBUS_IDX2_SUPPLY_READING13 0x1c
#define EBUS_IDX2_SUPPLY_READING14 0x1d
#define EBUS_IDX2_SUPPLY_READING15 0x1e
#define EBUS_IDX2_SUPPLY_READING16 0x1f
#define EBUS_IDX2_SUPPLY_CAL1 0x20
#define EBUS_IDX2_SUPPLY_CAL2 0x21
#define EBUS_IDX2_SUPPLY_CAL3 0x22
#define EBUS_IDX2_SUPPLY_CAL4 0x23
#define EBUS_IDX2_SUPPLY_CAL5 0x24
#define EBUS_IDX2_SUPPLY_CAL6 0x25
#define EBUS_IDX2_SUPPLY_CAL7 0x26
#define EBUS_IDX2_SUPPLY_CAL8 0x27
#define EBUS_IDX2_SUPPLY_CAL9 0x28
#define EBUS_IDX2_SUPPLY_CAL10 0x29
#define EBUS_IDX2_SUPPLY_CAL11 0x2a
#define EBUS_IDX2_SUPPLY_CAL12 0x2b
#define EBUS_IDX2_SUPPLY_CAL13 0x2c
#define EBUS_IDX2_SUPPLY_CAL14 0x2d
#define EBUS_IDX2_SUPPLY_CAL15 0x2e
#define EBUS_IDX2_SUPPLY_CAL16 0x2f
#define EBUS_IDX2_SUPPLY_NAME_START 0x40
#define EBUS_IDX2_SUPPLY_NAME_END 0xff
#define EBUS_IDX3_BREAKER_ENABLE_MASK 0x01
#define EBUS_IDX3_BREAKER_NAME_START 0x40
#define EBUS_IDX3_BREAKER_NAME_END 0xff
#define EBUS_IDX4_TEMP_ENABLE_MASK 0x01
#define EBUS_IDX4_OTEMP_ENABLE_MASK 0x02
#define EBUS_IDX4_TEMP_FATAL_MASK 0x03
#define EBUS_IDX4_OTEMP_FATAL_MASK 0x04
#define EBUS_IDX4_TEMP_HYSTERESIS 0x05
#define EBUS_IDX4_TEMP_FAN_LINK_MASK 0x06
#define EBUS_IDX4_TEMP_WARN2 0x11
#define EBUS_IDX4_TEMP_WARN3 0x12
#define EBUS_IDX4_TEMP_WARN4 0x13
#define EBUS_IDX4_TEMP_WARN5 0x14
#define EBUS_IDX4_TEMP_WARN6 0x15
#define EBUS_IDX4_TEMP_WARN7 0x16
#define EBUS_IDX4_TEMP_WARN8 0x17
#define EBUS_IDX4_TEMP_SDOWN2 0x19
#define EBUS_IDX4_TEMP_SDOWN3 0x1a
#define EBUS_IDX4_TEMP_SDOWN4 0x1b
#define EBUS_IDX4_TEMP_SDOWN5 0x1c
#define EBUS_IDX4_TEMP_SDOWN6 0x1d
#define EBUS_IDX4_TEMP_SDOWN7 0x1e
#define EBUS_IDX4_TEMP_SDOWN8 0x1f
#define EBUS_IDX4_TEMP_CORRECT2 0x21
#define EBUS_IDX4_TEMP_CORRECT3 0x22
#define EBUS_IDX4_TEMP_CORRECT4 0x23
#define EBUS_IDX4_TEMP_CORRECT5 0x24
#define EBUS_IDX4_TEMP_CORRECT6 0x25
#define EBUS_IDX4_TEMP_CORRECT7 0x26
#define EBUS_IDX4_TEMP_CORRECT8 0x27
#define EBUS_IDX4_TEMP_NAME_START 0x40
#define EBUS_IDX4_TEMP_NAME_END 0xff
#define EBUS_IDX5_FAN_ENABLE_CONFIG 0x01
#define EBUS_IDX5_FAN_NAME_START 0x40
#define EBUS_IDX5_FAN_NAME_END 0xff
#define EBUS_IDX10_LED_NAME_START 0x40
#define EBUS_IDX10_LED_NAME_END 0xff
/*
* This arrangement for CPU signatures allows only one CPU to generate a
* CPU Signature at a time. Since the signature won't fit into one byte
* it is recommended to datafill the MSB, LSB, STATE, SUBSTATE first, and
* then write the ID. A one byte ID limits the number of CPUs to 255.
* CPU 255 is handled specially; it denotes that the signature applies to
* "all", or rather "any" CPU ID.
*/
#define EBUS_ANY_CPU_ID 255
/*
* OBP-defined reset reasons. Solaris never generates these.
*/
#define EBUS_IDX11_HOST_RESET_REASON 0x07
/*
* I2C Transfers can be done using the BSC as a proxy. We transfer data at
* the conceptual level of struct i2c_transfer defined by the i2c services
* framework in Solaris.
*/
/*
* TRANSFER_TYPE mirrors the i2c_transfer.i2c_flags used in Solaris i2c
* services framework.
*/
/*
* RESULT mirrors the i2c_transfer.i2c_result used the Solaris i2c services
* framework.
*/
#define EBUS_I2C_SUCCESS 0x00
#define EBUS_I2C_FAILURE 0xFF
#define EBUS_I2C_INCOMPLETE 0xFE
#define EBUS_IDX12_MAX_TRANSFER_SZ 0x01
#define EBUS_IDX12_BUS_ADDRESS 0x02
#define EBUS_IDX12_CLIENT_ADDRESS 0x03
#define EBUS_IDX12_WR_RD_BOUNDARY 0x04
#define EBUS_IDX12_TRANSFER_TYPE 0x05
#define EBUS_IDX12_RESIDUAL_DATA 0x06
#define EBUS_IDX12_DATA_INOUT 0x07
#define EBUS_IDX12_RESULT 0x08
/* so multi i2c transactions */
/* can complete atomically */
#define EBUS_PROGRAM_PCSR 0x01
#define EBUS_PROGRAM_PCR_RSVD 0x00
#define EBUS_PROGRAM_PCR_READ 0x02
#define EBUS_PROGRAM_PCR_PRGMODE_ON 0x03
#define EBUS_PROGRAM_PCR_ERASE 0x04
#define EBUS_PROGRAM_PCR_PROGRAM 0x05
#define EBUS_PROGRAM_PCR_PRSVD 0x06
#define EBUS_PROGRAM_PCR_PRGMODE_OFF 0x07
#define EBUS_PROGRAM_PCR_PROGOFF_JUMPTOADDR 0x08
#define EBUS_PROGRAM_PSR_SUCCESS 0x00
#define EBUS_PROGRAM_PSR_PROGRAM_FAIL 0x01
#define EBUS_PROGRAM_PSR_ERASE_FAIL 0x02
#define EBUS_PROGRAM_PSR_INVALID_AREA 0x03
#define EBUS_PROGRAM_PSR_INCORRECT_CSUM 0x04
#define EBUS_PROGRAM_PSR_INCORRECT_COUNT 0x05
#define EBUS_PROGRAM_PSR_INVALID_OPERATION 0x06
#define EBUS_PROGRAM_PSR_STATUS_MASK 0x7f
#define EBUS_PROGRAM_PSR_PROG_MODE 0x80
#define EBUS_PROGRAM_DATA 0x02
#define EBUS_PROGRAM_PCSM1 0x04
#define EBUS_PROGRAM_PADR1 0x06
#define EBUS_PROGRAM_PADR2 0x07
#define EBUS_PROGRAM_PADR3 0x08
#define EBUS_PROGRAM_PSIZ1 0x0a
#define EBUS_PROGRAM_PSIZ2 0x0b
#define EBUS_PROGRAM_PSIZ3 0x0c
#define EBUS_PROGRAM_PAGE1 0x0e
#define EBUS_PROGRAM_PAGE2 0x0f
#define EBUS_PROGRAM_PAGE3 0x10
/*
* Command register and codes
*/
#define EBUS_CMD_CONLOG_ON 'F'
#define EBUS_CMD_CONLOG_OFF 'D'
#define EBUS_CMD_INTERRUPTS_ON 'i'
#define EBUS_CMD_INTERRUPTS_OFF 'I'
#define EBUS_CMD_PROG_START 'z'
/*
* space 11 - CPU signatures and OBP reset information.
*/
#define EBUS_CMD_SPACE_CPUSIG 0x0b
#define EBUS_CMD_SPACE13 0x0d
#define EBUS_CMD_SPACE14 0x0e
#define EBUS_CMD_SPACE15 0x0f
/*
* Number of unread events flag
*/
/*
* Prom boot mode parameters
*/
#define EBUS_BOOTMODE_FORCE_CONSOLE 0x01
#define EBUS_BOOTMODE_FORCE_NOBOOT 0x02
#define EBUS_BOOTMODE_RESET_DEFAULT 0x04
#define EBUS_BOOTMODE_FULLDIAG 0x08
#define EBUS_BOOTMODE_SKIPDIAG 0x10
/*
* Configuration register
*/
/*
* Configuration register 2
*/
#define EBUS_CONFIG2_NSUPPLY_DEC(n) ((n)&0xf)
#define EBUS_CONFIG2_NSUPPLY_ENC(n) ((n)&0xf)
/*
* Configuration register 3
*/
#define EBUS_CONFIG3_NBREAKERS_DEC(n) ((n)&0xf)
#define EBUS_CONFIG3_NBREAKERS_ENC(n) ((n)&0xf)
/*
* Miscellaneous host configuration register
*/
#define EBUS_CONFIG_MISC_PSUIPFAILEVENTS 0x80
#define EBUS_CONFIG_MISC_DELAYED_STARTUP 0x40
#define EBUS_CONFIG_MISC_RANDOM_DELAY 0x20
#define EBUS_CONFIG_MISC_DECLINE_STARTUP 0x10
#define EBUS_CONFIG_MISC_ALARM0_ENABLED 0x08
#define EBUS_CONFIG_MISC_PHONEHOME_ENABLED 0x04
#define EBUS_CONFIG_MISC_SECURITY_ENABLED 0x02
#define EBUS_CONFIG_MISC_AUTO_CONSOLE 0x01
/*
*/
/*
* General Channel Watchdog control
*/
/*
* Watchdog channel non-blocking byte
* Top nibble command, bottom nibble data
*/
#define EBUS_WDOG_NB_PAT 0x00
#define EBUS_WDOG_NB_CFG 0x10
/*
* PSU status
*/
/*
* State change flags
*/
/*
* Bit-0 is overloaded. It is used by the BSC to notify of a status change
* The detail field will then be one of EBUS_DETAIL_XXXX. Otherwise, it's used
* to indicate that an Alarm state has changed. The detail field would then
* be the alarm number.
*/
/*
* State Notify detail values
*/
/*
* Alarm config bytes for register $20
*/
#define ALARM_0 0x01
#define ALARM_0_ENABLE 0x02
/*
* Phone home configuration information
*/
#define PHONEHOME_CONFIG_REG 0x01
#define PHONEHOME_SCRIPT_START_REG 0x02
#define PHONEHOME_CONFIG_ON_UNXPOWEROFF 0x01
#define PHONEHOME_CONFIG_ON_WATCHDOGTRG 0x02
#define PHONEHOME_CONFIG_ON_DEMAND 0x04
/*
* CPU type ident codes. This determines the programming mode.
*/
#define CPU_IDENT_UNKNOWN 0x80
#define CPU_IDENT_H8_3434 0x81
#define CPU_IDENT_H8_3436 0x82
#define CPU_IDENT_H8_3437 0x83
#define CPU_IDENT_H8_3437SF 0x84
#define CPU_IDENT_H8S_2148 0x85
#define CPU_IDENT_H8S_2148A 0x86
#define CPU_IDENT_H8S_BSC 0x87
/*
* Capability codes
*/
/* Error codes as returned via the EBUS interface */
#define EBUS_ERROR_NONE 0 /* no error occured */
/* Magic values for specific registers. */
#define LOM_TEMP_MAX_VALUE 0x7c
#ifdef __cplusplus
}
#endif
#endif /* _SYS_LOM_EBUSCODES_H */