i8272A.h revision 7c478bd95313f5f23a4c958a745db2134aa03244
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License, Version 1.0 only
* (the "License"). You may not use this file except in compliance
* with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright (c) 1995 by Sun Microsystems, Inc.
* All rights reserved.
*/
#ifndef _SYS_I8272A_H
#define _SYS_I8272A_H
#pragma ident "%Z%%M% %I% %E% SMI"
#ifdef __cplusplus
extern "C" {
#endif
/*
* i/o port numbers
*/
#define FCR_DOR 0x002
#define FCR_MSR 0x004
#define FCR_DATA 0x005
#define FCR_DIR 0x007
/* SRA : values for Configuration Select Register for SMC FDC37C66xGT */
/* SRB : Configuration Data Register for SMC FDC37C66xGT */
/* DOR : Digital Output Register */
#define FD_DMTREN 0xF0
#define FD_D3MTR 0x80
#define FD_D2MTR 0x40
#define FD_DBMTR 0x20
#define FD_DAMTR 0x10
#define FD_RSETZ 0x04
#define FD_DRSEL 0x03
#define FD_DBSEL 0x01
#define FD_DASEL 0x00
#define ENAB_MCA_INT 0x00
/* MSR - Main Status Register */
#define FDC_RQM_RETRY 300
/* DIR : Digital Input Register */
/* DSR : Datarate Select Register on 82072 and 82077AA */
/* CCR : Configuration Control Register, aka Datarate Select Register */
/*
* Floppy controller command opcodes
*/
#define FO_RDTRK 0x02
#define FO_SPEC 0x03
#define FO_WRDAT 0x05
#define FO_RDDAT 0x06
#define FO_RECAL 0x07
#define FO_SINT 0x08
#define FO_WRDEL 0x09
#define FO_RDID 0x0A
#define FO_RDDEL 0x0C
#define FO_FRMT 0x0D
#define FO_SEEK 0x0F
/* option bits */
#define S0_XRDY 0xC0
#define S0_IVCMD 0x80
#define S0_ABTERM 0x40
#define S0_SEKEND 0x20
#define S0_ECHK 0x10
#define S0_NOTRDY 0x08
#define S1_CRCER 0x20
#define S1_OVRUN 0x10
#define S1_NODATA 0x04
#define S1_MADMK 0x01
#define S3_WPROT 0x40
#define S3_DRRDY 0x20
#define S3_TRK0 0x10
#define S3_2SIDE 0x08
#define S3_HEAD 0x04
#define S3_UNIT 0x03
/*
* controller chip values
*/
#define i8272A 0x8272
/* enhanced floppy controllers */
#define i82077 0x82077
#ifdef __cplusplus
}
#endif
#endif /* !_SYS_I8272A_H */