pciehpc_impl.h revision c333dd99c762d509c7eb6cce222221958e23b4c8
6185db853e024a486ff8837e6784dd290d866112dougm/*
6185db853e024a486ff8837e6784dd290d866112dougm * CDDL HEADER START
6185db853e024a486ff8837e6784dd290d866112dougm *
6185db853e024a486ff8837e6784dd290d866112dougm * The contents of this file are subject to the terms of the
6185db853e024a486ff8837e6784dd290d866112dougm * Common Development and Distribution License (the "License").
6185db853e024a486ff8837e6784dd290d866112dougm * You may not use this file except in compliance with the License.
6185db853e024a486ff8837e6784dd290d866112dougm *
6185db853e024a486ff8837e6784dd290d866112dougm * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
6185db853e024a486ff8837e6784dd290d866112dougm * or http://www.opensolaris.org/os/licensing.
6185db853e024a486ff8837e6784dd290d866112dougm * See the License for the specific language governing permissions
6185db853e024a486ff8837e6784dd290d866112dougm * and limitations under the License.
6185db853e024a486ff8837e6784dd290d866112dougm *
6185db853e024a486ff8837e6784dd290d866112dougm * When distributing Covered Code, include this CDDL HEADER in each
6185db853e024a486ff8837e6784dd290d866112dougm * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
6185db853e024a486ff8837e6784dd290d866112dougm * If applicable, add the following below this CDDL HEADER, with the
6185db853e024a486ff8837e6784dd290d866112dougm * fields enclosed by brackets "[]" replaced with your own identifying
6185db853e024a486ff8837e6784dd290d866112dougm * information: Portions Copyright [yyyy] [name of copyright owner]
6185db853e024a486ff8837e6784dd290d866112dougm *
6185db853e024a486ff8837e6784dd290d866112dougm * CDDL HEADER END
6185db853e024a486ff8837e6784dd290d866112dougm */
6185db853e024a486ff8837e6784dd290d866112dougm
6185db853e024a486ff8837e6784dd290d866112dougm/*
f345c0beb4c8f75cb54c2e070498e56febd468acdougm * Copyright 2006 Sun Microsystems, Inc. All rights reserved.
6185db853e024a486ff8837e6784dd290d866112dougm * Use is subject to license terms.
6185db853e024a486ff8837e6784dd290d866112dougm */
6185db853e024a486ff8837e6784dd290d866112dougm
6185db853e024a486ff8837e6784dd290d866112dougm#ifndef _SYS_HOTPLUG_PCI_PCIEHPC_IMPL_H
6185db853e024a486ff8837e6784dd290d866112dougm#define _SYS_HOTPLUG_PCI_PCIEHPC_IMPL_H
6185db853e024a486ff8837e6784dd290d866112dougm
6185db853e024a486ff8837e6784dd290d866112dougm#pragma ident "%Z%%M% %I% %E% SMI"
6185db853e024a486ff8837e6784dd290d866112dougm
6185db853e024a486ff8837e6784dd290d866112dougm#ifdef __cplusplus
6185db853e024a486ff8837e6784dd290d866112dougmextern "C" {
6185db853e024a486ff8837e6784dd290d866112dougm#endif
6185db853e024a486ff8837e6784dd290d866112dougm
6185db853e024a486ff8837e6784dd290d866112dougm#include <sys/disp.h>
6185db853e024a486ff8837e6784dd290d866112dougm#include <sys/stat.h>
6185db853e024a486ff8837e6784dd290d866112dougm#include <sys/condvar.h>
6185db853e024a486ff8837e6784dd290d866112dougm#include <sys/pcie.h>
6185db853e024a486ff8837e6784dd290d866112dougm#include <sys/hotplug/hpcsvc.h>
6185db853e024a486ff8837e6784dd290d866112dougm#include <sys/hotplug/pci/pciehpc.h>
6185db853e024a486ff8837e6784dd290d866112dougm
6185db853e024a486ff8837e6784dd290d866112dougm/*
6185db853e024a486ff8837e6784dd290d866112dougm * PCI Express Hot Plug slot softstate structure
6185db853e024a486ff8837e6784dd290d866112dougm *
6185db853e024a486ff8837e6784dd290d866112dougm */
6185db853e024a486ff8837e6784dd290d866112dougmtypedef struct pciehpc_slot
6185db853e024a486ff8837e6784dd290d866112dougm{
6185db853e024a486ff8837e6784dd290d866112dougm hpc_slot_info_t slot_info; /* HPS framework slot info */
6185db853e024a486ff8837e6784dd290d866112dougm hpc_slot_t slot_handle; /* HPS framework handle */
6185db853e024a486ff8837e6784dd290d866112dougm hpc_slot_ops_t slot_ops; /* HPS framework callbacks */
6185db853e024a486ff8837e6784dd290d866112dougm uint32_t fault_led_state; /* Fault LED state */
6185db853e024a486ff8837e6784dd290d866112dougm uint32_t power_led_state; /* Power LED state */
6185db853e024a486ff8837e6784dd290d866112dougm uint32_t attn_led_state; /* Attn LED state */
6185db853e024a486ff8837e6784dd290d866112dougm uint32_t active_led_state; /* Active LED state */
6185db853e024a486ff8837e6784dd290d866112dougm hpc_slot_state_t slot_state; /* Slot State */
6185db853e024a486ff8837e6784dd290d866112dougm uint32_t slotNum; /* slot number */
6185db853e024a486ff8837e6784dd290d866112dougm /* synchronization variable(s) for hot plug events */
6185db853e024a486ff8837e6784dd290d866112dougm kcondvar_t cmd_comp_cv; /* Command Completion intr. */
6185db853e024a486ff8837e6784dd290d866112dougm boolean_t command_pending;
6185db853e024a486ff8837e6784dd290d866112dougm kcondvar_t attn_btn_cv; /* ATTN button pressed intr */
6185db853e024a486ff8837e6784dd290d866112dougm boolean_t attn_btn_pending;
6185db853e024a486ff8837e6784dd290d866112dougm kthread_t *attn_btn_threadp; /* ATTN button event thread */
6185db853e024a486ff8837e6784dd290d866112dougm boolean_t attn_btn_thread_exit;
6185db853e024a486ff8837e6784dd290d866112dougm kcondvar_t dll_active_cv; /* DLL State Changed intr */
6185db853e024a486ff8837e6784dd290d866112dougm} pciehpc_slot_t;
6185db853e024a486ff8837e6784dd290d866112dougm
6185db853e024a486ff8837e6784dd290d866112dougmtypedef enum {
6185db853e024a486ff8837e6784dd290d866112dougm PCIEHPC_NATIVE_HP_MODE, PCIEHPC_ACPI_HP_MODE
6185db853e024a486ff8837e6784dd290d866112dougm} pciehpc_hp_mode_t;
6185db853e024a486ff8837e6784dd290d866112dougm
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmtypedef uint32_t pciehpc_soft_state_t;
6185db853e024a486ff8837e6784dd290d866112dougm
6185db853e024a486ff8837e6784dd290d866112dougm/* init_flags */
6185db853e024a486ff8837e6784dd290d866112dougm#define PCIEHPC_SOFT_STATE_UNINITIALIZED 0x01
6185db853e024a486ff8837e6784dd290d866112dougm#define PCIEHPC_SOFT_STATE_INITIALIZED 0x02
6185db853e024a486ff8837e6784dd290d866112dougm#define PCIEHPC_SOFT_STATE_INIT_HTABLE 0x04
6185db853e024a486ff8837e6784dd290d866112dougm#define PCIEHPC_SOFT_STATE_INIT_ALLOC 0x08
6185db853e024a486ff8837e6784dd290d866112dougm#define PCIEHPC_SOFT_STATE_INIT_HANDLER 0x10
6185db853e024a486ff8837e6784dd290d866112dougm#define PCIEHPC_SOFT_STATE_INIT_ENABLE 0x20
6185db853e024a486ff8837e6784dd290d866112dougm#define PCIEHPC_SOFT_STATE_INIT_BLOCK 0x40
6185db853e024a486ff8837e6784dd290d866112dougm#define PCIEHPC_SOFT_STATE_INIT_FM 0x80
6185db853e024a486ff8837e6784dd290d866112dougm#define PCIEHPC_SOFT_STATE_PCIE_DEV 0x10000
6185db853e024a486ff8837e6784dd290d866112dougm
6185db853e024a486ff8837e6784dd290d866112dougm/*
6185db853e024a486ff8837e6784dd290d866112dougm * PCI Express Hotplug controller soft state structure
6185db853e024a486ff8837e6784dd290d866112dougm */
6185db853e024a486ff8837e6784dd290d866112dougmtypedef struct pciehpc
6185db853e024a486ff8837e6784dd290d866112dougm{
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm dev_info_t *dip; /* DIP for the Nexus */
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm uint8_t bus; /* primary bus number */
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm uint8_t dev; /* device number */
6185db853e024a486ff8837e6784dd290d866112dougm uint8_t func; /* function number */
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm kmutex_t pciehpc_mutex; /* Mutex for this ctrl */
6185db853e024a486ff8837e6784dd290d866112dougm pciehpc_soft_state_t soft_state; /* soft state flags */
6185db853e024a486ff8837e6784dd290d866112dougm pciehpc_hp_mode_t hp_mode; /* HP mode (Native, ACPI) */
6185db853e024a486ff8837e6784dd290d866112dougm struct pciehpc *nextp; /* Linked list pointer */
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm
6185db853e024a486ff8837e6784dd290d866112dougm /* PCIE Hot Plug Controller register access */
6185db853e024a486ff8837e6784dd290d866112dougm ddi_acc_handle_t cfghdl; /* PCI cfg access handle */
6185db853e024a486ff8837e6784dd290d866112dougm caddr_t regs_base; /* config regs base */
6185db853e024a486ff8837e6784dd290d866112dougm uint_t pcie_caps_reg_offset; /* offset to PCIE Cap regs */
6185db853e024a486ff8837e6784dd290d866112dougm
6185db853e024a486ff8837e6784dd290d866112dougm /* slot information */
6185db853e024a486ff8837e6784dd290d866112dougm pciehpc_slot_t slot; /* Slot info */
6185db853e024a486ff8837e6784dd290d866112dougm boolean_t has_attn; /* Do we have attn btn? */
6185db853e024a486ff8837e6784dd290d866112dougm boolean_t has_mrl; /* Do we have MRL? */
6185db853e024a486ff8837e6784dd290d866112dougm boolean_t has_emi_lock; /* Do we have EMI Lock? */
6185db853e024a486ff8837e6784dd290d866112dougm
6185db853e024a486ff8837e6784dd290d866112dougm /* link capablities */
6185db853e024a486ff8837e6784dd290d866112dougm boolean_t dll_active_rep; /* Do we report DLL DL_Active state? */
6185db853e024a486ff8837e6784dd290d866112dougm
6185db853e024a486ff8837e6784dd290d866112dougm /* register read/write ops for non-standard HPC (e.g: OPL) */
6185db853e024a486ff8837e6784dd290d866112dougm pciehpc_regops_t regops;
6185db853e024a486ff8837e6784dd290d866112dougm
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm /* platform specific ops (Native HP, ACPI, etc.) */
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm struct pciehpc_ops {
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm /* initialize/setup hot plug controller hw */
6185db853e024a486ff8837e6784dd290d866112dougm int (*init_hpc_hw)(struct pciehpc *ctrl_p);
6185db853e024a486ff8837e6784dd290d866112dougm /* initialize slot information structure */
6185db853e024a486ff8837e6784dd290d866112dougm int (*init_hpc_slotinfo)(struct pciehpc *ctrl_p);
6185db853e024a486ff8837e6784dd290d866112dougm /* disable hot plug interrupts/events */
6185db853e024a486ff8837e6784dd290d866112dougm int (*disable_hpc_intr)(struct pciehpc *ctrl_p);
6185db853e024a486ff8837e6784dd290d866112dougm /* enable hot plug interrupts/events */
6185db853e024a486ff8837e6784dd290d866112dougm int (*enable_hpc_intr)(struct pciehpc *ctrl_p);
6185db853e024a486ff8837e6784dd290d866112dougm /* uninitialize hot plug controller hw */
6185db853e024a486ff8837e6784dd290d866112dougm int (*uninit_hpc_hw)(struct pciehpc *ctrl_p);
6185db853e024a486ff8837e6784dd290d866112dougm /* uninitialize slot information structure */
6185db853e024a486ff8837e6784dd290d866112dougm int (*uninit_hpc_slotinfo)(struct pciehpc *ctrl_p);
6185db853e024a486ff8837e6784dd290d866112dougm /* probe for HPC */
6185db853e024a486ff8837e6784dd290d866112dougm int (*probe_hpc)(struct pciehpc *ctrl_p);
6185db853e024a486ff8837e6784dd290d866112dougm } ops;
6185db853e024a486ff8837e6784dd290d866112dougm
6185db853e024a486ff8837e6784dd290d866112dougm /* platform implementation specific data if any: ACPI, CK804,... */
6185db853e024a486ff8837e6784dd290d866112dougm void *misc_data;
6185db853e024a486ff8837e6784dd290d866112dougm} pciehpc_t;
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm
6185db853e024a486ff8837e6784dd290d866112dougmtypedef struct pciehpc_ops pciehpc_ops_t;
6185db853e024a486ff8837e6784dd290d866112dougm
6185db853e024a486ff8837e6784dd290d866112dougm/*
6185db853e024a486ff8837e6784dd290d866112dougm * PCI-E HPC Command Completion delay in microseconds and the max retry
6185db853e024a486ff8837e6784dd290d866112dougm * count.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm */
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm#define PCIEHPC_CMD_WAIT_TIME 10000
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm#define PCIEHPC_CMD_WAIT_RETRY 100
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm/*
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * PCI-E HPC Dll State Change time out in seconds
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm */
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm#define PCIEHPC_DLL_STATE_CHANGE_TIMEOUT 1
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm#define SLOTCTL_SUPPORTED_INTRS_MASK \
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm (PCIE_SLOTCTL_ATTN_BTN_EN \
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm | PCIE_SLOTCTL_PWR_FAULT_EN \
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm | PCIE_SLOTCTL_MRL_SENSOR_EN \
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm | PCIE_SLOTCTL_PRESENCE_CHANGE_EN \
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm | PCIE_SLOTCTL_CMD_INTR_EN \
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm | PCIE_SLOTCTL_HP_INTR_EN \
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm | PCIE_SLOTCTL_DLL_STATE_EN)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm#define SLOT_STATUS_EVENTS \
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm (PCIE_SLOTSTS_ATTN_BTN_PRESSED \
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm | PCIE_SLOTSTS_PWR_FAULT_DETECTED \
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm | PCIE_SLOTSTS_MRL_SENSOR_CHANGED \
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm | PCIE_SLOTSTS_COMMAND_COMPLETED \
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm | PCIE_SLOTSTS_PRESENCE_CHANGED \
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm | PCIE_SLOTSTS_DLL_STATE_CHANGED)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm
6185db853e024a486ff8837e6784dd290d866112dougm/*
6185db853e024a486ff8837e6784dd290d866112dougm * function prototype defintions for common native mode functions in
6185db853e024a486ff8837e6784dd290d866112dougm * PCIEHPC module.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm */
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmint pciehpc_hpc_init(pciehpc_t *ctrl_p);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmint pciehpc_hpc_uninit(pciehpc_t *ctrl_p);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmint pciehpc_slotinfo_init(pciehpc_t *ctrl_p);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmint pciehpc_enable_intr(pciehpc_t *ctrl_p);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmint pciehpc_disable_intr(pciehpc_t *ctrl_p);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmint pciehpc_slotinfo_uninit(pciehpc_t *ctrl_p);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmint pciehpc_probe_hpc(pciehpc_t *ctrl_p);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmhpc_led_state_t pciehpc_led_state_to_hpc(uint16_t state);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmuint16_t pciehpc_led_state_to_pciehpc(hpc_led_state_t state);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmhpc_led_state_t pciehpc_get_led_state(pciehpc_t *ctrl_p, hpc_led_t led);
6185db853e024a486ff8837e6784dd290d866112dougmvoid pciehpc_set_led_state(pciehpc_t *ctrl_p, hpc_led_t led,
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm hpc_led_state_t state);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmint pciehpc_slot_connect(caddr_t ops_arg, hpc_slot_t slot_hdl,
6185db853e024a486ff8837e6784dd290d866112dougm void *data, uint_t flags);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmint pciehpc_slot_disconnect(caddr_t ops_arg, hpc_slot_t slot_hdl,
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm void *data, uint_t flags);
6185db853e024a486ff8837e6784dd290d866112dougmint pciehpc_slot_control(caddr_t ops_arg, hpc_slot_t slot_hdl,
6185db853e024a486ff8837e6784dd290d866112dougm int request, caddr_t arg);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmvoid pciehpc_get_slot_state(pciehpc_t *ctrl_p);
6185db853e024a486ff8837e6784dd290d866112dougmvoid pciehpc_issue_hpc_command(pciehpc_t *ctrl_p, uint16_t control);
6185db853e024a486ff8837e6784dd290d866112dougmint pciehpc_regs_setup(dev_info_t *dip, uint_t rnum, offset_t off,
6185db853e024a486ff8837e6784dd290d866112dougm caddr_t *addrp, ddi_acc_handle_t *handle);
6185db853e024a486ff8837e6784dd290d866112dougmvoid pciehpc_regs_teardown(ddi_acc_handle_t *handle);
6185db853e024a486ff8837e6784dd290d866112dougmint pciehpc_register_slot(pciehpc_t *ctrl_p);
6185db853e024a486ff8837e6784dd290d866112dougmint pciehpc_unregister_slot(pciehpc_t *ctrl_p);
6185db853e024a486ff8837e6784dd290d866112dougmuint8_t pciehpc_reg_get8(pciehpc_t *ctrl_p, uint_t off);
6185db853e024a486ff8837e6784dd290d866112dougmuint16_t pciehpc_reg_get16(pciehpc_t *ctrl_p, uint_t off);
6185db853e024a486ff8837e6784dd290d866112dougmuint32_t pciehpc_reg_get32(pciehpc_t *ctrl_p, uint_t off);
6185db853e024a486ff8837e6784dd290d866112dougmvoid pciehpc_reg_put8(pciehpc_t *ctrl_p, uint_t off, uint8_t val);
6185db853e024a486ff8837e6784dd290d866112dougmvoid pciehpc_reg_put16(pciehpc_t *ctrl_p, uint_t off, uint16_t val);
6185db853e024a486ff8837e6784dd290d866112dougmvoid pciehpc_reg_put32(pciehpc_t *ctrl_p, uint_t off, uint32_t val);
6185db853e024a486ff8837e6784dd290d866112dougmvoid pciehpc_set_slot_name(pciehpc_t *ctrl_p);
6185db853e024a486ff8837e6784dd290d866112dougm
6185db853e024a486ff8837e6784dd290d866112dougm#if defined(__i386) || defined(__amd64)
6185db853e024a486ff8837e6784dd290d866112dougmvoid pciehpc_update_ops(pciehpc_t *ctrl_p);
6185db853e024a486ff8837e6784dd290d866112dougm#endif /* defined(__i386) || defined(__amd64) */
6185db853e024a486ff8837e6784dd290d866112dougm
6185db853e024a486ff8837e6784dd290d866112dougm#ifdef DEBUG
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmextern int pciehpc_debug;
6185db853e024a486ff8837e6784dd290d866112dougm#define PCIEHPC_DEBUG(args) if (pciehpc_debug >= 1) cmn_err args
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm#define PCIEHPC_DEBUG2(args) if (pciehpc_debug >= 2) cmn_err args
6185db853e024a486ff8837e6784dd290d866112dougm#define PCIEHPC_DEBUG3(args) if (pciehpc_debug >= 3) cmn_err args
6185db853e024a486ff8837e6784dd290d866112dougm#else
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm#define PCIEHPC_DEBUG(args)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm#define PCIEHPC_DEBUG2(args)
6185db853e024a486ff8837e6784dd290d866112dougm#define PCIEHPC_DEBUG3(args)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm#endif
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm
6185db853e024a486ff8837e6784dd290d866112dougm/* default interrupt priority for Hot Plug interrupts */
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm#define PCIEHPC_INTR_PRI 1
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm
6185db853e024a486ff8837e6784dd290d866112dougm#if defined(__sparc)
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm#define PCIE_ENABLE_ERRORS(arg1, arg2) \
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm pcie_enable_errors(arg1, arg2); \
6185db853e024a486ff8837e6784dd290d866112dougm (void) pcie_enable_ce(arg1, arg2)
6185db853e024a486ff8837e6784dd290d866112dougm#define PCIE_DISABLE_ERRORS(arg1, arg2) pcie_disable_errors(arg1, arg2)
6185db853e024a486ff8837e6784dd290d866112dougm#else
6185db853e024a486ff8837e6784dd290d866112dougm#define PCIE_ENABLE_ERRORS(arg1, arg2) pcie_error_enable(arg1, arg2)
6185db853e024a486ff8837e6784dd290d866112dougm#define PCIE_DISABLE_ERRORS(arg1, arg2) pcie_error_disable(arg1, arg2)
7d968cb8b4b6274092771b93e94bf88d1ee31c6cdougm#endif
7d968cb8b4b6274092771b93e94bf88d1ee31c6cdougm
7d968cb8b4b6274092771b93e94bf88d1ee31c6cdougm#ifdef __cplusplus
7d968cb8b4b6274092771b93e94bf88d1ee31c6cdougm}
7d968cb8b4b6274092771b93e94bf88d1ee31c6cdougm#endif
6185db853e024a486ff8837e6784dd290d866112dougm
7d968cb8b4b6274092771b93e94bf88d1ee31c6cdougm#endif /* _SYS_HOTPLUG_PCI_PCIEHPC_IMPL_H */
7d968cb8b4b6274092771b93e94bf88d1ee31c6cdougm