pciehpc_impl.h revision c333dd99c762d509c7eb6cce222221958e23b4c8
6185db853e024a486ff8837e6784dd290d866112dougm * CDDL HEADER START
6185db853e024a486ff8837e6784dd290d866112dougm * The contents of this file are subject to the terms of the
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6185db853e024a486ff8837e6784dd290d866112dougm * You may not use this file except in compliance with the License.
6185db853e024a486ff8837e6784dd290d866112dougm * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
6185db853e024a486ff8837e6784dd290d866112dougm * See the License for the specific language governing permissions
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6185db853e024a486ff8837e6784dd290d866112dougm * fields enclosed by brackets "[]" replaced with your own identifying
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6185db853e024a486ff8837e6784dd290d866112dougm * CDDL HEADER END
f345c0beb4c8f75cb54c2e070498e56febd468acdougm * Copyright 2006 Sun Microsystems, Inc. All rights reserved.
6185db853e024a486ff8837e6784dd290d866112dougm * Use is subject to license terms.
6185db853e024a486ff8837e6784dd290d866112dougm#pragma ident "%Z%%M% %I% %E% SMI"
6185db853e024a486ff8837e6784dd290d866112dougmextern "C" {
6185db853e024a486ff8837e6784dd290d866112dougm * PCI Express Hot Plug slot softstate structure
6185db853e024a486ff8837e6784dd290d866112dougmtypedef struct pciehpc_slot
6185db853e024a486ff8837e6784dd290d866112dougm hpc_slot_info_t slot_info; /* HPS framework slot info */
6185db853e024a486ff8837e6784dd290d866112dougm hpc_slot_ops_t slot_ops; /* HPS framework callbacks */
6185db853e024a486ff8837e6784dd290d866112dougm /* synchronization variable(s) for hot plug events */
6185db853e024a486ff8837e6784dd290d866112dougm kcondvar_t cmd_comp_cv; /* Command Completion intr. */
6185db853e024a486ff8837e6784dd290d866112dougm kcondvar_t attn_btn_cv; /* ATTN button pressed intr */
6185db853e024a486ff8837e6784dd290d866112dougm kthread_t *attn_btn_threadp; /* ATTN button event thread */
6185db853e024a486ff8837e6784dd290d866112dougm kcondvar_t dll_active_cv; /* DLL State Changed intr */
6185db853e024a486ff8837e6784dd290d866112dougmtypedef enum {
6185db853e024a486ff8837e6784dd290d866112dougm/* init_flags */
6185db853e024a486ff8837e6784dd290d866112dougm * PCI Express Hotplug controller soft state structure
6185db853e024a486ff8837e6784dd290d866112dougmtypedef struct pciehpc
6185db853e024a486ff8837e6784dd290d866112dougm pciehpc_soft_state_t soft_state; /* soft state flags */
6185db853e024a486ff8837e6784dd290d866112dougm pciehpc_hp_mode_t hp_mode; /* HP mode (Native, ACPI) */
6185db853e024a486ff8837e6784dd290d866112dougm /* PCIE Hot Plug Controller register access */
6185db853e024a486ff8837e6784dd290d866112dougm uint_t pcie_caps_reg_offset; /* offset to PCIE Cap regs */
6185db853e024a486ff8837e6784dd290d866112dougm /* slot information */
6185db853e024a486ff8837e6784dd290d866112dougm /* link capablities */
6185db853e024a486ff8837e6784dd290d866112dougm boolean_t dll_active_rep; /* Do we report DLL DL_Active state? */
6185db853e024a486ff8837e6784dd290d866112dougm /* register read/write ops for non-standard HPC (e.g: OPL) */
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm /* platform specific ops (Native HP, ACPI, etc.) */
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm /* initialize/setup hot plug controller hw */
6185db853e024a486ff8837e6784dd290d866112dougm /* initialize slot information structure */
6185db853e024a486ff8837e6784dd290d866112dougm /* disable hot plug interrupts/events */
6185db853e024a486ff8837e6784dd290d866112dougm /* enable hot plug interrupts/events */
6185db853e024a486ff8837e6784dd290d866112dougm /* uninitialize hot plug controller hw */
6185db853e024a486ff8837e6784dd290d866112dougm /* uninitialize slot information structure */
6185db853e024a486ff8837e6784dd290d866112dougm /* probe for HPC */
6185db853e024a486ff8837e6784dd290d866112dougm /* platform implementation specific data if any: ACPI, CK804,... */
6185db853e024a486ff8837e6784dd290d866112dougm * PCI-E HPC Command Completion delay in microseconds and the max retry
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm * PCI-E HPC Dll State Change time out in seconds
6185db853e024a486ff8837e6784dd290d866112dougm * function prototype defintions for common native mode functions in
6185db853e024a486ff8837e6784dd290d866112dougm * PCIEHPC module.
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmhpc_led_state_t pciehpc_led_state_to_hpc(uint16_t state);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmuint16_t pciehpc_led_state_to_pciehpc(hpc_led_state_t state);
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmhpc_led_state_t pciehpc_get_led_state(pciehpc_t *ctrl_p, hpc_led_t led);
6185db853e024a486ff8837e6784dd290d866112dougmvoid pciehpc_set_led_state(pciehpc_t *ctrl_p, hpc_led_t led,
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmint pciehpc_slot_connect(caddr_t ops_arg, hpc_slot_t slot_hdl,
25a68471b9ababbc21cfdbbb2866014f34f419ecdougmint pciehpc_slot_disconnect(caddr_t ops_arg, hpc_slot_t slot_hdl,
6185db853e024a486ff8837e6784dd290d866112dougmint pciehpc_slot_control(caddr_t ops_arg, hpc_slot_t slot_hdl,
6185db853e024a486ff8837e6784dd290d866112dougmvoid pciehpc_issue_hpc_command(pciehpc_t *ctrl_p, uint16_t control);
6185db853e024a486ff8837e6784dd290d866112dougmint pciehpc_regs_setup(dev_info_t *dip, uint_t rnum, offset_t off,
6185db853e024a486ff8837e6784dd290d866112dougmuint8_t pciehpc_reg_get8(pciehpc_t *ctrl_p, uint_t off);
6185db853e024a486ff8837e6784dd290d866112dougmuint16_t pciehpc_reg_get16(pciehpc_t *ctrl_p, uint_t off);
6185db853e024a486ff8837e6784dd290d866112dougmuint32_t pciehpc_reg_get32(pciehpc_t *ctrl_p, uint_t off);
6185db853e024a486ff8837e6784dd290d866112dougmvoid pciehpc_reg_put8(pciehpc_t *ctrl_p, uint_t off, uint8_t val);
6185db853e024a486ff8837e6784dd290d866112dougmvoid pciehpc_reg_put16(pciehpc_t *ctrl_p, uint_t off, uint16_t val);
6185db853e024a486ff8837e6784dd290d866112dougmvoid pciehpc_reg_put32(pciehpc_t *ctrl_p, uint_t off, uint32_t val);
6185db853e024a486ff8837e6784dd290d866112dougm#endif /* defined(__i386) || defined(__amd64) */
6185db853e024a486ff8837e6784dd290d866112dougm#define PCIEHPC_DEBUG(args) if (pciehpc_debug >= 1) cmn_err args
25a68471b9ababbc21cfdbbb2866014f34f419ecdougm#define PCIEHPC_DEBUG2(args) if (pciehpc_debug >= 2) cmn_err args
6185db853e024a486ff8837e6784dd290d866112dougm#define PCIEHPC_DEBUG3(args) if (pciehpc_debug >= 3) cmn_err args
6185db853e024a486ff8837e6784dd290d866112dougm/* default interrupt priority for Hot Plug interrupts */
6185db853e024a486ff8837e6784dd290d866112dougm#if defined(__sparc)
6185db853e024a486ff8837e6784dd290d866112dougm#define PCIE_DISABLE_ERRORS(arg1, arg2) pcie_disable_errors(arg1, arg2)
6185db853e024a486ff8837e6784dd290d866112dougm#define PCIE_ENABLE_ERRORS(arg1, arg2) pcie_error_enable(arg1, arg2)
6185db853e024a486ff8837e6784dd290d866112dougm#define PCIE_DISABLE_ERRORS(arg1, arg2) pcie_error_disable(arg1, arg2)
7d968cb8b4b6274092771b93e94bf88d1ee31c6cdougm#endif /* _SYS_HOTPLUG_PCI_PCIEHPC_IMPL_H */