qlge.h revision a6766df40e85f57b203ec7f2143dd1a99e6fe03d
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2010 QLogic Corporation. All rights reserved.
*/
#ifndef _QLGE_H
#define _QLGE_H
#ifdef __cplusplus
extern "C" {
#endif
#include <sys/mac_provider.h>
#include <sys/mac_flow.h>
#include <sys/mac_ether.h>
#include <sys/ethernet.h>
#include <sys/byteorder.h>
#include <qlge_hw.h>
#include <qlge_dbg.h>
#include <qlge_open.h>
#define ADAPTER_NAME "qlge"
/*
* Local Macro Definitions.
*/
#ifdef TRUE
#endif
#define TRUE 1
#ifdef FALSE
#endif
#define FALSE 0
/* #define QLGE_TRACK_BUFFER_USAGE */
/*
* byte order, sparc is big endian, x86 is little endian,
* but PCI is little endian only
*/
#ifdef sparc
#define cpu_to_le64(x) BSWAP_64(x)
#define cpu_to_le32(x) BSWAP_32(x)
#define cpu_to_le16(x) BSWAP_16(x)
#define le64_to_cpu(x) cpu_to_le64(x)
#define le32_to_cpu(x) cpu_to_le32(x)
#define le16_to_cpu(x) cpu_to_le16(x)
#else
#define cpu_to_le64(x) (x)
#define cpu_to_le32(x) (x)
#define cpu_to_le16(x) (x)
#define le64_to_cpu(x) (x)
#define le32_to_cpu(x) (x)
#define le16_to_cpu(x) (x)
#endif
/*
* Macros to help code, maintain, etc.
*/
SWAP_ENDIAN_16(MSW(x)))
SWAP_ENDIAN_32(MS32(x)))
#define QL_MIN(x, y) ((x < y) ? x : y)
/*
* qlge local function return status codes
*/
#define QL_ERROR 1
#define QL_SUCCESS 0
/*
* Solaris version compatibility definitions.
*/
#define MINOR_NODE_FLAG 8
/*
* Host adapter default definitions.
*/
/* Timeout timer counts in seconds (must greater than 1 second). */
#define QL_ONE_SEC_DELAY 1000000
#define QL_ONE_MSEC_DELAY 1000
/*
* DMA attributes definitions.
*/
#define QL_DMA_LOW_ADDRESS (uint64_t)0
#define QL_DMA_BURSTSIZES 0xfff
#define QL_DMA_MIN_XFER_SIZE 1
#define QL_DMA_GRANULARITY 1
#define QL_DMA_XFER_FLAGS 0
#define QL_MAX_COOKIES 16
/*
* ISP PCI Configuration.
*/
/* GLD */
/* GLD DMA */
extern ddi_device_acc_attr_t ql_dev_acc_attr;
extern ddi_device_acc_attr_t ql_buf_acc_attr;
struct dma_info {
void *vaddr;
};
/*
* Sync a DMA area described by a dma_info
*/
/*
* Find the (kernel virtual) address of block of memory
* described by a dma_info
*/
/*
* Zero a block of memory described by a dma_info
*/
#define MAX_SG_ELEMENTS 16
#define QL_MAX_TX_DMA_HANDLES MAX_SG_ELEMENTS
/*
* ISP PCI Configuration.
*/
/* Initialize steps */
#define INIT_SOFTSTATE_ALLOC BIT_0
#define INIT_REGS_SETUP BIT_1
#define INIT_DOORBELL_REGS_SETUP BIT_2
#define INIT_MAC_ALLOC BIT_3
#define INIT_PCI_CONFIG_SETUP BIT_4
#define INIT_SETUP_RINGS BIT_5
#define INIT_MEMORY_ALLOC BIT_6
#define INIT_INTR_ALLOC BIT_7
#define INIT_ADD_INTERRUPT BIT_8
#define INIT_LOCKS_CREATED BIT_9
#define INIT_ADD_SOFT_INTERRUPT BIT_10
#define INIT_MUTEX BIT_11
#define ADAPTER_INIT BIT_12
#define INIT_MAC_REGISTERED BIT_13
#define INIT_KSTATS BIT_14
#define INIT_ADAPTER_UP BIT_16
#define INIT_ALLOC_RX_BUF BIT_17
#define INIT_INTR_ENABLED BIT_18
typedef uint64_t dma_addr_t;
/*
* LSO can support up to 65535 bytes of data, but can not be sent in one IOCB
* which only has 8 TX OALs, additional OALs must be applied separately.
*/
enum tx_mode_t {
};
#define QL_MAX_COPY_LENGTH 256
#define MAX_FRAGMENTS_IN_IOCB 7
#ifndef VLAN_ID_MASK
#define VLAN_ID_MASK 0x0fffu
#endif
#ifndef VLAN_TAGSZ
#define VLAN_TAGSZ 4
#endif
#ifndef ETHERTYPE_VLAN
#define ETHERTYPE_VLAN 0x8100
#endif
#ifndef MBLKL
#endif
/*
* Checksum Offload
*/
#define TCP_CKSUM_OFFSET 16
#define UDP_CKSUM_OFFSET 6
#define IPPROTO_IPv6OVERv4 41
/*
* Driver must be in one of these states
*/
enum mac_state {
QL_MAC_INIT, /* in the initialization stage */
QL_MAC_ATTACHED, /* driver attached */
QL_MAC_STARTED, /* interrupt enabled, driver is ready */
QL_MAC_BRINGDOWN, /* in the bring down process */
QL_MAC_STOPPED, /* stoped, no more interrupts */
QL_MAC_DETACH, /* to be detached */
};
/*
* Soft Request Flag
*/
/*
* (Internal) return values from ioctl subroutines
*/
enum ioc_reply {
IOC_DONE, /* OK, reply sent */
IOC_ACK, /* OK, just send ACK */
IOC_REPLY, /* OK, just send reply */
IOC_RESTART_ACK, /* OK, restart & ACK */
IOC_RESTART_REPLY /* OK, restart & reply */
};
/*
* Link Speed,in Mbps
*/
#define SPEED_10 10
#define SPEED_100 100
#define SPEED_1000 1000
#define SPEED_10G 10000
/*
* Multicast List
*/
typedef struct {
struct ether_addr addr;
unsigned char reserved[2];
#define MAX_MULTICAST_LIST_SIZE 128
typedef struct {
#define MAX_UNICAST_LIST_SIZE 128
/*
* Device kstate structure.
*/
enum {
QL_KSTAT_CHIP = 0,
};
/*
*/
enum {
BIT_SET = 0,
};
/*
* Flash Image Search State
*/
enum { STOP_SEARCH, /* Image address bad, no more search */
CONTINUE_SEARCH, /* Image address ok, continue search */
LAST_IMAGE_FOUND /* Found last image and FLTDS address */
};
/*
* Loop Back Modes
*/
enum { QLGE_LOOP_NONE,
};
/* for soft state routine */
typedef struct {
char *name;
} ql_ksindex_t;
struct bq_desc {
/* is to be freed by OS */
/* being freed, new one should not */
/* be allocated */
};
#define VM_PAGE_SIZE 4096
#define QLGE_POLL_ALL -1
#define SMALL_BUFFER_SIZE 512
#define LARGE_BUFFER_SIZE 4096
#define MAX_TX_WAIT_COUNT 1000
#define MIN_BUFFERS_ARM_COUNT 16
/* value, arm the chip */
/* if less than 16 free lrg buf nodes in the free list, then */
/* rx has to use copy method to send packets upstream */
/* if there are more than TX_STOP_THRESHOLD free tx buffers, try to send it */
#define TX_STOP_THRESHOLD 16
#define TX_RESUME_THRESHOLD 8
struct tx_ring_desc {
int tx_dma_handle_used;
void *oal;
};
struct tx_ring {
/* tx completions */
volatile uint32_t tx_free_count;
struct tx_ring_desc *wq_desc;
/* shadow copy of consumer idx */
/* dma-shadow copy consumer */
};
struct bq_element {
};
/*
* Type of inbound queue.
*/
enum {
};
struct rx_ring {
/* GLD required flags */
/* statistics */
volatile uint32_t rx_indicate;
/* miscellaneous */
int type; /* DEFAULT_Q, TX_Q, RX_Q */
/* completion queue */
/* large buffer queue */
struct bq_desc **lbuf_in_use;
volatile uint32_t lbuf_in_use_count;
/* small buffer queue */
struct bq_desc **sbuf_in_use;
volatile uint32_t sbuf_in_use_count;
/* for test purpose */
#ifdef QLGE_PERFORMANCE
#endif
};
struct intr_ctx {
/*
* It's incremented for
* each irq handler that is scheduled.
* When each handler finishes it
* decrements irq_cnt and enables
* interrupts if it's zero.
*/
};
struct tx_buf_desc {
#define TX_DESC_LEN_MASK 0x000fffff
#define TX_DESC_C 0x40000000
#define TX_DESC_E 0x80000000
};
typedef struct qlge {
/*
* Solaris adapter configuration data
*/
int instance;
/* fault management capabilities */
int fm_capabilities;
#define CFG_JUMBLE_PACKET BIT_1
#define CFG_RX_COPY_MODE BIT_2
#define CFG_SUPPORT_MULTICAST BIT_3
#define CFG_HW_UNABLE_PSEUDO_HDR_CKSUM BIT_4
#define CFG_CKSUM_HEADER_IPv4 BIT_5
#define CFG_CKSUM_PARTIAL BIT_6
#define CFG_CKSUM_FULL_IPv4 BIT_7
#define CFG_CKSUM_FULL_IPv6 BIT_8
#define CFG_SUPPORT_SCATTER_GATHER BIT_10
#define CFG_ENABLE_SPLIT_HEADER BIT_11
#define CFG_ENABLE_EXTENDED_LOGGING BIT_15
#define CFG_CHIP_8100 BIT_16
/* For Shadow Registers, used by adapter to write to host memory */
struct dma_info host_copy_shadow_dma_attr;
/*
* for each CQICB and read by chip, new request since 8100
*/
struct dma_info buf_q_ptr_base_addr_dma_attr;
/*
* Debugging
*/
/*
* GLD
*/
/*
* mutex
*/
/*
* Generic timer
*/
/*
* Interrupt
*/
int intr_type;
/* for legacy interrupt */
/* for MSI and Fixed interrupts */
int intr_cnt; /* # of intrs actually allocated */
int intr_cap; /* Interrupt capabilities */
/* interrupt handlers */
/* Power management context. */
#define MAX_POWER_LEVEL 0
/*
* General NIC
*/
/*
* PCI status
*/
/*
* Multicast list
*/
/*
* MAC address information
*/
/*
* Soft Interrupt handlers
*/
/* soft interrupt handle for MPI interrupt */
/* soft interrupt handle for asic reset */
/* soft interrupt handle for mpi reset */
/*
* IOCTL
*/
/* new ioctl admin flags to work around the 1024 max data copy in&out */
/*
* Mailbox lock and flags
*/
struct dma_info ioctl_buf_dma_attr;
/*
* Flash
*/
/*
* TX / RX
*/
int tx_ring_size;
int rx_ring_size;
#ifdef QLGE_TRACK_BUFFER_USAGE
/* Count no of times the buffers fell below 32 */
#endif
} qlge_t;
/*
* Reconfiguring the network devices requires the net_config privilege
* in Solaris 10+.
*/
/*
* Global Function Prototypes in qlge_dbg.c source file.
*/
extern int ql_fw_dump(qlge_t *);
extern void ql_dump_all_contrl_regs(qlge_t *);
extern void ql_dump_pci_config(qlge_t *);
extern void ql_dump_host_pci_regs(qlge_t *);
/*
* Global Data in qlge.c source file.
*/
extern int ql_init_misc_registers(qlge_t *);
extern int ql_init_mem_resources(qlge_t *);
extern int ql_do_start(qlge_t *);
extern int ql_do_stop(qlge_t *);
extern void ql_set_promiscuous(qlge_t *, int);
extern void ql_get_hw_stats(qlge_t *);
extern void ql_wake_asic_reset_soft_intr(qlge_t *);
extern mblk_t *ql_ring_rx_poll(void *, int);
/*
* Global Function Prototypes in qlge_flash.c source file.
*/
extern int ql_sem_flash_lock(qlge_t *);
extern void ql_sem_flash_unlock(qlge_t *);
/*
* Global Function Prototypes in qlge_mpi.c source file.
*/
extern int ql_reset_mpi_risc(qlge_t *);
extern int ql_get_LED_config(qlge_t *);
extern int ql_get_firmware_version(qlge_t *,
struct qlnic_mpi_version_info *);
extern void ql_core_dump(qlge_t *);
extern void ql_dump_crash_record(qlge_t *);
extern void ql_printf(const char *, ...);
/*
* Global Function Prototypes in qlge_gld.c source file.
*/
/*
* Global Function Prototypes in qlge_fm.c source file.
*/
#ifdef __cplusplus
}
#endif
#endif /* _QLGE_H */