ql_api.h revision f885d00f4e3c96a769ce0228a732da31ad9d0b78
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/* Copyright 2010 QLogic Corporation */
/*
*/
#ifndef _QL_API_H
#define _QL_API_H
/*
* ISP2xxx Solaris Fibre Channel Adapter (FCA) driver header file.
*
* ***********************************************************************
* * **
* * NOTICE **
* * COPYRIGHT (C) 1996-2010 QLOGIC CORPORATION **
* * ALL RIGHTS RESERVED **
* * **
* ***********************************************************************
*
*/
#ifdef __cplusplus
extern "C" {
#endif
/* OS include files. */
#include <sys/byteorder.h>
#include <ql_open.h>
#ifndef DDI_INTR_TYPE_FIXED
#define DDI_INTR_TYPE_FIXED 0x1
#endif
#ifndef DDI_INTR_TYPE_MSI
#define DDI_INTR_TYPE_MSI 0x2
#endif
#ifndef DDI_INTR_TYPE_MSIX
#define DDI_INTR_TYPE_MSIX 0x4
#endif
#ifndef DDI_INTR_FLAG_BLOCK
#define DDI_INTR_FLAG_BLOCK 0x100
#endif
#ifndef DDI_INTR_ALLOC_NORMAL
#define DDI_INTR_ALLOC_NORMAL 0
#endif
#ifndef DDI_INTR_ALLOC_STRICT
#define DDI_INTR_ALLOC_STRICT 1
#endif
/*
* NPIV defines
*/
#ifndef FC_NPIV_FDISC_FAILED
#define FC_NPIV_FDISC_FAILED 0x45
#endif
#ifndef FC_NPIV_FDISC_WWN_INUSE
#define FC_NPIV_FDISC_WWN_INUSE 0x46
#endif
#ifndef FC_NPIV_NOT_SUPPORTED
#define FC_NPIV_NOT_SUPPORTED 0x47
#endif
#ifndef FC_NPIV_WRONG_TOPOLOGY
#define FC_NPIV_WRONG_TOPOLOGY 0x48
#endif
#ifndef FC_NPIV_NPIV_BOUND
#define FC_NPIV_NPIV_BOUND 0x49
#endif
#pragma weak ddi_intr_get_supported_types
#pragma weak ddi_intr_get_nintrs
#pragma weak ddi_intr_alloc
#pragma weak ddi_intr_free
#pragma weak ddi_intr_get_pri
#pragma weak ddi_intr_add_handler
#pragma weak ddi_intr_dup_handler
#pragma weak ddi_intr_get_navail
#pragma weak ddi_intr_block_disable
#pragma weak ddi_intr_block_enable
#pragma weak ddi_intr_disable
#pragma weak ddi_intr_enable
#pragma weak ddi_intr_get_cap
#pragma weak ddi_intr_remove_handler
extern int ddi_intr_get_supported_types();
extern int ddi_intr_get_nintrs();
extern int ddi_intr_alloc();
extern int ddi_intr_free();
extern int ddi_intr_get_pri();
extern int ddi_intr_add_handler();
extern int ddi_intr_dup_handler();
extern int ddi_intr_get_navail();
extern int ddi_intr_block_disable();
extern int ddi_intr_block_enable();
extern int ddi_intr_disable();
extern int ddi_intr_enable();
extern int ddi_intr_get_cap();
extern int ddi_intr_remove_handler();
#ifndef QL_DRV_HARDENING
#define ddi_devstate_t int
#define DDI_DEVSTATE_UP 0
#define ddi_get_devstate(a) DDI_DEVSTATE_UP
#define ddi_dev_report_fault(a, b, c, d)
#define ddi_check_dma_handle(a) DDI_SUCCESS
#define ddi_check_acc_handle(a) DDI_SUCCESS
#define QL_CLEAR_DMA_HANDLE(x)
#else
((ddi_dma_impl_t *)x)->dmai_fault_check = 0; \
((ddi_dma_impl_t *)x)->dmai_fault = 0
#endif
#ifndef FC_STATE_1GBIT_SPEED
#endif
#ifndef FC_STATE_2GBIT_SPEED
#endif
#ifndef FC_STATE_4GBIT_SPEED
#endif
#ifndef FC_STATE_8GBIT_SPEED
#endif
#ifndef FC_STATE_10GBIT_SPEED
#endif
/*
* Data bit definitions.
*/
#define BIT_0 0x1
#define BIT_1 0x2
#define BIT_2 0x4
#define BIT_3 0x8
#define BIT_4 0x10
#define BIT_5 0x20
#define BIT_6 0x40
#define BIT_7 0x80
#define BIT_8 0x100
#define BIT_9 0x200
#define BIT_10 0x400
#define BIT_11 0x800
#define BIT_12 0x1000
#define BIT_13 0x2000
#define BIT_14 0x4000
#define BIT_15 0x8000
#define BIT_16 0x10000
#define BIT_17 0x20000
#define BIT_18 0x40000
#define BIT_19 0x80000
#define BIT_20 0x100000
#define BIT_21 0x200000
#define BIT_22 0x400000
#define BIT_23 0x800000
#define BIT_24 0x1000000
#define BIT_25 0x2000000
#define BIT_26 0x4000000
#define BIT_27 0x8000000
#define BIT_28 0x10000000
#define BIT_29 0x20000000
#define BIT_30 0x40000000
#define BIT_31 0x80000000
/*
* Local Macro Definitions.
*/
#ifndef TRUE
#endif
#ifndef FALSE
#endif
/*
* I/O register
*/
/*
* FCA definitions
*/
#define MAX_LUNS 16384
#define QL_FCA_BRAND 0x0fca2200
/* Following to be removed when defined by OS. */
/* ************************************************************************ */
#define LA_ELS_FARP_REQ 0x54
#define LA_ELS_FARP_REPLY 0x55
#define LA_ELS_LPC 0x71
#define LA_ELS_LSTS 0x72
typedef struct {
} ql_lpc_t;
typedef struct {
} ql_acc_rjt_t;
typedef fc_linit_resp_t ql_lpc_resp_t;
typedef fc_scr_resp_t ql_rscn_resp_t;
typedef struct {
typedef struct {
/* *********************************************************************** */
/*
* Fibre Channel device definitions.
*/
#define MAX_22_FIBRE_DEVICES 256
#define MAX_24_FIBRE_DEVICES 2048
#define MAX_24_VIRTUAL_PORTS 127
#define MAX_25_VIRTUAL_PORTS 254
#define LAST_LOCAL_LOOP_ID 0x7d
#define SNS_FIRST_LOOP_ID 0x81
#define SNS_LAST_LOOP_ID 0xfe
/*
* Fibre Channel 24xx device definitions.
*/
#define LAST_N_PORT_HDL 0x7ef
/* Loop ID's used as flags, must be higher than any valid Loop ID */
/* Fibre Channel Topoploy. */
#define QL_NL_PORT BIT_1
#define QL_FL_PORT BIT_3
#define QL_SNS_CONNECTION BIT_4
/* Timeout timer counts in seconds (must greater than 1 second). */
#define LOOP_DOWN_TIMER_OFF 0
#define LOOP_DOWN_TIMER_END 1
/* Maximum outstanding commands in ISP queues (1-4095) */
#define MAX_OUTSTANDING_COMMANDS 0x400
#define OSC_INDEX_MASK 0xfff
#define OSC_INDEX_SHIFT 12
/* Maximum unsolicited buffers (1-65535) */
#define QL_UB_LIMIT 256
/* ISP request, response and receive buffer entry counts */
/*
* ISP request, response, mailbox and receive buffer queue sizes
*/
#define REQUEST_ENTRY_SIZE 64
#define RESPONSE_ENTRY_SIZE 64
#define MAILBOX_BUFFER_SIZE 0x4000
#define RCVBUF_CONTAINER_SIZE 12
/*
* ISP DMA buffer definitions
*/
#define REQUEST_Q_BUFFER_OFFSET 0
/*
* DMA attributes definitions.
*/
#define QL_DMA_LOW_ADDRESS (uint64_t)0
#define QL_DMA_BURSTSIZES 0xff
#define QL_DMA_MIN_XFER_SIZE 1
#ifdef __sparc
#define QL_DMA_SG_LIST_LENGTH 1
#define QL_FCSM_CMD_SGLLEN 1
#define QL_FCSM_RSP_SGLLEN 1
#define QL_FCIP_CMD_SGLLEN 1
#define QL_FCIP_RSP_SGLLEN 1
#define QL_FCP_CMD_SGLLEN 1
#define QL_FCP_RSP_SGLLEN 1
#else
#define QL_DMA_SG_LIST_LENGTH 1024
#define QL_FCSM_CMD_SGLLEN 1
#define QL_FCSM_RSP_SGLLEN 6
/*
* QL_FCIP_CMD_SGLLEN needs to be increased as we changed the max fcip packet
* size to about 64K. With this, we need to increase the maximum number of
* scatter-gather elements allowable from the existing 7. We want it to be more
* like 17 (max fragments for an fcip packet that is unaligned). (64K / 4K) + 1
* or whatever. Otherwise the DMA breakup routines will give bad results.
*/
#define QL_FCIP_CMD_SGLLEN 17
#define QL_FCIP_RSP_SGLLEN 1
#define QL_FCP_CMD_SGLLEN 1
#define QL_FCP_RSP_SGLLEN 1
#endif
#ifndef DDI_DMA_RELAXED_ORDERING
#define DDI_DMA_RELAXED_ORDERING 0x400
#endif
#define QL_DMA_GRANULARITY 1
#define QL_DMA_XFER_FLAGS 0
typedef union {
} conv_num_t;
/*
* Device register offsets.
*/
#define MAX_MBOX_COUNT 32
typedef struct {
} reg_off_t;
/*
* Mbox-8 read maximum debounce count.
* Reading Mbox-8 could be debouncing, before getting stable value.
* This is the recommended driver fix from Qlogic along with firmware fix.
* During testing, maximum count did not cross 3.
*/
#define QL_MAX_DEBOUNCE 10
/*
* Control Status register definitions
*/
/*
* Control Status 24xx register definitions
*/
#define FLASH_NVRAM_ACCESS_ERROR BIT_18
#define DMA_ACTIVE BIT_17
#define DMA_SHUTDOWN BIT_16
#define FUNCTION_NUMBER BIT_15
#define MWB_2048_BYTES BIT_5
#define MWB_1024_BYTES BIT_4
#define MWB_512_BYTES 0
/*
* Interrupt Control register definitions
*/
/*
* Interrupt Status register definitions
*/
/*
*/
/*
* NVRAM register definitions.
*/
#define NV_DESELECT 0
#define NV_DATA_OUT BIT_2
#define NV_DATA_IN BIT_3
/*
*/
#define FLASH_DATA_FLAG BIT_31
#define FLASH_CONF_ADDR 0x7FFD0000
#define FLASH_24_25_DATA_ADDR 0x7FF00000
#define FLASH_8100_DATA_ADDR 0x7F800000
#define FLASH_ADDR_MASK 0x7FFF0000
#define NVRAM_CONF_ADDR 0x7FFF0000
#define NVRAM_DATA_ADDR 0x7FFE0000
#define NVRAM_2200_FUNC0_ADDR 0x0
#define NVRAM_2300_FUNC0_ADDR 0x0
#define NVRAM_2300_FUNC1_ADDR 0x80
#define NVRAM_2400_FUNC0_ADDR 0x80
#define NVRAM_2400_FUNC1_ADDR 0x180
#define NVRAM_2500_FUNC0_ADDR 0x48080
#define NVRAM_2500_FUNC1_ADDR 0x48180
#define NVRAM_8100_FUNC0_ADDR 0xD0080
#define NVRAM_8100_FUNC1_ADDR 0xD0180
#define NVRAM_8021_FUNC0_ADDR 0xF0080
#define NVRAM_8021_FUNC1_ADDR 0xF0180
#define VPD_2400_FUNC0_ADDR 0
#define VPD_2400_FUNC1_ADDR 0x100
#define VPD_2500_FUNC0_ADDR 0x48000
#define VPD_2500_FUNC1_ADDR 0x48100
#define VPD_8100_FUNC0_ADDR 0xD0000
#define VPD_8100_FUNC1_ADDR 0xD0400
#define VPD_8021_FUNC0_ADDR 0xFA300
#define VPD_8021_FUNC1_ADDR 0xFA300
#define VPD_SIZE 0x80
#define FLASH_2200_FIRMWARE_ADDR 0x20000
#define FLASH_2300_FIRMWARE_ADDR 0x20000
#define FLASH_2400_FIRMWARE_ADDR 0x20000
#define FLASH_2500_FIRMWARE_ADDR 0x20000
#define FLASH_8100_FIRMWARE_ADDR 0xA0000
#define FLASH_8021_FIRMWARE_ADDR 0x40000
#define FLASH_8021_FIRMWARE_SIZE 0x80000
#define FLASH_8021_BOOTLOADER_ADDR 0x4000
#define FLASH_8021_BOOTLOADER_SIZE 0x8000
#define FLASH_2400_ERRLOG_START_ADDR_0 0
#define FLASH_2400_ERRLOG_START_ADDR_1 0
#define FLASH_2500_ERRLOG_START_ADDR_0 0x54000
#define FLASH_2500_ERRLOG_START_ADDR_1 0x54400
#define FLASH_8100_ERRLOG_START_ADDR_0 0xDC000
#define FLASH_8100_ERRLOG_START_ADDR_1 0xDC400
#define FLASH_ERRLOG_SIZE 0x200
#define FLASH_ERRLOG_ENTRY_SIZE 4
#define FLASH_2400_DESCRIPTOR_TABLE 0
#define FLASH_2500_DESCRIPTOR_TABLE 0x50000
#define FLASH_8100_DESCRIPTOR_TABLE 0xD8000
#define FLASH_8021_DESCRIPTOR_TABLE 0
#define FLASH_2400_LAYOUT_TABLE 0x11400
#define FLASH_2500_LAYOUT_TABLE 0x50400
#define FLASH_8100_LAYOUT_TABLE 0xD8400
#define FLASH_8021_LAYOUT_TABLE 0xFC400
/*
* Flash Error Log Event Codes.
*/
#define FLASH_ERRLOG_AEN_8002 0x8002
#define FLASH_ERRLOG_AEN_8003 0x8003
#define FLASH_ERRLOG_AEN_8004 0x8004
#define FLASH_ERRLOG_RESET_ERR 0xF00B
#define FLASH_ERRLOG_ISP_ERR 0xF020
#define FLASH_ERRLOG_PARITY_ERR 0xF022
#define FLASH_ERRLOG_NVRAM_CHKSUM_ERR 0xF023
#define FLASH_ERRLOG_FLASH_FW_ERR 0xF024
#define VPD_TAG_END 0x78
#define VPD_TAG_CHKSUM "RV"
#define VPD_TAG_SN "SN"
#define VPD_TAG_PN "PN"
#define VPD_TAG_PRODID "\x82"
#define VPD_TAG_LRT 0x90
#define VPD_TAG_LRTC 0x91
/*
* RISC to Host Status register definitions.
*/
/*
* RISC to Host Status register status field definitions.
*/
#define ROM_MBX_SUCCESS 0x01
#define ROM_MBX_ERR 0x02
#define MBX_SUCCESS 0x10
#define MBX_ERR 0x11
#define ASYNC_EVENT 0x12
#define RESP_UPDATE 0x13
#define REQ_UPDATE 0x14
#define SCSI_FAST_POST_16 0x15
#define SCSI_FAST_POST_32 0x16
#define CTIO_FAST_POST 0x17
#define IP_FAST_POST_XMT 0x18
#define IP_FAST_POST_RCV 0x19
#define IP_FAST_POST_BRD 0x1a
#define IP_FAST_POST_RCV_ALN 0x1b
#define ATIO_UPDATE 0x1c
#define ATIO_RESP_UPDATE 0x1d
/*
* HCCR commands.
*/
/* RISC pause. */
/*
* HCCR commands for 24xx and 25xx.
*/
/*
* ISP Initialization Control Blocks.
* Little endian except where noted.
*/
#define ICB_VERSION 1
typedef struct ql_init_cb {
/*
* LSB BIT 0 = enable_hard_loop_id
* LSB BIT 1 = enable_fairness
* LSB BIT 2 = enable_full_duplex
* LSB BIT 3 = enable_fast_posting
* LSB BIT 4 = enable_target_mode
* LSB BIT 5 = disable_initiator_mode
* LSB BIT 6 = enable_adisc
* LSB BIT 7 = enable_target_inquiry_data
*
* MSB BIT 0 = enable_port_update_ae
* MSB BIT 1 = disable_initial_lip
* MSB BIT 2 = enable_decending_soft_assign
* MSB BIT 3 = previous_assigned_addressing
* MSB BIT 4 = enable_stop_q_on_full
* MSB BIT 5 = enable_full_login_on_lip
* MSB BIT 6 = enable_node_name
* MSB BIT 7 = extended_control_block
*/
/*
* LSB BIT 0 = Timer operation mode bit 0
* LSB BIT 1 = Timer operation mode bit 1
* LSB BIT 2 = Timer operation mode bit 2
* LSB BIT 3 = Timer operation mode bit 3
* LSB BIT 4 = P2P Connection option bit 0
* LSB BIT 5 = P2P Connection option bit 1
* LSB BIT 6 = P2P Connection option bit 2
* LSB BIT 7 = Enable Non part on LIHA failure
*
* MSB BIT 0 = Enable class 2
* MSB BIT 1 = Enable ACK0
* MSB BIT 2 =
* MSB BIT 3 =
* MSB BIT 4 = FC Tape Enable
* MSB BIT 5 = Enable FC Confirm
* MSB BIT 6 = Enable CRN
* MSB BIT 7 =
*/
/*
* LSB BIT 0 = Enable Read xfr_rdy
* LSB BIT 1 = Soft ID only
* LSB BIT 2 =
* LSB BIT 3 =
* LSB BIT 4 = FCP RSP Payload [0]
* LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
* LSB BIT 6 =
* LSB BIT 7 =
*
* MSB BIT 0 = Sbus enable - 2300
* MSB BIT 1 =
* MSB BIT 2 =
* MSB BIT 3 =
* MSB BIT 4 =
* MSB BIT 5 = enable 50 ohm termination
* MSB BIT 6 = Data Rate (2300 only)
* MSB BIT 7 = Data Rate (2300 only)
*/
} ql_init_cb_t;
/*
* Virtual port definition.
*/
typedef struct ql_vp_cfg {
} ql_vp_cfg_t;
/*
* VP options.
*/
#define VPO_ENABLE_SNS_LOGIN_SCR BIT_6
#define VPO_TARGET_MODE_DISABLED BIT_5
#define VPO_INITIATOR_MODE_ENABLED BIT_4
#define VPO_ENABLED BIT_3
#define VPO_ID_NOT_ACQUIRED BIT_2
#define VPO_PREVIOUSLY_ASSIGNED_ID BIT_1
#define VPO_HARD_ASSIGNED_ID BIT_0
#define ICB_24XX_VERSION 1
typedef struct ql_init_24xx_cb {
/*
* BIT 0 = Hard Assigned Loop ID
* BIT 1 = Enable Fairness
* BIT 2 = Enable Full-Duplex
* BIT 3 = Reserved
* BIT 4 = Target Mode Enable
* BIT 5 = Initiator Mode Disable
* BIT 6 = Reserved
* BIT 7 = Reserved
*
* BIT 8 = Reserved
* BIT 9 = Disable Initial LIP
* BIT 10 = Descending Loop ID Search
* BIT 11 = Previous Assigned Loop ID
* BIT 12 = Reserved
* BIT 13 = Full Login after LIP
* BIT 14 = Node Name Option
* BIT 15-31 = Reserved
*/
/*
* BIT 0 = Operation Mode bit 0
* BIT 1 = Operation Mode bit 1
* BIT 2 = Operation Mode bit 2
* BIT 3 = Operation Mode bit 3
* BIT 4 = Connection Options bit 0
* BIT 5 = Connection Options bit 1
* BIT 6 = Connection Options bit 2
* BIT 7 = Enable Non part on LIHA failure
*
* BIT 8 = Enable Class 2
* BIT 9 = Enable ACK0
* BIT 10 = Reserved
* BIT 11 = Enable FC-SP Security
* BIT 12 = FC Tape Enable
* BIT 13 = Reserved
* BIT 14 = Target PRLI Control
* BIT 15 = Reserved
*
* BIT 16 = Enable Emulated MSIX
* BIT 17 = Reserved
* BIT 18 = Enable Alternate Device Number
* BIT 19 = Enable Alternate Bus Number
* BIT 20 = Enable Translated Address
* BIT 21 = Enable VM Security
* BIT 22 = Enable Interrupt Handshake
* BIT 23 = Enable Multiple Queue
*
* BIT 24 = IOCB Security
* BIT 25 = qos
* BIT 26-31 = Reserved
*/
/*
* BIT 0 = Reserved
* BIT 1 = Soft ID only
* BIT 2 = Reserved
* BIT 3 = Reserved
* BIT 4 = FCP RSP Payload bit 0
* BIT 5 = FCP RSP Payload bit 1
* BIT 6 = Enable Rec Out-of-Order data frame handling
* BIT 7 = Disable Automatic PLOGI on Local Loop
*
* BIT 8 = Reserved
* BIT 9 = Enable Out-of-Order FCP_XFER_RDY relative
* offset handling
* BIT 10 = Reserved
* BIT 11 = Reserved
* BIT 12 = Reserved
* BIT 13 = Data Rate bit 0
* BIT 14 = Data Rate bit 1
* BIT 15 = Data Rate bit 2
*
* BIT 16 = 75-ohm Termination Select
* BIT 17 = Enable Multiple FCFs
* BIT 18 = MAC Addressing Mode
* BIT 19 = MAC Addressing Mode
* BIT 20 = MAC Addressing Mode
* BIT 21 = Ethernet Data Rate
* BIT 22 = Ethernet Data Rate
* BIT 23 = Ethernet Data Rate
*
* BIT 24 = Ethernet Data Rate
* BIT 25 = Ethernet Data Rate
* BIT 26 = Enable Ethernet Header ATIO Queue
* BIT 27 = Enable Ethernet Header Response Queue
* BIT 28 = SPMA Selection
* BIT 29 = SPMA Selection
* BIT 30 = Reserved
* BIT 31 = Reserved
*/
/*
* Multi-ID firmware.
*/
/*
* BIT 1 = Allows mode 2 connection option
*/
/*
* Extended Initialization Control Block
*/
typedef union ql_comb_init_cb {
/*
* ISP IP Initialization Control Block.
* Little endian except where noted.
*/
#define IP_ICB_VERSION 1
typedef struct ql_ip_init_cb {
/*
* LSB BIT 0 = receive_buffer_address_length
* LSB BIT 1 = fast post broadcast received
* LSB BIT 2 = allow out of receive buffers AE
*/
#define IP_ICB_24XX_VERSION 1
typedef struct ql_ip_init_24xx_cb {
/*
* LSB BIT 2 = allow out of receive buffers AE
*/
typedef union ql_comb_ip_init_cb {
/*
* f/w module table
*/
struct fw_table {
};
/*
* aif function table
*/
typedef struct ql_ifunc {
} ql_ifunc_t;
#define QL_MSIX_AIF 0x0
#define QL_MSIX_RSPQ 0x1
/*
* DMA memory type.
*/
typedef enum mem_alloc_type {
/*
* DMA memory alignment type.
*/
typedef enum men_align_type {
/*
* DMA memory object.
*/
typedef struct dma_mem {
void *bp;
} dma_mem_t;
/*
* dma_mem_t memflags defines
*/
#define MFLG_32BIT_ONLY BIT_0
/*
* 24 bit port ID type definition.
*/
typedef union {
struct {
}r;
#if defined(_BIT_FIELDS_LTOH)
struct {
}b;
#elif defined(_BIT_FIELDS_HTOL)
struct {
}b;
#else
#endif
} port_id_t;
/*
* Link list definitions.
*/
typedef struct ql_link {
void *base_address;
} ql_link_t;
typedef struct ql_head {
} ql_head_t;
/*
* This is the per-command structure
*/
typedef struct ql_srb {
/* Command link. */
/* Watchdog link and timer. */
/* FCA and FC Transport data. */
struct ql_adapter_state *ha;
/* unsolicited buffer context. */
/* FCP command. */
/* Request sense. */
/* Device queue pointer. */
/* Command IOCB context. */
void (*iocb)(struct ql_adapter_state *,
struct ql_srb *, void *);
struct cmd_entry *request_ring_ptr;
} ql_srb_t;
/*
* This byte will be used to define flags for the LUN on the target.
* Presently, we have untagged-command as one flag. Others can be
* added later, if needed.
*/
typedef struct tgt_lun_flags {
unused_bits:7;
#define QL_IS_UNTAGGED_PENDING(q, lun_num) \
#define QL_SET_UNTAGGED_PENDING(q, lun_num) \
#define QL_CLEAR_UNTAGGED_PENDING(q, lun_num) \
/*
* Fibre Channel LUN Queue structure
*/
typedef struct ql_lun {
/* Head command link. */
struct ql_target *target_queue;
/* LUN execution throttle. */
} ql_lun_t;
/*
* LUN Queue flags
*/
#define LQF_UNTAGGED_PENDING BIT_0
/*
* Fibre Channel Device Queue structure
*/
typedef struct ql_target {
/* Device queue lock. */
/* Head target command link. */
/* Device link. */
/* Head watchdog link. */
/* Unsolicited buffer IP data. */
/* Port down retry counter. */
/* logout sent state */
/* Data from Port database matches machine type. */
/* LUN context. */
} ql_tgt_t;
/*
* Target Queue flags
*/
#define TQF_TAPE_DEVICE BIT_0
#define TQF_FABRIC_DEVICE BIT_2
#define TQF_INITIATOR_DEVICE BIT_3
#define TQF_RSCN_RCVD BIT_4
#define TQF_NEED_AUTHENTICATION BIT_5
#define TQF_PLOGI_PROGRS BIT_6
#define TQF_IIDMA_NEEDED BIT_7
/*
* Tempoary N_Port information
*/
typedef struct ql_n_port_info {
/*
* iiDMA
*/
#define IIDMA_RATE_1GB 0x0
#define IIDMA_RATE_2GB 0x1
#define IIDMA_RATE_4GB 0x3
#define IIDMA_RATE_8GB 0x4
#define IIDMA_RATE_10GB 0x13
#define IIDMA_RATE_MAX IIDMA_RATE_10GB
/*
* Kernel statistic structure definitions.
*/
typedef struct ql_device_stat {
int logouts_recvd;
int task_mgmt_failures;
int data_ro_mismatches;
int dl_len_mismatches;
typedef struct ql_adapter_24xx_stat {
int version; /* version of this struct */
int lip_count; /* lips forced */
int ncmds; /* outstanding commands */
/*
* Firmware code segment.
*/
#define MAX_RISC_CODE_SEGMENTS 3
typedef struct fw_code {
} ql_fw_code_t;
/* diagnostic els ECHO defines */
/* DUMP state flags. */
#define QL_DUMPING BIT_0
#define QL_DUMP_VALID BIT_1
#define QL_DUMP_UPLOADED BIT_2
typedef struct el_trace_desc {
char *trace_buffer;
/*
* NVRAM cache descriptor.
*/
typedef struct nvram_cache_desc {
void *cache;
/*
* ql attach progress indication
*/
#define QL_SOFT_STATE_ALLOCED BIT_0
#define QL_REGS_MAPPED BIT_1
#define QL_HBA_BUFFER_SETUP BIT_2
#define QL_MUTEX_CV_INITED BIT_3
#define QL_INTR_ADDED BIT_4
#define QL_CONFIG_SPACE_SETUP BIT_5
#define QL_TASK_DAEMON_STARTED BIT_6
#define QL_KSTAT_CREATED BIT_7
#define QL_MINOR_NODE_CREATED BIT_8
#define QL_FCA_TRAN_ALLOCED BIT_9
#define QL_FCA_ATTACH_DONE BIT_10
#define QL_IOMAP_IOBASE_MAPPED BIT_11
#define QL_N_PORT_INFO_CREATED BIT_12
#define QL_DB_IOBASE_MAPPED BIT_13
/* Device queue head list size (based on AL_PA address). */
#define DEVICE_HEAD_LIST_SIZE 0x81
struct legacy_intr_set {
};
/*
* Adapter state structure.
*/
typedef struct ql_adapter_state {
/* Task Daemon context. */
volatile uint32_t task_daemon_flags;
/* Interrupt context. */
volatile uint8_t intr_claimed;
/*
* ISP request queue, response queue, mailbox buffer and
* IP receive queue buffer.
*/
/* ISP request queue context. */
struct cmd_entry *request_ring_bp;
struct cmd_entry *request_ring_ptr;
/* ISP response queue context. */
struct sts_entry *response_ring_bp;
struct sts_entry *response_ring_ptr;
/* Mailbox context. */
volatile uint8_t mailbox_flags;
/* ISP receive buffer queue context. */
struct rcvbuf *rcvbuf_ring_bp;
struct rcvbuf *rcvbuf_ring_ptr;
/* Unsolicited buffer data. */
/* Head of device queue list. */
/* Kernel statistics. */
/* Solaris adapter configuration data */
/* Adapter context */
void (*fcp_cmd)(struct ql_adapter_state *,
ql_srb_t *, void *);
void (*ip_cmd)(struct ql_adapter_state *,
ql_srb_t *, void *);
void (*ms_cmd)(struct ql_adapter_state *,
ql_srb_t *, void *);
/* NVRAM configuration data */
/* Power management context. */
/* sbus card data */
/* XIOCTL context pointer. */
/* AIF (Advanced Interrupt Framework) support */
/* PCI maximum read request override */
/* port manage mutex */
/* f/w dump mutex */
void *ql_dump_ptr;
/* Virtual port context. */
struct ql_adapter_state *pha;
struct ql_adapter_state *vp_next;
/* Tempoary N_Port information */
struct ql_n_port_info *n_port;
void (*els_cmd)(struct ql_adapter_state *,
ql_srb_t *, void *);
/* VLAN ID and MAC address */
/* NetXen context */
struct legacy_intr_set nx_legacy_intr;
/*
* adapter state flags
*/
#define INTERRUPTS_ENABLED BIT_3
#define ABORT_CMDS_LOOP_DOWN_TMO BIT_4
#define POINT_TO_POINT BIT_5
#define IP_ENABLED BIT_6
#define IP_INITIALIZED BIT_7
#define MENLO_LOGIN_OPERATIONAL BIT_8
#define ADAPTER_SUSPENDED BIT_9
#define ADAPTER_TIMER_BUSY BIT_10
#define PARITY_ERROR BIT_11
#define FLASH_ERRLOG_MARKER BIT_12
#define VP_ENABLED BIT_13
#define FDISC_ENABLED BIT_14
#define FUNCTION_1 BIT_15
#define MPI_RESET_NEEDED BIT_16
/*
* task daemon flags
*/
#define TASK_DAEMON_STOP_FLG BIT_0
#define TASK_DAEMON_SLEEPING_FLG BIT_1
#define TASK_DAEMON_ALIVE_FLG BIT_2
#define TASK_DAEMON_IDLE_CHK_FLG BIT_3
#define SUSPENDED_WAKEUP_FLG BIT_4
#define FC_STATE_CHANGE BIT_5
#define NEED_UNSOLICITED_BUFFERS BIT_6
#define RESET_MARKER_NEEDED BIT_7
#define RESET_ACTIVE BIT_8
#define ISP_ABORT_NEEDED BIT_9
#define ABORT_ISP_ACTIVE BIT_10
#define LOOP_RESYNC_NEEDED BIT_11
#define LOOP_RESYNC_ACTIVE BIT_12
#define DRIVER_STALL BIT_14
#define COMMAND_WAIT_NEEDED BIT_15
#define COMMAND_WAIT_ACTIVE BIT_16
#define STATE_ONLINE BIT_17
#define ABORT_QUEUES_NEEDED BIT_18
#define TASK_DAEMON_STALLED_FLG BIT_19
#define TASK_THREAD_CALLED BIT_20
#define FIRMWARE_UP BIT_21
#define LIP_RESET_PENDING BIT_22
#define FIRMWARE_LOADED BIT_23
#define RSCN_UPDATE_NEEDED BIT_24
#define HANDLE_PORT_BYPASS_CHANGE BIT_25
#define PORT_RETRY_NEEDED BIT_26
#define TASK_DAEMON_POWERING_DOWN BIT_27
#define TD_IIDMA_NEEDED BIT_28
#define SEND_PLOGI BIT_29
/*
* Mailbox flags
*/
#define MBX_WANT_FLG BIT_0
#define MBX_BUSY_FLG BIT_1
#define MBX_INTERRUPT BIT_2
/*
* Configuration flags
*/
#define CFG_ENABLE_HARD_ADDRESS BIT_0
#define CFG_ENABLE_64BIT_ADDRESSING BIT_1
#define CFG_ENABLE_LIP_RESET BIT_2
#define CFG_ENABLE_FULL_LIP_LOGIN BIT_3
#define CFG_ENABLE_TARGET_RESET BIT_4
#define CFG_ENABLE_LINK_DOWN_REPORTING BIT_5
#define CFG_ENABLE_FCP_2_SUPPORT BIT_7
#define CFG_MULTI_CHIP_ADAPTER BIT_8
#define CFG_SBUS_CARD BIT_9
#define CFG_CTRL_2300 BIT_10
#define CFG_CTRL_6322 BIT_11
#define CFG_CTRL_2200 BIT_12
#define CFG_CTRL_2422 BIT_13
#define CFG_CTRL_25XX BIT_14
#define CFG_ENABLE_EXTENDED_LOGGING BIT_15
#define CFG_DISABLE_RISC_CODE_LOAD BIT_16
#define CFG_SET_CACHE_LINE_SIZE_1 BIT_17
#define CFG_CTRL_MENLO BIT_18
#define CFG_EXT_FW_INTERFACE BIT_19
#define CFG_LOAD_FLASH_FW BIT_20
#define CFG_DUMP_MAILBOX_TIMEOUT BIT_21
#define CFG_DUMP_ISP_SYSTEM_ERROR BIT_22
#define CFG_DUMP_LOOP_OFFLINE_TIMEOUT BIT_24
#define CFG_ENABLE_FWEXTTRACE BIT_25
#define CFG_ENABLE_FWFCETRACE BIT_26
#define CFG_FW_MISMATCH BIT_27
#define CFG_CTRL_81XX BIT_28
#define CFG_CTRL_8021 BIT_29
#define CFG_FAST_TIMEOUT BIT_30
#define CFG_LR_SUPPORT BIT_31
/*
* Interrupt configuration flags
*/
#define IFLG_INTR_LEGACY BIT_0
#define IFLG_INTR_FIXED BIT_1
#define IFLG_INTR_MSI BIT_2
#define IFLG_INTR_MSIX BIT_3
/*
* Macros to help code, maintain, etc.
*/
/* Little endian machine correction defines. */
#ifdef _LITTLE_ENDIAN
#define LITTLE_ENDIAN_16(x)
#define LITTLE_ENDIAN_24(x)
#define LITTLE_ENDIAN_32(x)
#define LITTLE_ENDIAN_64(x)
#endif /* _LITTLE_ENDIAN */
/* Big endian machine correction defines. */
#ifdef _BIG_ENDIAN
#define BIG_ENDIAN_16(x)
#define BIG_ENDIAN_24(x)
#define BIG_ENDIAN_32(x)
#define BIG_ENDIAN_64(x)
#endif /* _BIG_ENDIAN */
#define LOCAL_LOOP_ID(x) (x <= LAST_LOCAL_LOOP_ID)
#define FABRIC_LOOP_ID(x) (x == FL_PORT_LOOP_ID || \
#define SNS_LOOP_ID(x) (x >= SNS_FIRST_LOOP_ID && \
x <= SNS_LAST_LOOP_ID)
#define BROADCAST_LOOP_ID(x) (x == IP_BROADCAST_LOOP_ID)
FABRIC_LOOP_ID(x) || BROADCAST_LOOP_ID(x))
#define VALID_N_PORT_HDL(x) (x <= LAST_N_PORT_HDL || \
(x >= SNS_24XX_HDL && x <= BROADCAST_24XX_HDL))
VALID_N_PORT_HDL(x) : VALID_LOOP_ID(x))
(x > LAST_N_PORT_HDL && x <= FL_PORT_24XX_HDL) : \
(x >= FL_PORT_LOOP_ID && x <= SIMPLE_NAME_SERVER_LOOP_ID))
#define QL_TASK_PENDING(ha) ( \
#define QL_DAEMON_NOT_ACTIVE(ha) ( \
#define QL_DAEMON_SUSPENDED(ha) (\
#define QL_MAX_FRAME_SIZE(ha) \
/*
* Locking Macro Definitions
*/
/*
*/
#define QL_PM_CS_REG 0x48
/*
* ql component
*/
#define QL_POWER_COMPONENT 0
typedef struct ql_config_space {
#ifdef USE_DDI_INTERFACES
#else /* USE_DDI_INTERFACES */
#endif /* USE_DDI_INTERFACES */
#define QL_IS_SET(x, y) (((x) & (y)) == (y))
/*
* QL local function return status codes
*/
#define QL_SUCCESS 0x4000
#define QL_INVALID_COMMAND 0x4001
#define QL_INTERFACE_ERROR 0x4002
#define QL_TEST_FAILED 0x4003
#define QL_COMMAND_ERROR 0x4005
#define QL_PARAMETER_ERROR 0x4006
#define QL_PORT_ID_USED 0x4007
#define QL_LOOP_ID_USED 0x4008
#define QL_ALL_IDS_IN_USE 0x4009
#define QL_NOT_LOGGED_IN 0x400A
#define QL_LOOP_DOWN 0x400B
#define QL_LOOP_BACK_ERROR 0x400C
#define QL_CHECKSUM_ERROR 0x4010
#define QL_CONSUMED 0x4011
#define QL_FUNCTION_TIMEOUT 0x100
#define QL_FUNCTION_PARAMETER_ERROR 0x101
#define QL_FUNCTION_FAILED 0x102
#define QL_MEMORY_ALLOC_FAILED 0x103
#define QL_FABRIC_NOT_INITIALIZED 0x104
#define QL_LOCK_TIMEOUT 0x105
#define QL_ABORTED 0x106
#define QL_FUNCTION_SUSPENDED 0x107
#define QL_END_OF_DATA 0x108
#define QL_IP_UNSUPPORTED 0x109
#define QL_PM_ERROR 0x10a
#define QL_DATA_EXISTS 0x10b
#define QL_NOT_SUPPORTED 0x10c
#define QL_MEMORY_FULL 0x10d
#define QL_FW_NOT_SUPPORTED 0x10e
#define QL_FWMODLOAD_FAILED 0x10f
#define QL_FWSYM_NOT_FOUND 0x110
#define QL_LOGIN_NOT_SUPPORTED 0x111
/*
* SBus card FPGA register offsets.
*/
#define FPGA_CONF 0x100
#define FPGA_EEPROM_LOADDR 0x102
#define FPGA_EEPROM_HIADDR 0x104
#define FPGA_EEPROM_DATA 0x106
#define FPGA_REVISION 0x108
#define SBUS_FLASH_WRITE_ENABLE 0x0080
#define QL_SBUS_FCODE_SIZE 0x30000
#define QL_FCODE_OFFSET 0
#define QL_FPGA_SIZE 0x40000
#define QL_FPGA_OFFSET 0x40000
/*
* Structure used to associate cmds with strings which describe them.
*/
typedef struct cmd_table_entry {
char *string;
} cmd_table_t;
/*
* ELS command table initializer
*/
#define ELS_CMD_TABLE() \
{ \
{LA_ELS_RJT, "LA_ELS_RJT"}, \
{LA_ELS_ACC, "LA_ELS_ACC"}, \
{LA_ELS_PLOGI, "LA_ELS_PLOGI"}, \
{LA_ELS_PDISC, "LA_ELS_PDISC"}, \
{LA_ELS_FLOGI, "LA_ELS_FLOGI"}, \
{LA_ELS_FDISC, "LA_ELS_FDISC"}, \
{LA_ELS_LOGO, "LA_ELS_LOGO"}, \
{LA_ELS_PRLI, "LA_ELS_PRLI"}, \
{LA_ELS_PRLO, "LA_ELS_PRLO"}, \
{LA_ELS_ADISC, "LA_ELS_ADISC"}, \
{LA_ELS_LINIT, "LA_ELS_LINIT"}, \
{LA_ELS_LPC, "LA_ELS_LPC"}, \
{LA_ELS_LSTS, "LA_ELS_LSTS"}, \
{LA_ELS_SCR, "LA_ELS_SCR"}, \
{LA_ELS_RSCN, "LA_ELS_RSCN"}, \
{LA_ELS_FARP_REQ, "LA_ELS_FARP_REQ"}, \
{LA_ELS_FARP_REPLY, "LA_ELS_FARP_REPLY"}, \
{LA_ELS_RLS, "LA_ELS_RLS"}, \
{LA_ELS_RNID, "LA_ELS_RNID"}, \
}
/*
* ELS Passthru IOCB data segment descriptor.
*/
typedef struct data_seg_desc {
/*
* ELS descriptor used to abstract the hosts fibre channel packet
* from the ISP ELS code.
*/
typedef struct els_desc {
typedef struct prli_svc_pram_resp_page {
/*
* PRLI accept Service Parameter Page Word 3
*/
#define PRLI_W3_OBSOLETE_BIT_2 BIT_2
#define PRLI_W3_OBSOLETE_BIT_3 BIT_3
#define PRLI_W3_TARGET_FUNCTION BIT_4
#define PRLI_W3_INITIATOR_FUNCTION BIT_5
#define PRLI_W3_DATA_OVERLAY_ALLOWED BIT_6
#define PRLI_W3_CONFIRMED_COMP_ALLOWED BIT_7
#define PRLI_W3_RETRY BIT_8
#define PRLI_W3_TASK_RETRY_ID_REQUESTED BIT_9
typedef struct prli_acc_resp {
struct prli_svc_pram_resp_page svc_params;
#define EL_TRACE_BUF_SIZE 8192
/*
* Global Data in ql_api.c source file.
*/
extern void *ql_state; /* for soft state routine */
extern uint32_t ql_os_release_level;
extern kmutex_t ql_global_mutex;
extern kmutex_t ql_global_hw_mutex;
extern kmutex_t ql_global_el_mutex;
extern uint8_t ql_ip_fast_post_count;
extern uint32_t ql_ip_buffer_count;
extern uint32_t ql_ip_low_water;
extern uint8_t ql_alpa_to_index[];
extern uint32_t ql_gfru_hba_index;
extern uint32_t ql_enable_ets;
extern uint16_t ql_osc_wait_count;
/*
* Global Function Prototypes in ql_api.c source file.
*/
void ql_setup_fruinfo(ql_adapter_state_t *);
uint32_t);
int ql_binary_fw_dump(ql_adapter_state_t *, int);
int ql_24xx_flash_id(ql_adapter_state_t *);
void ql_flash_disable(ql_adapter_state_t *);
void ql_flash_enable(ql_adapter_state_t *);
int ql_erase_flash(ql_adapter_state_t *, int);
void ql_cmd_wait(ql_adapter_state_t *);
void ql_loop_online(ql_adapter_state_t *);
void ql_restart_driver(ql_adapter_state_t *);
void ql_24xx_protect_flash(ql_adapter_state_t *);
char *els_cmd_text(int);
char *mbx_cmd_text(int);
char *cmd_text(cmd_table_t *, int);
#ifdef __cplusplus
}
#endif
#endif /* _QL_API_H */