oce_hw.h revision 3abb112f8485b33b6b9b52b340bede0a333c10bf
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/* Copyright © 2003-2011 Emulex. All rights reserved. */
/*
* Header file containing the command structures for Hardware
*/
#ifndef _OCE_HW_H_
#define _OCE_HW_H_
#ifdef __cplusplus
extern "C" {
#endif
#pragma pack(1)
#define OC_CNA_GEN2 0x2
#define OC_CNA_GEN3 0x3
#define DEVID_TIGERSHARK 0x700
#define DEVID_TOMCAT 0x710
/* PCI CSR offsets */
#define PCICFG_SEMAPHORE 0xbc
#define PCICFG_SOFT_RESET 0x5c
#define PCICFG_UE_STATUS_HI_MASK 0xac
#define PCICFG_UE_STATUS_LO_MASK 0xa8
#define PCICFG_ONLINE0 0xb0
#define PCICFG_ONLINE1 0xb4
#define INTR_EN 0x20000000
/* CSR register offsets */
#define MPU_EP_CONTROL 0
#define MPU_EP_SEMAPHORE 0xac
#define PCICFG_INTR_CTRL 0xfc
#define HOSTINTR_PFUNC_SHIFT 26
#define HOSTINTR_PFUNC_MASK 7
/* POST status reg struct */
#define POST_STAGE_POWER_ON_RESET 0x00
#define POST_STAGE_AWAITING_HOST_RDY 0x01
#define POST_STAGE_HOST_RDY 0x02
#define POST_STAGE_CHIP_RESET 0x03
#define POST_STAGE_ARMFW_READY 0xc000
#define POST_STAGE_ARMFW_UE 0xf000
/* DOORBELL registers */
#define PD_RXULP_DB 0x0100
#define PD_TXULP_DB 0x0060
#define DB_RQ_ID_MASK 0x3FF
#define PD_CQ_DB 0x0120
#define PD_MPU_MBOX_DB 0x0160
#define PD_MQ_DB 0x0140
/* EQE completion types */
#define EQ_MINOR_CODE_COMPLETION 0x00
#define EQ_MINOR_CODE_OTHER 0x01
#define EQ_MAJOR_CODE_COMPLETION 0x00
/* Link Status field values */
#define PHY_LINK_FAULT_NONE 0x0
#define PHY_LINK_FAULT_LOCAL 0x01
#define PHY_LINK_FAULT_REMOTE 0x02
#define PHY_LINK_DUPLEX_NONE 0x0
#define PHY_LINK_DUPLEX_HALF 0x1
#define PHY_LINK_DUPLEX_FULL 0x2
/* Hardware Address types */
/* CREATE_IFACE capability and cap_en flags */
#define MBX_RX_IFACE_FLAGS_RSS 0x4
#define MBX_RX_IFACE_FLAGS_PROMISCUOUS 0x8
#define MBX_RX_IFACE_FLAGS_BROADCAST 0x10
#define MBX_RX_IFACE_FLAGS_UNTAGGED 0x20
#define MBX_RX_IFACE_FLAGS_ULP 0x40
#define MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS 0x80
#define MBX_RX_IFACE_FLAGS_VLAN 0x100
#define MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS 0x200
#define MBX_RX_IFACE_FLAGS_PASS_L2 0x400
#define MBX_RX_IFACE_FLAGS_PASS_L3L4 0x800
#define MBX_DB_READY_BIT 0x1
#define MBX_DB_HI_BIT 0x2
#define ASYNC_EVENT_CODE_LINK_STATE 0x1
#define ASYNC_EVENT_LINK_UP 0x1
#define ASYNC_EVENT_LINK_DOWN 0x0
/* port link_status */
#define ASYNC_EVENT_LOGICAL 0x02
/* Logical Link Status */
#define NTWK_LOGICAL_LINK_DOWN 0
#define NTWK_LOGICAL_LINK_UP 1
/* Rx filter bits */
#define NTWK_RX_FILTER_IP_CKSUM 0x1
#define NTWK_RX_FILTER_TCP_CKSUM 0x2
#define NTWK_RX_FILTER_UDP_CKSUM 0x4
#define NTWK_RX_FILTER_STRIP_CRC 0x8
/* max SGE per mbx */
#define MAX_MBX_SGE 19
/* physical address structure to be used in MBX */
struct phys_addr {
/* dw0 */
/* dw1 */
};
typedef union pcicfg_intr_ctl_u {
struct {
#ifdef _BIG_ENDIAN
#else
#endif
} bits;
typedef union pcicfg_semaphore_u {
struct {
#ifdef _BIG_ENDIAN
#else
#endif
}bits;
typedef union pcicfg_soft_reset_u {
struct {
#ifdef _BIG_ENDIAN
#else
#endif
}bits;
typedef union pcicfg_online1_u {
struct {
#ifdef _BIG_ENDIAN
#else
#endif
}bits;
typedef union mpu_ep_semaphore_u {
struct {
#ifdef _BIG_ENDIAN
#else
#endif
}bits;
typedef union mpu_ep_control_u {
struct {
#ifdef _BIG_ENDIAN
#else
#endif
}bits;
/* RX doorbell */
typedef union pd_rxulp_db_u {
struct {
#ifdef _BIG_ENDIAN
#else
#endif
}bits;
/* TX doorbell */
typedef union pd_txulp_db_u {
struct {
#ifdef _BIG_ENDIAN
#else
#endif
}bits;
/* CQ doorbell */
typedef union cq_db_u {
struct {
#ifdef _BIG_ENDIAN
#else
#endif
}bits;
}cq_db_t;
/* EQ doorbell */
typedef union eq_db_u {
struct {
#ifdef _BIG_ENDIAN
#else
#endif
}bits;
}eq_db_t;
/* bootstrap mbox doorbell */
typedef union pd_mpu_mbox_db_u {
struct {
#ifdef _BIG_ENDIAN
#else
#endif
}bits;
/* MQ ring doorbell */
typedef union pd_mq_db_u {
struct {
#ifdef _BIG_ENDIAN
#else
#endif
}bits;
/*
* Event Queue Entry
*/
struct oce_eqe {
union {
struct {
#ifdef _BIG_ENDIAN
#else
#endif
}s;
}u0;
};
/* MQ scatter gather entry. Array of these make an SGL */
struct oce_mq_sge {
};
/*
* payload can contain an SGL or an embedded array of upto 59 dwords
*/
struct oce_mbx_payload {
union {
union {
}u1;
}u0;
};
/*
* MQ MBX structure
*/
struct oce_mbx {
union {
struct {
#ifdef _BIG_ENDIAN
#else
#endif
}s;
}u0;
struct oce_mbx_payload payload;
};
/* completion queue entry for MQ */
struct oce_mq_cqe {
union {
struct {
#ifdef _BIG_ENDIAN
/* dw0 */
/* dw1 dw2 */
/* dw3 */
#else
/* dw0 */
/* dw1 dw2 */
/* dw3 */
#endif
}s;
}u0;
};
struct oce_async_cqe_link_state {
union {
struct {
#ifdef _BIG_ENDIAN
/* dw0 */
/* dw1 */
/* dw2 */
/* dw3 */
#else
/* dw0 */
/* dw1 */
/* dw2 */
/* dw3 */
#endif
}s;
}u0;
};
/* MQ mailbox structure */
struct oce_bmbx {
struct oce_mq_cqe cqe;
};
/* ---[ MBXs start here ]---------------------------------------------- */
/* MBXs sub system codes */
enum {
MBX_SUBSYSTEM_RSVD = 0,
MBX_SUBSYSTEM_COMMON = 1,
MBX_SUBSYSTEM_NIC = 3,
MBX_SUBSYSTEM_TOE = 4,
MBX_SUBSYSTEM_RDMA = 10,
MBX_SUBSYSTEM_LOWLEVEL = 11,
MBX_SUBSYSTEM_LRO = 13,
IOCBMBX_SUBSYSTEM_DCBX = 15,
IOCBMBX_SUBSYSTEM_DIAG = 16,
};
/* common ioctl opcodes */
enum {
OPCODE_CREATE_COMMON_CQ = 12,
OPCODE_CREATE_COMMON_EQ = 13,
OPCODE_CREATE_COMMON_MQ = 21,
OPCODE_COMMON_GET_QOS = 27,
OPCODE_COMMON_SET_QOS = 28,
OPCODE_COMMON_NOP = 33,
OPCODE_COMMON_GET_FAT = 40,
OPCODE_COMMON_RED_CONFIG = 49,
OPCODE_DESTROY_COMMON_MQ = 53,
OPCODE_DESTROY_COMMON_CQ = 54,
OPCODE_DESTROY_COMMON_EQ = 55,
};
/* common ioctl header */
struct mbx_hdr {
union {
struct {
#ifdef _BIG_ENDIAN
#else
#endif
}req;
struct {
/* dw 0 */
/* dw 1 */
}rsp;
}u0;
};
#define OCE_BMBX_RHDR_SZ 20
#define OCE_MBX_RRHDR_SZ sizeof (struct mbx_hdr)
/* [05] OPCODE_QUERY_COMMON_LINK_STATUS */
struct mbx_query_common_link_status {
union {
struct {
}req;
struct {
/* dw 0 */
/* dw 1 */
}rsp;
}params;
};
/* [57] OPCODE_SET_COMMON_LINK_SPEED */
struct mbx_set_common_link_speed {
union {
struct {
#ifdef _BIG_ENDIAN
#else
#endif
}req;
struct {
}rsp;
}params;
};
struct mac_address_format {
};
/* [01] OPCODE_QUERY_COMMON_IFACE_MAC */
struct mbx_query_common_iface_mac {
union {
struct {
#ifdef _BIG_ENDIAN
#else
#endif
}req;
struct {
struct mac_address_format mac;
}rsp;
}params;
};
/* [02] OPCODE_SET_COMMON_IFACE_MAC */
struct mbx_set_common_iface_mac {
union {
struct {
#ifdef _BIG_ENDIAN
/* dw 0 */
#else
/* dw 0 */
#endif
/* dw 1 */
struct mac_address_format mac;
}req;
struct {
}rsp;
}params;
};
/* [03] OPCODE_SET_COMMON_IFACE_MULTICAST */
struct mbx_set_common_iface_multicast {
union {
struct {
/* dw 0 */
/* dw 1-48 */
struct {
} mac[32];
}req;
struct {
}rsp;
}params;
};
struct qinq_vlan {
#ifdef _BIG_ENDIAN
#else
#endif
};
struct normal_vlan {
};
struct ntwk_if_vlan_tag {
union {
struct normal_vlan normal;
}u0;
};
/* [50] OPCODE_CREATE_COMMON_IFACE */
struct mbx_create_common_iface {
union {
struct {
struct ntwk_if_vlan_tag vlan_tag;
}req;
struct {
}rsp;
}params;
};
/* [51] OPCODE_DESTROY_COMMON_IFACE */
struct mbx_destroy_common_iface {
union {
struct {
}req;
struct {
}rsp;
}params;
};
/* event queue context structure */
struct oce_eq_ctx {
#ifdef _BIG_ENDIAN
/* dw0 */
/* dw1 */
/* dw2 */
/* dw 3 */
#else
/* dw0 */
/* dw1 */
/* dw2 */
/* dw3 */
#endif
};
/* [13] OPCODE_CREATE_COMMON_EQ */
struct mbx_create_common_eq {
union {
struct {
#ifdef _BIG_ENDIAN
#else
#endif
struct oce_eq_ctx eq_ctx;
}req;
struct {
}rsp;
}params;
};
/* [55] OPCODE_DESTROY_COMMON_EQ */
struct mbx_destroy_common_eq {
union {
struct {
#ifdef _BIG_ENDIAN
#else
#endif
}req;
struct {
}rsp;
}params;
};
struct oce_cq_ctx {
#ifdef _BIG_ENDIAN
/* dw0 */
/* dw1 */
/* dw2 */
#else
/* dw0 */
/* dw1 */
/* dw2 */
#endif
};
/* [12] OPCODE_CREATE_COMMON_CQ */
struct mbx_create_common_cq {
union {
struct {
#ifdef _BIG_ENDIAN
#else
#endif
struct oce_cq_ctx cq_ctx;
}req;
struct {
}rsp;
}params;
};
/* [54] OPCODE_DESTROY_COMMON_CQ */
struct mbx_destroy_common_cq {
union {
struct {
#ifdef _BIG_ENDIAN
#else
#endif
}req;
struct {
}rsp;
}params;
};
struct mq_ring_ctx {
union {
struct {
#ifdef _BIG_ENDIAN
/* dw 0 */
/* dw1 */
/* dw 2 */
#else
/* dw 0 */
/* dw1 */
/* dw 2 */
#endif
/* dw3 */
}s;
}u0;
};
/* [21] OPCODE_CREATE_COMMON_MQ */
struct mbx_create_common_mq {
union {
struct {
#ifdef _BIG_ENDIAN
#else
#endif
struct mq_ring_ctx context;
}req;
struct {
}rsp;
}params;
};
/* [53] OPCODE_DESTROY_COMMON_MQ */
struct mbx_destroy_common_mq {
union {
struct {
#ifdef _BIG_ENDIAN
#else
#endif
}req;
struct {
}rsp;
}params;
};
/* [35] OPCODE_GET_COMMON_ FW_VERSION */
struct mbx_get_common_fw_version {
union {
struct {
}req;
struct {
}rsp;
}params;
};
/* [52] OPCODE_COMMON_CEV_MODIFY_MSI_MESSAGES */
struct mbx_common_cev_modify_msi_messages {
union {
struct {
}req;
struct {
}rsp;
}params;
};
/* [36] OPCODE_SET_COMMON_FLOW_CONTROL */
/* [37] OPCODE_GET_COMMON_FLOW_CONTROL */
struct mbx_common_get_set_flow_control {
#ifdef _BIG_ENDIAN
#else
#endif
};
enum e_flash_opcode {
};
/* [06] OPCODE_READ_COMMON_FLASHROM */
/* [07] OPCODE_WRITE_COMMON_FLASHROM */
struct mbx_common_read_write_flashrom {
};
/* ULP MODE SUPPORTED */
enum {
ULP_TOE_MODE = 0x1,
ULP_NIC_MODE = 0x2,
ULP_RDMA_MODE = 0x4,
ULP_ISCSI_INI_MODE = 0x10,
ULP_ISCSI_TGT_MODE = 0x20,
ULP_FCOE_INI_MODE = 0x40,
ULP_FCOE_TGT_MODE = 0x80,
ULP_DAL_MODE = 0x100,
ULP_LRO_MODE = 0x200
};
/* Function Mode Supported */
enum {
};
struct mbx_common_query_fw_config {
union {
struct {
}req;
struct {
struct {
} ulp[2];
}rsp;
}params;
};
struct mbx_common_config_vlan {
union {
struct {
#ifdef _BIG_ENDIAN
#else
#endif
union {
}tags;
}req;
struct {
}rsp;
}params;
};
/* [34] OPCODE_COMMON_NTWK_RX_FILTER */
struct mbx_set_common_ntwk_rx_filter {
struct {
}mac[32];
};
/* [41] OPCODE_MODIFY_COMMON_EQ_DELAY */
struct mbx_modify_common_eq_delay {
union {
struct {
struct {
}delay[8];
}req;
struct {
}rsp;
}params;
};
/* [59] OPCODE_ADD_COMMON_IFACE_MAC */
struct mbx_add_common_iface_mac {
union {
struct {
}req;
struct {
}rsp;
} params;
};
/* [60] OPCODE_DEL_COMMON_IFACE_MAC */
struct mbx_del_common_iface_mac {
union {
struct {
}req;
struct {
}rsp;
} params;
};
/* [8] OPCODE_QUERY_COMMON_MAX_MBX_BUFFER_SIZE */
struct mbx_query_common_max_mbx_buffer_size {
struct {
} rsp;
};
/* [61] OPCODE_COMMON_FUNCTION_RESET */
struct ioctl_common_function_reset {
};
/* [80] OPCODE_COMMON_FUNCTION_LINK_CONFIG */
struct mbx_common_func_link_cfg {
union {
struct {
}req;
struct {
}rsp;
} params;
};
#pragma pack()
#ifdef __cplusplus
}
#endif
#endif /* _OCE_HW_H_ */