emlxs_mbox.h revision 6a573d82e26abdedeb701fcdd5b5461b2fa0da40
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2010 Emulex. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _EMLXS_MBOX_H
#define _EMLXS_MBOX_H
#ifdef __cplusplus
extern "C" {
#endif
/* SLI 2/3 Mailbox defines */
#define MBOX_SIZE 256
#define MBOX_EXTENSION_OFFSET MBOX_SIZE
#ifdef MBOX_EXT_SUPPORT
#define MBOX_EXTENSION_SIZE 1024
#else
#define MBOX_EXTENSION_SIZE 0
#endif /* MBOX_EXT_SUPPORT */
/* ==== Mailbox Commands ==== */
#define MBX_LOAD_SM 0x01
#define MBX_READ_NV 0x02
#define MBX_WRITE_NV 0x03
#define MBX_RUN_BIU_DIAG 0x04
#define MBX_INIT_LINK 0x05
#define MBX_DOWN_LINK 0x06
#define MBX_CONFIG_LINK 0x07
#define MBX_PART_SLIM 0x08
#define MBX_CONFIG_RING 0x09
#define MBX_RESET_RING 0x0A
#define MBX_READ_CONFIG 0x0B
#define MBX_READ_RCONFIG 0x0C
#define MBX_READ_SPARM 0x0D
#define MBX_READ_STATUS 0x0E
#define MBX_READ_RPI 0x0F
#define MBX_READ_XRI 0x10
#define MBX_READ_REV 0x11
#define MBX_READ_LNK_STAT 0x12
#define MBX_REG_LOGIN 0x13
#define MBX_READ_LA 0x15
#define MBX_CLEAR_LA 0x16
#define MBX_DUMP_MEMORY 0x17
#define MBX_DUMP_CONTEXT 0x18
#define MBX_RUN_DIAGS 0x19
#define MBX_RESTART 0x1A
#define MBX_UPDATE_CFG 0x1B
#define MBX_DOWN_LOAD 0x1C
#define MBX_DEL_LD_ENTRY 0x1D
#define MBX_RUN_PROGRAM 0x1E
#define MBX_SET_MASK 0x20
#define MBX_SET_VARIABLE 0x21
#define MBX_UNREG_D_ID 0x23
#define MBX_KILL_BOARD 0x24
#define MBX_CONFIG_FARP 0x25
#define MBX_BEACON 0x2A
#define MBX_READ_VPI 0x2B
#define MBX_CONFIG_MSIX 0x30
#define MBX_HEARTBEAT 0x31
#define MBX_WRITE_VPARMS 0x32
#define MBX_ASYNC_EVENT 0x33
#define MBX_READ_EVENT_LOG_STATUS 0x37
#define MBX_READ_EVENT_LOG 0x38
#define MBX_WRITE_EVENT_LOG 0x39
#define MBX_NV_LOG 0x3A
#define MBX_PORT_CAPABILITIES 0x3B
#define MBX_IOV_CONTROL 0x3C
#define MBX_IOV_MBX 0x3D
#define MBX_LOAD_AREA 0x81
#define MBX_RUN_BIU_DIAG64 0x84
#define MBX_GET_DEBUG 0x86
#define MBX_CONFIG_PORT 0x88
#define MBX_READ_SPARM64 0x8D
#define MBX_READ_RPI64 0x8F
#define MBX_CONFIG_MSI 0x90
#define MBX_READ_LA64 0x95
#define MBX_FLASH_WR_ULA 0x98
#define MBX_SET_DEBUG 0x99
#define MBX_SLI_CONFIG 0x9B
#define MBX_LOAD_EXP_ROM 0x9C
#define MBX_REQUEST_FEATURES 0x9D
#define MBX_RESUME_RPI 0x9E
#define MBX_REG_VFI 0x9F
#define MBX_REG_FCFI 0xA0
#define MBX_UNREG_VFI 0xA1
#define MBX_UNREG_FCFI 0xA2
#define MBX_INIT_VFI 0xA3
#define MBX_INIT_VPI 0xA4
#define MBX_ACCESS_VDATA 0xA5
#define MBX_MAX_CMDS 0xA6
/*
* Define Status
*/
#define MBX_SUCCESS 0x0
#define MBX_FAILURE 0x1
#define MBXERR_NUM_IOCBS 0x2
#define MBXERR_IOCBS_EXCEEDED 0x3
#define MBXERR_BAD_RING_NUMBER 0x4
#define MBXERR_MASK_ENTRIES_RANGE 0x5
#define MBXERR_MASKS_EXCEEDED 0x6
#define MBXERR_BAD_PROFILE 0x7
#define MBXERR_BAD_DEF_CLASS 0x8
#define MBXERR_BAD_MAX_RESPONDER 0x9
#define MBXERR_BAD_MAX_ORIGINATOR 0xA
#define MBXERR_RPI_REGISTERED 0xB
#define MBXERR_RPI_FULL 0xC
#define MBXERR_NO_RESOURCES 0xD
#define MBXERR_BAD_RCV_LENGTH 0xE
#define MBXERR_DMA_ERROR 0xF
#define MBXERR_NOT_SUPPORTED 0x10
#define MBXERR_UNSUPPORTED_FEATURE 0x11
#define MBXERR_UNKNOWN_COMMAND 0x12
/* Driver special codes */
#define MBX_NONEMBED_ERROR 0xF9
#define MBX_OVERTEMP_ERROR 0xFA
#define MBX_HARDWARE_ERROR 0xFB
#define MBX_DRVR_ERROR 0xFC
#define MBX_BUSY 0xFD
#define MBX_TIMEOUT 0xFE
#define MBX_NOT_FINISHED 0xFF
/*
* flags for EMLXS_SLI_ISSUE_MBOX_CMD()
*/
/* then return */
/* wakes thread up */
/*
* Begin Structure Definitions for Mailbox Commands
*/
typedef struct revcompat
{
#ifdef EMLXS_BIG_ENDIAN
/* 0 if none */
#endif
#ifdef EMLXS_LITTLE_ENDIAN
/* 0 if none */
#endif
} REVCOMPAT;
typedef struct id_word
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
union
{
} un;
} PROG_ID;
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} RR_REG;
/* Structure used for a HBQ entry */
typedef struct
{
union UN_TAG
{
uint32_t w;
struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} ext;
} unt;
} HBQE_t;
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} HBQ_MASK;
#define EMLXS_MAX_HBQ_BUFFERS 4096
typedef struct
{
/* port array */
/* for LogEntry */
/* 7=logentry */
/* Ring0=b0001, ring2=b0100 */
/* of HBQs[] */
/* use */
/* from Port */
/* in list */
union
{
struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} profile2;
struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} profile3;
struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} profile5;
} profiles;
} HBQ_INIT_t;
/* Structure for MB Command LOAD_SM and DOWN_LOAD */
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#define DL_FROM_BDE 0 /* method */
#define DL_FROM_SLIM 1
#define PROGRAM_FLASH 0 /* erase_or_prog */
#define ERASE_FLASH 1
union
{
} un;
} LOAD_SM_VAR;
/* Structure for MB Command READ_NVPARM (02) */
/* Good for SLI2/3 and SLI4 */
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} READ_NV_VAR;
/* Structure for MB Command WRITE_NVPARMS (03) */
/* Good for SLI2/3 and SLI4 */
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} WRITE_NV_VAR;
/* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
/* Good for SLI2/3 and SLI4 */
typedef struct
{
union
{
struct
{
} s2;
} un;
} BIU_DIAG_VAR;
/* Structure for MB Command INIT_LINK (05) */
/* Good for SLI2/3 and SLI4 */
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
/* Reset to */
#endif
#ifdef EMLXS_LITTLE_ENDIAN
/* Reset to */
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/* ENDEC loopback */
#define LINK_SPEED_AUTO 0 /* Auto selection */
/* Structure for MB Command DOWN_LINK (06) */
/* Good for SLI2/3 and SLI4 */
typedef struct
{
/* Structure for MB Command CONFIG_LINK (07) */
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} CONFIG_LINK;
/* Structure for MB Command PART_SLIM (08) */
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/* Structure for MB Command CONFIG_RING (09) */
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/* Structure for MB Command RESET_RING (10) */
typedef struct
{
/* Structure for MB Command READ_CONFIG (11) */
/* Good for SLI2/3 only */
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/* Defines for topology (defined previously) */
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#define LMT_1GB_CAPABLE 0x0004
#define LMT_2GB_CAPABLE 0x0008
#define LMT_4GB_CAPABLE 0x0040
#define LMT_8GB_CAPABLE 0x0080
#define LMT_10GB_CAPABLE 0x0100
/* E2E supported on adapters >= 8GB */
/* Structure for MB Command READ_CONFIG(0x11) */
/* Good for SLI4 only */
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/* Structure for MB Command READ_RCONFIG (12) */
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/* Structure for MB Command READ_SPARM (13) */
/* Structure for MB Command READ_SPARM64 (0x8D) */
/* Good for SLI2/3 and SLI4 */
typedef struct
{
union
{
/* structure */
} un;
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/* Structure for MB Command READ_STATUS (14) */
/* Good for SLI2/3 and SLI4 */
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/* Structure for MB Command READ_RPI (15) */
/* Structure for MB Command READ_RPI64 (0x8F) */
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
union
{
} un;
} READ_RPI_VAR;
/* Structure for MB Command READ_XRI (16) */
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} READ_XRI_VAR;
/* Structure for MB Command READ_REV (17) */
/* Good for SLI2/3 only */
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
union
{
struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} b;
} un;
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} READ_REV_VAR;
/* Structure for MB Command READ_REV (17) */
/* Good for SLI4 only */
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#define EMLXS_DCBX_MODE_CIN 0 /* Mapped to nonFIP mode */
/* Structure for MB Command READ_LINK_STAT (18) */
/* Good for SLI2/3 and SLI4 */
typedef struct
{
} READ_LNK_VAR;
/* Structure for MB Command REG_LOGIN (19) */
/* Structure for MB Command REG_LOGIN64 (0x93) */
/* Structure for MB Command REG_RPI (0x93) */
/* Good for SLI2/3 and SLI4 */
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
union
{
} un;
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/* Word 30 contents for REG_LOGIN */
typedef union
{
struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} f;
} REG_WD30;
/* Structure for MB Command UNREG_LOGIN (0x14) - SLI2/3 */
/* Structure for MB Command UNREG_RPI (0x14) - SLI4 */
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/* Structure for MB Command REG_FCFI (0xA0) */
/* Good for SLI4 only */
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} REG_FCFI_VAR;
/* Defines for mam */
/* Structure for MB Command UNREG_FCFI (0xA2) */
/* Good for SLI4 only */
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/* Structure for MB Command RESUME_RPI (0x9E) */
/* Good for SLI4 only */
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/* Structure for MB Command UNREG_D_ID (0x23) */
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/* Structure for MB Command READ_LA (21) */
/* Structure for MB Command READ_LA64 (0x95) */
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/* lipType */
/* topology */
union
{
/* 128 byte buffer to store */
/* the LILP AL_PA position */
/* map into */
} un;
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} READ_LA_VAR;
/* Structure for MB Command CLEAR_LA (22) */
typedef struct
{
} CLEAR_LA_VAR;
/* Structure for MB Command DUMP */
/* Good for SLI2/3 only */
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} DUMP_VAR;
/* Structure for MB Command DUMP */
/* Good for SLI4 only */
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} DUMP4_VAR;
/*
* Dump type
*/
#define DMP_MEM_REG 0x1
#define DMP_NV_PARAMS 0x2
/*
* Dump region ID
*/
#define NODE_CFG_A_REGION_ID 0
#define NODE_CFG_B_REGION_ID 1
#define NODE_CFG_C_REGION_ID 2
#define NODE_CFG_D_REGION_ID 3
#define WAKE_UP_PARMS_REGION_ID 4
#define DEF_PCI_CFG_REGION_ID 5
#define PCI_CFG_1_REGION_ID 6
#define PCI_CFG_2_REGION_ID 7
#define RSVD1_REGION_ID 8
#define RSVD2_REGION_ID 9
#define RSVD3_REGION_ID 10
#define RSVD4_REGION_ID 11
#define RSVD5_REGION_ID 12
#define RSVD6_REGION_ID 13
#define RSVD7_REGION_ID 14
#define DIAG_TRACE_REGION_ID 15
#define WWN_REGION_ID 16
#define DMP_VPD_REGION 14
#define DMP_VPD_SIZE 1024
#define DMP_VPD_DUMP_WCOUNT 24
#define DMP_FCOE_REGION 23
#define DMP_FCOE_DUMP_WCOUNT 256
/* Structure for MB Command UPDATE_CFG */
/* Good for SLI2/3 and SLI4 */
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#define INIT_REGION 1
#define UPDATE_DATA 2
#define CLEAN_UP_CFG 3
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#define INIT_REGION 1
#define UPDATE_DATA 2
#define CLEAN_UP_CFG 3
#endif
/* Structure for MB Command DEL_LD_ENTRY (29) */
typedef struct
{
#ifdef EMLXS_LITTLE_ENDIAN
#else
#endif
#define FLASH_LOAD_LIST 1
#define RAM_LOAD_LIST 2
#define BOTH_LISTS 3
/* Structure for MB Command LOAD_AREA (81) */
typedef struct
{
#ifdef EMLXS_LITTLE_ENDIAN
#else
#endif
union
{
} un;
/* Structure for MB Command LOAD_EXP_ROM (9C) */
typedef struct
{
#ifdef EMLXS_LITTLE_ENDIAN
#else
#endif
union
{
} un;
/* Structure for MB Command CONFIG_HBQ (7C) */
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
union
{
struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} profile2;
struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} profile3;
struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} profile5;
} profiles;
/* Structure for MB Command REG_VPI(0x96) */
/* Good for SLI2/3 and SLI4 */
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} REG_VPI_VAR;
/* Structure for MB Command INIT_VPI(0xA3) */
/* Good for SLI4 only */
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} INIT_VPI_VAR;
/* Structure for MB Command UNREG_VPI (0x97) */
/* Good for SLI2/3 */
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/* Structure for MB Command UNREG_VPI (0x97) */
/* Good for SLI4 */
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/* Structure for MB Command REG_VFI(0x9F) */
/* Good for SLI4 only */
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
/* CHANGE with next firmware drop */
#endif
#ifdef EMLXS_LITTLE_ENDIAN
/* CHANGE with next firmware drop */
#endif
} REG_VFI_VAR;
/* Structure for MB Command INIT_VFI(0xA4) */
/* Good for SLI4 only */
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} INIT_VFI_VAR;
/* Structure for MB Command UNREG_VFI (0xA1) */
/* Good for SLI4 only */
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
union
{
} un;
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/* Structure for MB Command CONFIG_PORT (0x88) */
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
/* config block */
#endif
#ifdef EMLXS_LITTLE_ENDIAN
/* config block */
#endif
/* config block */
/* config block */
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
/* Handling */
/* Block */
/* Buffer Management */
#endif
#ifdef EMLXS_LITTLE_ENDIAN
/* Buffer Management */
/* Block */
/* Handling */
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/* Structure for MB Command REQUEST_FEATURES (0x9D) */
/* Good for SLI4 only */
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
#define SLI4_FEATURE_INHIBIT_AUTO_ABTS 0x0001
#define SLI4_FEATURE_NPIV 0x0002
#define SLI4_FEATURE_DIF 0x0004
#define SLI4_FEATURE_VIRTUAL_FABRICS 0x0008
#define SLI4_FEATURE_FCP_INITIATOR 0x0010
#define SLI4_FEATURE_FCP_TARGET 0x0020
#define SLI4_FEATURE_FCP_COMBO 0x0040
#define SLI4_FEATURE_INHIBIT_FIP 0x0080
/* SLI-2 Port Control Block */
/* SLIM POINTER */
typedef struct _SLI2_RDSC
{
} SLI2_RDSC;
typedef struct _PCB
{
#ifdef EMLXS_BIG_ENDIAN
#define TYPE_NATIVE_SLI2 0x01;
#define FEATURE_INITIAL_SLI2 0x01;
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#define FEATURE_INITIAL_SLI2 0x01;
#define TYPE_NATIVE_SLI2 0x01;
#endif
} PCB;
/* NEW_FEATURE */
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/* NEW_FEATURE */
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/* NEW_FEATURE */
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/* Union of all Mailbox Command types */
typedef union
{
/* UPDATE_CFG cmd */
} MAILVARIANTS;
#define MAILBOX_CMD_BSIZE 128
#define MAILBOX_CMD_WSIZE 32
/*
* SLI-2 specific structures
*/
typedef struct _SLI1_DESC
{
} SLI1_DESC; /* 128 bytes */
typedef struct
{
} HGP;
typedef struct
{
} PGP;
typedef struct _SLI2_DESC
{
} SLI2_DESC; /* 128 bytes */
typedef union
{
} SLI_VAR;
typedef volatile struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} MAILBOX; /* 256 bytes */
/* SLI4 IOCTL Mailbox */
/* ALL SLI4 specific mbox commands have a standard request /response header */
/* Word 0 is just like SLI 3 */
typedef struct mbox_req_hdr
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
typedef struct mbox_rsp_hdr
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
typedef struct be_req_hdr
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
union
{
} un_hdr;
} be_req_hdr_t;
/* SLI_CONFIG Mailbox commands */
#define IOCTL_SUBSYSTEM_COMMON 0x01
#define IOCTL_SUBSYSTEM_FCOE 0x0C
#define IOCTL_SUBSYSTEM_DCBX 0x10
#define COMMON_OPCODE_READ_FLASHROM 0x06
#define COMMON_OPCODE_WRITE_FLASHROM 0x07
#define COMMON_OPCODE_CQ_CREATE 0x0C
#define COMMON_OPCODE_EQ_CREATE 0x0D
#define COMMON_OPCODE_MQ_CREATE 0x15
#define COMMON_OPCODE_GET_CNTL_ATTRIB 0x20
#define COMMON_OPCODE_NOP 0x21
#define COMMON_OPCODE_QUERY_FIRMWARE_CONFIG 0x3A
#define COMMON_OPCODE_RESET 0x3D
#define COMMON_OPCODE_MANAGE_FAT 0x44
#define FCOE_OPCODE_WQ_CREATE 0x01
#define FCOE_OPCODE_CFG_POST_SGL_PAGES 0x03
#define FCOE_OPCODE_RQ_CREATE 0x05
#define FCOE_OPCODE_READ_FCF_TABLE 0x08
#define FCOE_OPCODE_ADD_FCF_TABLE 0x09
#define FCOE_OPCODE_POST_HDR_TEMPLATES 0x0B
#define DCBX_OPCODE_GET_DCBX_MODE 0x04
#define DCBX_OPCODE_SET_DCBX_MODE 0x05
typedef struct
{
struct
{
#define MGMT_FLASHROM_OPCODE_FLASH 1
#define MGMT_FLASHROM_OPCODE_SAVE 2
#define MGMT_FLASHROM_OPCODE_CLEAR 3
#define MGMT_FLASHROM_OPCODE_REPORT 4
#define MGMT_FLASHROM_OPCODE_INFO 5
#define MGMT_FLASHROM_OPCODE_CRC 6
#define MGMT_FLASHROM_OPTYPE_ISCSI_FIRMWARE 0
#define MGMT_FLASHROM_OPTYPE_REDBOOT 1
#define MGMT_FLASHROM_OPTYPE_ISCSI_BIOS 2
#define MGMT_FLASHROM_OPTYPE_PXE_BIOS 3
#define MGMT_FLASHROM_OPTYPE_CTRLS 4
#define MGMT_FLASHROM_OPTYPE_CFG_IPSEC 5
#define MGMT_FLASHROM_OPTYPE_CFG_INI 6
#define MGMT_FLASHROM_OPTYPE_ROM_OFFSET 7
#define MGMT_FLASHROM_OPTYPE_FCOE_BIOS 8
#define MGMT_FLASHROM_OPTYPE_ISCSI_BACKUP 9
#define MGMT_FLASHROM_OPTYPE_FCOE_FIRMWARE 10
#define MGMT_FLASHROM_OPTYPE_FCOE_BACKUP 11
#define MGMT_FLASHROM_OPTYPE_CTRLP 12
} params;
typedef struct
{
union
{
struct
{
#define RETRIEVE_FAT 0
#define QUERY_FAT 1
#define CLEAR_FAT 2
} request;
struct
{
} response;
} params;
/* IOCTL_COMMON_QUERY_FIRMWARE_CONFIG */
typedef struct _BE_FW_CFG
{
} BE_FW_CFG;
typedef struct _IOCTL_COMMON_QUERY_FIRMWARE_CONFIG
{
union
{
struct
{
} request;
} params;
/* IOCTL_FCOE_READ_FCF_TABLE */
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} FCF_RECORD_t;
#define EMLXS_FCOE_MAX_RCV_SZ 0x800
/* defines for mac_address_provider */
#define EMLXS_MAM_BOTH 0 /* Both SPMA and FPMA */
typedef struct
{
union
{
struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} request;
struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} response;
} params;
/* IOCTL_FCOE_ADD_FCF_TABLE */
typedef struct
{
union
{
struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} request;
struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} response;
} params;
#define FCOE_FCF_MAC0 0x0E
#define FCOE_FCF_MAC1 0xFC
#define FCOE_FCF_MAC2 0x00
#define FCOE_FCF_MAC3 0xFF
#define FCOE_FCF_MAC4 0xFF
#define FCOE_FCF_MAC5 0xFE
#define FCOE_FCF_MAP0 0x0E
#define FCOE_FCF_MAP1 0xFC
#define FCOE_FCF_MAP2 0x00
#define MGMT_STATUS_FCF_IN_USE 0x3a
/* IOCTL_COMMON_NOP */
typedef struct _IOCTL_COMMON_NOP
{
union
{
struct
{
} request;
struct
{
} response;
} params;
/* Context for EQ create */
typedef struct _EQ_CONTEXT
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
/* define for Count field */
#define EQ_ELEMENT_COUNT_1024 2
#define EQ_ELEMENT_COUNT_2048 3
#define EQ_ELEMENT_COUNT_4096 4
/* define for Size field */
#define EQ_ELEMENT_SIZE_4 0
/* define for DelayMullt - used for interrupt coalescing */
#define EQ_DELAY_MULT 256
/* Context for CQ create */
typedef struct _CQ_CONTEXT
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} CQ_CONTEXT;
/* define for Count field */
#define CQ_ELEMENT_COUNT_256 0
#define CQ_ELEMENT_COUNT_512 1
#define CQ_ELEMENT_COUNT_1024 2
/* Context for MQ create */
typedef struct _MQ_CONTEXT
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} MQ_CONTEXT;
/* define for Size field */
#define MQ_ELEMENT_COUNT_16 0x05
/* Context for RQ create */
typedef struct _RQ_CONTEXT
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} RQ_CONTEXT;
/* IOCTL_COMMON_EQ_CREATE */
typedef struct
{
union
{
struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} request;
struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} response;
} params;
/* IOCTL_COMMON_CQ_CREATE */
typedef struct
{
union
{
struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} request;
struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} response;
} params;
/* IOCTL_COMMON_MQ_CREATE */
typedef struct
{
union
{
struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} request;
struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} response;
} params;
/* IOCTL_FCOE_RQ_CREATE */
typedef struct
{
union
{
struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} request;
struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} response;
} params;
/* IOCTL_FCOE_WQ_CREATE */
typedef struct
{
union
{
struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} request;
struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} response;
} params;
/* IOCTL_FCOE_CFG_POST_SGL_PAGES */
typedef struct _FCOE_SGL_PAGES
{
typedef struct
{
union
{
struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} request;
struct
{
} response;
} params;
/* IOCTL_FCOE_POST_HDR_TEMPLATES */
typedef struct _IOCTL_FCOE_POST_HDR_TEMPLATES
{
union
{
struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
}request;
}params;
#define EMLXS_IOCTL_DCBX_MODE_CEE 0 /* Mapped to FIP mode */
/* IOCTL_DCBX_GET_DCBX_MODE */
typedef struct _IOCTL_DCBX_GET_DCBX_MODE
{
union
{
struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} request;
struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} response;
} params;
/* IOCTL_DCBX_SET_DCBX_MODE */
typedef struct _IOCTL_DCBX_SET_DCBX_MODE
{
union
{
struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} request;
struct
{
} response;
} params;
/* IOCTL_COMMON_GET_CNTL_ATTRIB */
typedef struct
{
char flashrom_version_string[32];
char manufacturer_name[32];
char rsvd0[28];
char controller_model_number[32];
char controller_description[64];
char controller_serial_number[32];
char ip_version_string[32];
char firmware_version_string[32];
char bios_version_string[32];
char redboot_version_string[32];
char driver_version_string[32];
char fw_on_flash_version_string[32];
typedef struct
{
typedef struct
{
union
{
struct
{
} request;
struct
{
} response;
} params;
typedef union
{
/* Structure for MB Command SLI_CONFIG(0x9b) */
/* Good for SLI4 only */
typedef struct
{
typedef union
{
} MAILVARIANTS4; /* Used for SLI-4 */
#define MAILBOX_CMD_SLI4_BSIZE 256
#define MAILBOX_CMD_SLI4_WSIZE 64
#define MAILBOX_CMD_MAX_BSIZE 256
#define MAILBOX_CMD_MAX_WSIZE 64
typedef volatile struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
} MAILBOX4; /* Used for SLI-4 */
/*
* End Structure Definitions for Mailbox Commands
*/
typedef struct emlxs_mbq
{
/* Defferred handling pointers */
/* structure */
/* structure */
/* structure */
/* structure */
#define MBQ_POOL_ALLOCATED 0x00000001
#define MBQ_PASSTHRU 0x00000002
#define MBQ_EMBEDDED 0x00000004
#define MBQ_BOOTSTRAP 0x00000008
#define MBQ_INIT_MASK 0x0000ffff
#ifdef MBOX_EXT_SUPPORT
#endif /* MBOX_EXT_SUPPORT */
} emlxs_mbq_t;
typedef emlxs_mbq_t MAILBOXQ;
/* We currently do not support IOCBs in SLI1 mode */
typedef struct
{
#ifdef MBOX_EXT_SUPPORT
#endif /* MBOX_EXT_SUPPORT */
(sizeof (MAILBOX) + MBOX_EXTENSION_SIZE))];
} SLIM1;
typedef struct
{
#ifdef MBOX_EXT_SUPPORT
#endif /* MBOX_EXT_SUPPORT */
} SLIM2;
/* def for new 2MB Flash (Pegasus ...) */
#define MBX_LOAD_AREA 0x81
#define MBX_LOAD_EXP_ROM 0x9C
#define FILE_TYPE_AWC 0xE1A01001
#define FILE_TYPE_DWC 0xE1A02002
#define FILE_TYPE_BWC 0xE1A03003
#define AREA_ID_MASK 0xFFFFFF0F
#define AREA_ID_AWC 0x00000001
#define AREA_ID_DWC 0x00000002
#define AREA_ID_BWC 0x00000003
#define CMD_START_ERASE 1
#define CMD_CONTINUE_ERASE 2
#define CMD_DOWNLOAD 3
#define CMD_END_DOWNLOAD 4
#define RSP_ERASE_STARTED 1
#define RSP_ERASE_COMPLETE 2
#define RSP_DOWNLOAD_MORE 3
#define RSP_DOWNLOAD_DONE 4
#define EROM_CMD_FIND_IMAGE 8
#define EROM_CMD_CONTINUE_ERASE 9
#define EROM_CMD_COPY 10
#define EROM_RSP_ERASE_STARTED 8
#define EROM_RSP_ERASE_COMPLETE 9
#define EROM_RSP_COPY_MORE 10
#define EROM_RSP_COPY_DONE 11
#define ALLext 1
#define DWCext 2
#define BWCext 3
#define NO_ALL 0
#define ALL_WITHOUT_BWC 1
#define ALL_WITH_BWC 2
#define KERNEL_START_ADDRESS 0x000000
#define DOWNLOAD_START_ADDRESS 0x040000
#define EXP_ROM_START_ADDRESS 0x180000
#define SCRATCH_START_ADDRESS 0x1C0000
#define CONFIG_START_ADDRESS 0x1E0000
typedef struct SliAifHdr
{
typedef struct ImageHdr
{
} IMAGE_HDR, *PIMAGE_HDR;
typedef struct
{
#ifdef EMLXS_BIG_ENDIAN
#endif
#ifdef EMLXS_LITTLE_ENDIAN
#endif
union
{
} u0;
union
{
} u1;
#define PROG_DESCR_STR_LEN 24
#define MAX_LOAD_ENTRY 32
typedef struct
{
union
{
} un;
} LOAD_ENTRY;
typedef struct
{
} LOAD_LIST;
#ifdef __cplusplus
}
#endif
#endif /* _EMLXS_MBOX_H */