emlxs_fc.h revision fe199829b492e6b3aa36dd76af597360bb4af121
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Emulex. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _EMLXS_FC_H
#define _EMLXS_FC_H
#ifdef __cplusplus
extern "C" {
#endif
typedef struct emlxs_buf
{
void *bmp; /* Save the buffer pointer */
/* list for later use. */
void *node; /* Save node and used by */
/* abort */
void *channel; /* Save channel and used by */
/* abort */
/* for the fc_packet_t */
/* abort */
/* abort */
/* this packet is responding */
/* to, if any */
#ifdef SFCT_SUPPORT
#define EMLXS_FCT_ELS_RSP 0x04
#define EMLXS_FCT_FCP_DATA 0x20
#define EMLXS_FCT_FCP_STATUS 0x40
#define EMLXS_FCT_SEND_STATUS 0x01
#define EMLXS_FCT_ABORT_INP 0x02
#define EMLXS_FCT_IO_INP 0x04
#define EMLXS_FCT_REGISTERED 0x10
#define EMLXS_FCT_PLOGI_RECEIVED 0x20
#define EMLXS_FCT_FLOGI 0x40
#define EMLXS_FCT_FCP_CMD_RECEIVED 1
#define EMLXS_FCT_ELS_CMD_RECEIVED 2
#define EMLXS_FCT_CMD_POSTED 3
#define EMLXS_FCT_CMD_WAITQ 4
#define EMLXS_FCT_SEND_CMD_RSP 5
#define EMLXS_FCT_SEND_ELS_RSP 6
#define EMLXS_FCT_SEND_ELS_REQ 7
#define EMLXS_FCT_SEND_CT_REQ 8
#define EMLXS_FCT_RSP_PENDING 9
#define EMLXS_FCT_REQ_PENDING 10
#define EMLXS_FCT_REG_PENDING 11
#define EMLXS_FCT_REG_COMPLETE 12
#define EMLXS_FCT_OWNED 13
#define EMLXS_FCT_SEND_FCP_DATA 14
#define EMLXS_FCT_SEND_FCP_STATUS 15
#define EMLXS_FCT_DATA_PENDING 16
#define EMLXS_FCT_STATUS_PENDING 17
#define EMLXS_FCT_PKT_COMPLETE 18
#define EMLXS_FCT_PKT_FCPRSP_COMPLETE 19
#define EMLXS_FCT_PKT_ELSRSP_COMPLETE 20
#define EMLXS_FCT_PKT_ELSCMD_COMPLETE 21
#define EMLXS_FCT_PKT_CTCMD_COMPLETE 22
#define EMLXS_FCT_REQ_COMPLETE 23
#define EMLXS_FCT_CLOSE_PENDING 24
#define EMLXS_FCT_ABORT_PENDING 25
#define EMLXS_FCT_ABORT_DONE 26
#define EMLXS_FCT_IO_DONE 27
#endif /* SFCT_SUPPORT */
#ifdef SAN_DIAG_SUPPORT
#endif
} emlxs_buf_t;
#ifdef FCT_IO_TRACE
#else
/* define to set fct_state */
#endif /* FCT_IO_TRACE */
/* pkt_flags */
#define PACKET_IN_COMPLETION 0x00000001
#define PACKET_IN_TXQ 0x00000002
#define PACKET_IN_CHIPQ 0x00000004
#define PACKET_IN_DONEQ 0x00000008
#define PACKET_FCP_RESET 0x00000030
#define PACKET_FCP_TGT_RESET 0x00000010
#define PACKET_FCP_LUN_RESET 0x00000020
#define PACKET_POLLED 0x00000040
#ifdef EMLXS_I386
#define PACKET_FCP_SWAPPED 0x00000100
#define PACKET_ELS_SWAPPED 0x00000200
#define PACKET_CT_SWAPPED 0x00000400
#define PACKET_CSP_SWAPPED 0x00000800
#endif /* EMLXS_I386 */
#define PACKET_STALE 0x00001000
#define PACKET_IN_TIMEOUT 0x00010000
#define PACKET_IN_FLUSH 0x00020000
#define PACKET_IN_ABORT 0x00040000
#define PACKET_CHIP_COMP 0x00100000
#define PACKET_COMPLETED 0x00200000
#define PACKET_ULP_OWNED 0x00400000
#define PACKET_STATE_VALID 0x01000000
#define PACKET_FCP_RSP_VALID 0x02000000
#define PACKET_ELS_RSP_VALID 0x04000000
#define PACKET_CT_RSP_VALID 0x08000000
#define PACKET_DELAY_REQUIRED 0x10000000
#define PACKET_ALLOCATED 0x40000000
#define PACKET_VALID 0x80000000
/*
* From fc_error.h pkt_reason (except for state = NPORT_RJT, FABRIC_RJT,
* NPORT_BSY, FABRIC_BSY, LS_RJT, BA_RJT, FS_RJT)
*
* FCA unique error codes can begin after FC_REASON_FCA_UNIQUE.
* Each FCA defines its own set with values greater >= 0x7F
*/
#define FC_REASON_FCA_DEFINED 0x100
/*
* Device VPD save area
*/
typedef struct emlxs_vpd
{
char postKernName[32];
char opFwName[32];
char opFwLabel[32];
char sli1FwName[32];
char sli1FwLabel[32];
char sli2FwName[32];
char sli2FwLabel[32];
char sli3FwName[32];
char sli3FwLabel[32];
char sli4FwName[32];
char sli4FwLabel[32];
char fw_version[32];
char fw_label[32];
char fcode_version[32];
char boot_version[32];
char serial_num[32];
char part_num[32];
char port_num[20];
char eng_change[32];
char manufacturer[80];
char model[80];
char model_desc[256];
char prog_types[256];
char id[80];
} emlxs_vpd_t;
typedef struct emlxs_queue
{
typedef emlxs_queue_t Q;
/*
* This structure is used when allocating a buffer pool.
* Note: this should be identical to gasket buf_info (fldl.h).
*/
typedef struct emlxs_buf_info
{
/* address to physical address (skip */
/* the malloc). */
/* For free - just unmap the given */
/* physical address (skip the free). */
/* physical memory */
#define FC_MBUF_DMA32 0x20
void *virt; /* specifies virtual buffer pointer */
void *data_handle;
void *dma_handle;
typedef emlxs_buf_info_t MBUF_INFO;
#define EMLXS_ELS_HBQ_ID 0
#define EMLXS_IP_HBQ_ID 1
#define EMLXS_CT_HBQ_ID 2
#define EMLXS_FCT_HBQ_ID 3
#ifdef SFCT_SUPPORT
#else
#endif /* SFCT_SUPPORT */
/*
* path for IOs.
*/
typedef struct emlxs_channel
{
void *iopath; /* ptr to SLI3/4 io path */
#define EMLXS_NEEDS_TRIGGER 1
/* Protected by EMLXS_TX_CHANNEL_LOCK */
/* Channel command counters */
typedef emlxs_channel_t CHANNEL;
/*
* Should be able to handle max number of io paths for a
* SLI4 HBA (EMLXS_MAX_WQS) or for a SLI3 HBA (MAX_RINGS)
*/
#define MAX_CHANNEL EMLXS_MSI_MAX_INTRS
/* Structure used to access adapter rings */
typedef struct emlxs_ring
{
void *fc_cmdringaddr; /* virtual offset for cmd */
/* rings */
void *fc_rspringaddr; /* virtual offset for rsp */
/* rings */
/* structure */
/* structure */
/* per ring */
/* per ring */
/* ring */
/* ring */
} emlxs_ring_t;
typedef emlxs_ring_t RING;
#ifdef SAN_DIAG_SUPPORT
/*
* Although right now it's just 1 field, SAN Diag anticipates that this
* structure will grow in the future.
*/
typedef struct sd_timestat_level0 {
int count;
#endif
typedef struct emlxs_node
{
struct emlxs_node *nlp_list_next;
struct emlxs_node *nlp_list_prev;
/* REG_LOGIN */
/* REG_LOGIN */
/* nlp_fcp_info */
#define NODE_POOL_ALLOCATED 0x00000001
/* Protected by EMLXS_TX_CHANNEL_LOCK */
/* flags */
/* nlp_flag */
#define NLP_CLOSED 0x1
#define NLP_OFFLINE 0x2
#define NLP_RPI_XRI 0x4
/* Queue head */
/* Queue pointer used */
/* when node needs */
/* servicing */
#ifdef DHCHAP_SUPPORT
#endif /* DHCHAP_SUPPORT */
#ifdef SAN_DIAG_SUPPORT
#endif
} emlxs_node_t;
typedef emlxs_node_t NODELIST;
typedef struct emlxs_fcip_nethdr
{
typedef emlxs_fcip_nethdr_t NETHDR;
#define MEM_NLP 0 /* memory segment to hold node list entries */
#ifdef SFCT_SUPPORT
#define FC_MAX_SEG 8
#else
#define FC_MAX_SEG 7
#endif /* SFCT_SUPPORT */
/* A BPL entry is 12 bytes. Subtract 2 for command and response buffers */
/* A SGL entry is 16 bytes. Subtract 2 for command and response buffers */
#ifdef EMLXS_I386
#else /* EMLXS_SPARC */
#define EMLXS_SGLLEN 1
#endif /* EMLXS_I386 */
#define MEM_BUF_SIZE 1024
#define MEM_BUF_COUNT 64
#define MEM_ELSBUF_SIZE MEM_BUF_SIZE
#define MEM_IPBUF_SIZE 65535
#define MEM_IPBUF_COUNT 60
#define MEM_CTBUF_COUNT 8
#define MEM_FCTBUF_SIZE 65535
#define MEM_FCTBUF_COUNT 128
typedef struct emlxs_memseg
{
/* of memory block */
/* of memory block */
char fc_label[32];
typedef emlxs_memseg_t MEMSEG;
/* Board stat counters */
typedef struct emlxs_stats
{
#ifdef SFCT_SUPPORT
#endif /* SFCT_SUPPORT */
#ifdef SFCT_SUPPORT
#endif /* SFCT_SUPPORT */
#define EMLXS_NUM_THREADS 8
#define EMLXS_MIN_TASKS 8
#define EMLXS_MAX_TASKS 8
#define EMLXS_NUM_HASH_QUES 32
/* pkt_tran_flag */
#define FC_TRAN_COMPLETED 0x8000
typedef struct emlxs_dfc_event
{
void *dataout;
typedef struct emlxs_hba_event
{
#ifdef SFCT_SUPPORT
/*
* FctP2IOXcnt will count IOs by their fcpDL. Counters
* are for buckets of various power of 2 sizes.
* Bucket 0 < 512 > 0
* Bucket 1 >= 512 < 1024
* Bucket 2 >= 1024 < 2048
* Bucket 3 >= 2048 < 4096
* Bucket 4 >= 4096 < 8192
* Bucket 5 >= 8192 < 16K
* Bucket 6 >= 16K < 32K
* Bucket 7 >= 32K < 64K
* Bucket 8 >= 64K < 128K
* Bucket 9 >= 128K < 256K
* Bucket 10 >= 256K < 512K
* Bucket 11 >= 512K < 1MB
* Bucket 12 >= 1MB < 2MB
* Bucket 13 >= 2MB < 4MB
* Bucket 14 >= 4MB < 8MB
* Bucket 15 >= 8MB
*/
#define MAX_TGTPORT_IOCNT 16
/*
* These routines will bump the right counter, based on
* the size of the IO inputed, with the least number of
* comparisions. A max of 5 comparisions is only needed
* to classify the IO in one of 16 ranges. A binary search
* to locate the high bit in the size is used.
*/
{ \
/* Use binary search to find the first high bit */ \
if (cnt & 0xffff0000) { \
if (cnt & 0xff800000) { \
} \
else { \
/* It must be 0x007f0000 */ \
if (cnt & 0x00700000) { \
if (cnt & 0x00400000) { \
} \
else { \
/* it must be 0x00300000 */ \
if (cnt & 0x00200000) { \
} \
else { \
/* It must be 0x00100000 */ \
} \
} \
} \
else { \
/* It must be 0x000f0000 */ \
if (cnt & 0x000c0000) { \
if (cnt & 0x00080000) { \
} \
else { \
/* It must be 0x00040000 */ \
} \
} \
else { \
/* It must be 0x00030000 */ \
if (cnt & 0x00020000) { \
} \
else { \
/* It must be 0x00010000 */ \
} \
} \
} \
} \
} \
else { \
if (cnt & 0x0000fe00) { \
if (cnt & 0x0000f000) { \
if (cnt & 0x0000c000) { \
if (cnt & 0x00008000) { \
} \
else { \
/* It must be 0x00004000 */ \
} \
} \
else { \
/* It must be 0x00000300 */ \
if (cnt & 0x00000200) { \
} \
else { \
/* It must be 0x00000100 */ \
} \
} \
} \
else { \
/* It must be 0x00000e00 */ \
if (cnt & 0x00000800) { \
} \
else { \
/* It must be 0x00000600 */ \
if (cnt & 0x00000400) { \
} \
else { \
/* It must be 0x00000200 */ \
} \
} \
} \
} \
else { \
/* It must be 0x000001ff */ \
TGTPORTSTAT.FctP2IORcnt[0]++; \
} \
} \
}
{ \
/* Use binary search to find the first high bit */ \
if (cnt & 0xffff0000) { \
if (cnt & 0xff800000) { \
} \
else { \
/* It must be 0x007f0000 */ \
if (cnt & 0x00700000) { \
if (cnt & 0x00400000) { \
} \
else { \
/* It must be 0x00300000 */ \
if (cnt & 0x00200000) { \
} \
else { \
/* It must be 0x00100000 */ \
} \
} \
} \
else { \
/* It must be 0x000f0000 */ \
if (cnt & 0x000c0000) { \
if (cnt & 0x00080000) { \
} \
else { \
/* it must be 0x00040000 */ \
} \
} \
else { \
/* It must be 0x00030000 */ \
if (cnt & 0x00020000) { \
} \
else { \
/* It must be 0x00010000 */ \
} \
} \
} \
} \
} \
else { \
if (cnt & 0x0000fe00) { \
if (cnt & 0x0000f000) { \
if (cnt & 0x0000c000) { \
if (cnt & 0x00008000) { \
} \
else { \
/* It must be 0x00004000 */ \
} \
} \
else { \
/* It must be 0x00000300 */ \
if (cnt & 0x00000200) { \
} \
else { \
/* It must be 0x00000100 */ \
} \
} \
} \
else { \
/* It must be 0x00000e00 */ \
if (cnt & 0x00000800) { \
} \
else { \
/* It must be 0x00000600 */ \
if (cnt & 0x00000400) { \
} \
else { \
/* It must be 0x00000200 */ \
} \
} \
} \
} \
else { \
/* It must be 0x000001ff */ \
TGTPORTSTAT.FctP2IOWcnt[0]++; \
} \
} \
}
typedef struct emlxs_tgtport_stat
{
/* IO counters */
/* IOCB handling counters */
/* Fct event counters */
#ifdef FCT_IO_TRACE
#define MAX_IO_TRACE 67
typedef struct emlxs_iotrace
{
#endif /* FCT_IO_TRACE */
#endif /* SFCT_SUPPORT */
/*
* Port Information Data Structure
*/
typedef struct emlxs_port
{
/* Virtual port management */
#define EMLXS_PORT_ENABLE 0x00000001
#define EMLXS_PORT_BOUND 0x00000002
#define EMLXS_PORT_IP_UP 0x00000010
#define EMLXS_PORT_CONFIG 0x00000020
/* flag */
/* completed */
/* across hard reset */
/* across link reset */
/* logins */
/* logins */
#define EMLXS_OPT_RESTRICT_MASK 0x00000003
/* FC world wide names */
char snn[256];
char spn[256];
/* Common service paramters */
/* fc_id management */
/* support FC_PORT_GET_P2P_INFO only */
/* FC_AL management */
/* Node management */
/* Polled packet management */
/* ULP */
void (*ulp_statec_cb) (); /* Port state change */
/* callback routine */
void (*ulp_unsol_cb) (); /* unsolicited event */
/* callback routine */
/* ULP unsolicited buffers */
/* before link up */
/* before link up */
#ifdef DHCHAP_SUPPORT
#endif /* DHCHAP_SUPPORT */
#ifdef SFCT_SUPPORT
#define FCT_BUF_COUNT_512 256
#define FCT_BUF_COUNT_8K 128
#define FCT_BUF_COUNT_64K 64
#define FCT_BUF_COUNT_128K 64
#define FCT_MAX_BUCKETS 16
int fct_queue_depth;
#define EMLXS_FCT_DFLT_QDEPTH 64
char cfd_name[24];
#define FCT_STATE_PORT_ONLINE 0x00000001
#define FCT_STATE_NOT_ACKED 0x00000002
#define FCT_STATE_LINK_UP 0x00000010
#define FCT_STATE_LINK_UP_ACKED 0x00000020
/* Used to save fct_cmd for deferred unsol ELS commands, except FLOGI */
/* Used to save context for deferred unsol FLOGIs */
#ifdef FCT_IO_TRACE
#endif /* FCT_IO_TRACE */
#endif /* SFCT_SUPPORT */
#ifdef SAN_DIAG_SUPPORT
#define SD_INVALID 0x00
#define SD_COLLECTING 0x01
#define SD_STOPPED 0x02
/* SD event management list */
#endif
/* Used for SLI4 */
} emlxs_port_t;
/* Host Attn reg */
/* Chip Attn reg */
/* Host Status reg */
/* Host Cntl reg */
/* BIU Configuration reg */
/* Used by SBUS adapter */
/* TITAN Cntl reg */
/* TITAN Status reg */
/* TITAN Update reg */
/* MPU Semaphore reg */
/* Bootstrap Mailbox Doorbell reg */
/* MQ Doorbell reg */
/* CQ Doorbell reg */
/* WQ Doorbell reg */
/* RQ Doorbell reg */
/* Used by SBUS adapter */
(_offset)))
/* SLI4 registers */
{ \
}
/* Used when EMLXS_PORT_LOCK is already held */
{ \
{ \
&emlxs_state_msg, "%s --> %s", \
{ \
} \
} \
}
#ifdef FMA_SUPPORT
}
#endif /* FMA_SUPPORT */
/*
* This is the HBA control area for the adapter
*/
#ifdef MODSYM_SUPPORT
typedef struct emlxs_modsym
{
/* Leadville (fctl) */
int (*fc_fca_detach)(dev_info_t *);
int (*fc_fca_init)(struct dev_ops *);
#ifdef SFCT_SUPPORT
/* Comstar (fct) */
void* (*fct_alloc)(fct_struct_id_t, int, int);
void (*fct_free)(void *);
int (*fct_register_local_port)(fct_local_port_t *);
void (*fct_deregister_local_port)(fct_local_port_t *);
void (*fct_ctl)(void *, int, void *);
uint32_t);
(fct_local_port_t *, uint32_t, char *);
(fct_local_port_t *, uint32_t, char *);
void (*fct_cmd_fca_aborted)
(fct_cmd_t *, fct_status_t, int);
(fct_local_port_t *, fct_flogi_xchg_t *);
/* Comstar (stmf) */
void* (*stmf_alloc)(stmf_struct_id_t, int, int);
void (*stmf_free)(void *);
void (*stmf_deregister_port_provider) (stmf_port_provider_t *);
int (*stmf_register_port_provider) (stmf_port_provider_t *);
#endif /* SFCT_SUPPORT */
extern emlxs_modsym_t emlxs_modsym;
#else
#endif /* MODSYM_SUPPORT */
/* defines for resource state */
#define RESOURCE_FREE 0
#define RESOURCE_ALLOCATED 1
#define RESOURCE_FCFI_REG 2
#define RESOURCE_FCFI_DISC 4
#define RESOURCE_FCFI_VLAN_ID 8
#define RESOURCE_VFI_REG 2
#define RESOURCE_RPI_PAUSED 2
#define RESOURCE_XRI_RESERVED 2
#define RESOURCE_XRI_PENDING_IO 4
#define RESOURCE_XRI_ABORT_INP 8
typedef struct VFIobject
{
struct FCFIobject *FCFIp;
} VFIobj_t;
typedef struct RPIobject
{
} RPIobj_t;
typedef struct XRIobject
{
} XRIobj_t;
typedef struct FCFIobject
{
struct RPIobject scratch_rpi;
} FCFIobj_t;
typedef struct RPIHdrTmplate
{
typedef struct EQ_DESC
{
} EQ_DESC_t;
typedef struct CQ_DESC
{
} CQ_DESC_t;
typedef struct WQ_DESC
{
} WQ_DESC_t;
typedef struct RQ_DESC
{
} RQ_DESC_t;
typedef struct RXQ_DESC
{
} RXQ_DESC_t;
typedef struct MQ_DESC
{
} MQ_DESC_t;
/* Define the number of queues the driver will be using */
#define EMLXS_MAX_EQS EMLXS_MSI_MAX_INTRS
#define EMLXS_MAX_WQS EMLXS_MSI_MAX_INTRS
#define EMLXS_MAX_MQS 1
/* One CQ for each WQ & (RQ pair) plus one for the MQ */
/* The First CQ created is ALWAYS for mbox / event handling */
#define EMLXS_CQ_MBOX 0
/* The Second CQ created is ALWAYS for unsol rcv handling */
/* At this time we are allowing ONLY 1 pair of RQs */
#define EMLXS_CQ_RCV 1
/* The remaining CQs are for WQ completions */
#define EMLXS_CQ_OFFSET_WQ 2
/* FCFI RQ Configuration */
#define EMLXS_FCFI_RQ0_INDEX 0
#define EMLXS_FCFI_RQ0_RMASK 0 /* match all */
#define EMLXS_FCFI_RQ0_RCTL 0 /* match all */
#define EMLXS_FCFI_RQ0_TMASK 0 /* match all */
#define EMLXS_FCFI_RQ0_TYPE 0 /* match all */
/* Define the maximum value for a Queue Id */
#define EMLXS_MAX_EQ_IDS 256
#define EMLXS_MAX_CQ_IDS 1024
#define EMLXS_MAX_WQ_IDS 1024
#define EMLXS_MAX_RQ_IDS 4
#define EMLXS_RXQ_ELS 0
#define EMLXS_RXQ_CT 1
#define EMLXS_MAX_RXQS 2
#define PCI_CONFIG_SIZE 0x80
typedef struct emlxs_sli3
{
/* SLIM management */
/* HBQ management */
/* configured */
/* Adapter memory management */
/* SBUS adapter management */
/* Flash */
/* CORE */
/* CSR */
/* SLI 2/3 Adapter register management */
/* config reg */
/* attn reg */
/* ctl reg */
/* attn reg */
/* status reg */
/* Ctrl reg */
/* Status reg */
/* Update reg */
/* Ring management */
/* Protected by EMLXS_FCTAB_LOCK */
#ifdef EMLXS_SPARC
/* bpl buffers */
#endif /* EMLXS_SPARC */
} emlxs_sli3_t;
typedef struct emlxs_sli4
{
/* SLI4 Adapter register management */
#define EMLXS_SLI4_INTR_ENABLED 0x1
/* Save Config Region 23 info */
#define EMLXS_DUMP_REGION_SIZE 1024
/* Single linked list for available XRIs */
/* Double linked list for XRIs in use */
/* Used to map a queue ID to a queue DESC_t */
} emlxs_sli4_t;
typedef struct emlxs_sli_api
{
int (*sli_map_hdw)();
void (*sli_unmap_hdw)();
int32_t (*sli_online)();
void (*sli_offline)();
uint32_t (*sli_hba_reset)();
void (*sli_hba_kill)();
void (*sli_issue_iocb_cmd)();
uint32_t (*sli_issue_mbox_cmd)();
uint32_t (*sli_prep_fct_iocb)();
uint32_t (*sli_prep_fcp_iocb)();
uint32_t (*sli_prep_ip_iocb)();
uint32_t (*sli_prep_els_iocb)();
uint32_t (*sli_prep_ct_iocb)();
void (*sli_poll_intr)();
int32_t (*sli_intx_intr)();
uint32_t (*sli_msi_intr)();
void (*sli_disable_intr)();
void (*sli_timer)();
void (*sli_poll_erratt)();
typedef struct emlxs_hba
{
#ifdef FMA_SUPPORT
#endif /* FMA_SUPPORT */
/* HBA Info */
char snn[256];
char spn[256];
#define PCI_FC 0
#define SBUS_FC 1
/* Link management */
/* Memory Pool management */
/* structures */
/* Fibre Channel Service Parameters */
/* Adapter State management */
#define FC_INIT_NVPARAMS 0x11
#define FC_INIT_REV 0x12
#define FC_INIT_CFGPORT 0x13
#define FC_INIT_CFGRING 0x14
#define FC_INIT_INITLINK 0x15
#define FC_LINK_DOWN 0x20
#define FC_LINK_DOWN_PERSIST 0x21
#define FC_LINK_UP 0x30
#define FC_CLEAR_LA 0x31
#define FC_READY 0x40
#define FC_ONLINING_MODE 0x00000001
#define FC_ONLINE_MODE 0x00000002
#define FC_OFFLINING_MODE 0x00000004
#define FC_OFFLINE_MODE 0x00000008
/* and link is ready */
/* and NameServer cmds */
#define FC_BOOTSTRAPMB_INIT 0x00000400
#define FC_FABRIC_ATTACHED 0x00001000
#define FC_PT_TO_PT 0x00002000
#define FC_BYPASSED_MODE 0x00004000
#define FC_INTERLOCKED 0x00200000
#define FC_HBQ_ENABLED 0x00400000
#define FC_ASYNC_EVENTS 0x00800000
#define FC_ILB_MODE 0x01000000
#define FC_ELB_MODE 0x02000000
/* over temperature event */
/* mailbox timeout event */
/* a hard reset */
/* a linkdown */
/* SBUS adapter management */
/* pci config */
/* PCI BUS adapter management */
#define EMLXS_HBA_SLI1_MODE 1
#define EMLXS_HBA_SLI2_MODE 2
#define EMLXS_HBA_SLI3_MODE 3
#define EMLXS_HBA_SLI4_MODE 4
/* SLI private data */
union {
} sli;
/* SLI API entry point routines */
/* in progress */
/* IO Completion management */
/* Protected by EMLXS_PORT_LOCK */
/* IO Channel management */
#define CHANNEL_FCT channel_fcp
/* IOTag management */
/* iotag */
#define EMLXS_MAX_ABORT_TAG 0x7fff
/* regular iotag */
/* Mailbox Management */
/* Interrupt management */
void *intr_arg;
#define EMLXS_INTX_INITED 0x0001
#define EMLXS_INTX_ADDED 0x0002
#define EMLXS_MSI_ENABLED 0x0010
#define EMLXS_MSI_INITED 0x0020
#define EMLXS_MSI_ADDED 0x0040
#ifdef MSI_SUPPORT
#define MSI_CAP_ID 0x05
#define MSIX_CAP_ID 0x11
#endif /* MSI_SUPPORT */
/* IOCTL management */
#define EMLXS_OPEN 0x00000001
#define EMLXS_OPEN_EXCLUSIVE 0x00000002
/* Timer management */
#define EMLXS_TIMER_STARTED 0x0000001
#define EMLXS_TIMER_BUSY 0x0000002
#define EMLXS_TIMER_KILL 0x0000004
#define EMLXS_TIMER_ENDED 0x0000008
/* Misc Timers */
/* Power Management */
/* pm_state */
#define EMLXS_PM_IN_ATTACH 0x00000001
#define EMLXS_PM_IN_DETACH 0x00000002
#define EMLXS_PM_IN_SOL_CB 0x00000010
#define EMLXS_PM_IN_UNSOL_CB 0x00000020
#define EMLXS_PM_IN_LINK_RESET 0x00000100
#define EMLXS_PM_IN_HARD_RESET 0x00000200
#define EMLXS_PM_SUSPENDED 0x01000000
/* pm_level */
#define EMLXS_PM_ADAPTER_DOWN 0
#define EMLXS_PM_ADAPTER_UP 1
#ifdef IDLE_TIMER
#endif /* IDLE_TIMER */
/* Loopback management */
void *loopback_pkt;
/* Event management */
/* Parameter management */
/* Driver stat management */
/* Log management */
/* Port managment */
/* Last one is for */
/* NPIV ready test */
#ifdef DHCHAP_SUPPORT
/* Points to list of entries. */
/* Protected by auth_lock */
/* Points to list of entries. */
/* Protected by auth_lock */
#endif /* DHCHAP_SUPPORT */
#ifdef TEST_SUPPORT
#endif /* TEST_SUPPORT */
#ifdef MODFW_SUPPORT
#endif /* MODFW_SUPPORT */
#ifdef DUMP_SUPPORT
#define EMLXS_TXT_FILE 1
#define EMLXS_DMP_FILE 2
#define EMLXS_CEE_FILE 3
#define EMLXS_DRV_DUMP 0
#define EMLXS_TEMP_DUMP 1
#define EMLXS_USER_DUMP 2
#endif /* DUMP_SUPPORT */
} emlxs_hba_t;
#ifdef MSI_SUPPORT
#else
#endif /* MSI_SUPPORT */
/* Power Management Component */
#define EMLXS_PM_ADAPTER 0
/* nodes, rings */
/* polling */
/* polling */
/* buffer pool */
/* These SWAPs will swap on any platform */
/* These LE_SWAPs will only swap on a LE platform */
#ifdef EMLXS_LITTLE_ENDIAN
#if (EMLXS_MODREVX == EMLXS_MODREV2X)
#endif /* EMLXS_MODREV2X */
#else /* BIG ENDIAN */
#endif /* EMLXS_LITTLE_ENDIAN */
/* These BE_SWAPs will only swap on a BE platform */
#ifdef EMLXS_BIG_ENDIAN
#else /* LITTLE ENDIAN */
#endif /* EMLXS_BIG_ENDIAN */
#ifdef __cplusplus
}
#endif
#endif /* _EMLXS_FC_H */