bge_hw.h revision 7c478bd95313f5f23a4c958a745db2134aa03244
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * CDDL HEADER START
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3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
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3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * CDDL HEADER END
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * Copyright 2005 Sun Microsystems, Inc. All rights reserved.
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * Use is subject to license terms.
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel#pragma ident "%Z%%M% %I% %E% SMI"
3d19cdae966d9ac4218dd9859640463bd7da19d8stevelextern "C" {
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * First section:
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * Identification of the various Broadcom chips
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * Note: the various ID values are *not* all unique ;-(
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * Note: the presence of an ID here does *not* imply that the chip is
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * supported. At this time, only the 5703C, 5704C, and 5704S devices
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * used on the motherboards of certain Sun products are supported.
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * Note: the revision-id values in the PCI revision ID register are
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * *NOT* guaranteed correct. Use the chip ID from the MHCR instead.
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * Second section:
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * Offsets of important registers & definitions for bits therein
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * PCI-X registers & bits
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * Miscellaneous Host Control Register, in PCI config space
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel#define MHCR_CHIP_REV_5702_A0 0x10020000 /* duplicate! */
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel#define MHCR_CHIP_ASIC_REV(ChipRevId) ((ChipRevId) & 0xf0000000)
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * PCI DMA read/write Control Register, in PCI config space
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * Note that several fields previously defined here have been deleted
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * as they are not implemented in the 5703/4.
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * Note: the value of this register is critical. It is possible to
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * cause various unpleasant effects (DTOs, transaction deadlock, etc)
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * by programming the wrong value. The value #defined below has been
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * tested and shown to avoid all known problems. If it is to be changed,
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * correct operation must be reverified on all supported platforms.
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * In particular, we set both watermark fields to 2xCacheLineSize (128)
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * bytes and DMA_MIN_BEATS to 0 in order to avoid unfortunate interactions
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * with Tomatillo's internal pipelines, that otherwise result in stalls,
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * repeated retries, and DTOs.
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * These are the actual values to be put into the fields shown above
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel#define PDRWCR_DMA_WRITE_WATERMARK 0x00180000 /* 011 => 128 */
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel#define PDRWCR_DMA_READ_WATERMARK 0x00030000 /* 011 => 128 */
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * PCI State Register, in PCI config space
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * Note: this register is read-only unless the ENABLE_PCI_STATE_WRITE bit
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * is set in the MHCR, EXCEPT for the RETRY_SAME_DMA bit which is always RW
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * PCI Clock Control Register, in PCI config space
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * Dual MAC Control Register, in PCI config space
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel#define DUALMAC_CHANNEL_CONTROL_MASK 0x00000003 /* RW */
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * Register Indirect Access Address Register, 0x78 in PCI config
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * space. Once this is set, accesses to the Register Indirect
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * Access Data Register (0x80) refer to the register whose address
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * is given by *this* register. This allows access to all the
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * operating registers, while using only config space accesses.
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * Note that the address written to the RIIAR should lie in one
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * of the following ranges:
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * 0x00000000 <= address < 0x00008000 (regular registers)
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * 0x00030000 <= address < 0x00034000 (RxRISC scratchpad)
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * 0x00034000 <= address < 0x00038000 (TxRISC scratchpad)
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * 0x00038000 <= address < 0x00038800 (RxRISC ROM)
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * Memory Window Base Address Register, 0x7c in PCI config space
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * Once this is set, accesses to the Memory Window Data Access Register
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * (0x84) refer to the word of NIC-local memory whose address is given
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * by this register. When used in this way, the whole of the address
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * written to this register is significant.
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * This register also provides the 32K-aligned base address for a 32K
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * region of NIC-local memory that the host can directly address in
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * the upper 32K of the 64K of PCI memory space allocated to the chip.
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * In this case, the bottom 15 bits of the register are ignored.
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * Note that the address written to the MWBAR should lie in the range
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * 0x00000000 <= address < 0x00020000. The rest of the range up to 1M
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * (i.e. 0x00200000 <= address < 0x01000000) would be valid if external
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * memory were present, but it's only supported on the 5700, not the
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * 5701/5703/5704.
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * The PCI express device control register and device status register
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * which are only applicable on BCM5751 and BCM5721.
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * Where to find things in NIC-local (on-chip) memory
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * Note: the (non-bogus) values below are appropriate for systems
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * without external memory. They would be different on a 5700 with
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * external memory.
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * Note: The higher send ring addresses and the mini ring shadow
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * buffer address are dummies - systems without external memory
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * are limited to 4 send rings and no mini receive ring.
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel#define NIC_MEM_SHADOW_SEND_RING(ring, nslots) (0x4000 + 4*(ring)*(nslots))
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * Put this in the GENCOMM port to tell the firmware not to run PXE
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * The remaining registers appear in the low 32K of regular
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * PCI Memory Address Space
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * All the state machine control registers below have at least a
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * <RESET> bit and an <ENABLE> bit as defined below. Some also
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * have an <ATTN_ENABLE> bit.
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * Other bits in some of the above state machine control registers
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * Transmit MAC Mode Register
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * (TRANSMIT_MAC_MODE_REG, 0x045c)
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * Receive MAC Mode Register
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * (RECEIVE_MAC_MODE_REG, 0x0468)
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * Receive BD Initiator Mode Register
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * (RCV_BD_INITIATOR_MODE_REG, 0x2c00)
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * Each of these bits controls whether ATTN is asserted
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * on a particular condition
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * Receive Data & Receive BD Initiator Mode Register
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * (RCV_DATA_BD_INITIATOR_MODE_REG, 0x2400)
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * Each of these bits controls whether ATTN is asserted
3d19cdae966d9ac4218dd9859640463bd7da19d8stevel * on a particular condition
#define MI_COMMS_DATA_SHIFT 0
#define MAC_HASH_4_REG 0x????
#define MAC_HASH_5_REG 0x????
#define MAC_HASH_6_REG 0x????
#define MAC_HASH_7_REG 0x????
#define MII_AUX_CTRL_NORMAL 0
#ifdef BGE_EXT_MEM
#ifdef _BIG_ENDIAN
} bge_rcb_t;
#ifdef _BIG_ENDIAN
} bge_sbd_t;
#ifdef _BIG_ENDIAN
} bge_rbd_t;
#ifdef _BIG_ENDIAN
} bge_status_t;
#ifdef _BIG_ENDIAN
#define STATUS_STD_BUFF_CONS_INDEX 0
#define STATUS_MINI_BUFF_CONS_INDEX 0
#ifdef __cplusplus