auxv_386.h revision d0f8ff6ee41946134faff06b3a9f643e21aefa78
2N/A/*
2N/A * CDDL HEADER START
2N/A *
2N/A * The contents of this file are subject to the terms of the
2N/A * Common Development and Distribution License (the "License").
2N/A * You may not use this file except in compliance with the License.
2N/A *
2N/A * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
2N/A * or http://www.opensolaris.org/os/licensing.
2N/A * See the License for the specific language governing permissions
2N/A * and limitations under the License.
2N/A *
2N/A * When distributing Covered Code, include this CDDL HEADER in each
2N/A * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
2N/A * If applicable, add the following below this CDDL HEADER, with the
2N/A * fields enclosed by brackets "[]" replaced with your own identifying
2N/A * information: Portions Copyright [yyyy] [name of copyright owner]
2N/A *
2N/A * CDDL HEADER END
2N/A */
2N/A/*
2N/A * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
2N/A * Use is subject to license terms.
2N/A */
2N/A
2N/A#ifndef _SYS_AUXV_386_H
2N/A#define _SYS_AUXV_386_H
2N/A
2N/A#pragma ident "%Z%%M% %I% %E% SMI"
2N/A
2N/A#ifdef __cplusplus
2N/Aextern "C" {
2N/A#endif
2N/A
2N/A/*
2N/A * Flags used in AT_SUN_HWCAP elements to describe various userland
2N/A * instruction set extensions available on different processors.
2N/A * The basic assumption is that of the i386 ABI; that is, i386 plus i387
2N/A * floating point.
2N/A *
2N/A * Note that if a given bit is set; the implication is that the kernel
2N/A * provides all the underlying architectural support for the correct
2N/A * functioning of the extended instruction(s).
2N/A */
2N/A#define AV_386_FPU 0x00001 /* x87-style floating point */
2N/A#define AV_386_TSC 0x00002 /* rdtsc insn */
2N/A#define AV_386_CX8 0x00004 /* cmpxchg8b insn */
2N/A#define AV_386_SEP 0x00008 /* sysenter and sysexit */
2N/A#define AV_386_AMD_SYSC 0x00010 /* AMD's syscall and sysret */
2N/A#define AV_386_CMOV 0x00020 /* conditional move insns */
2N/A#define AV_386_MMX 0x00040 /* MMX insns */
2N/A#define AV_386_AMD_MMX 0x00080 /* AMD's MMX insns */
2N/A#define AV_386_AMD_3DNow 0x00100 /* AMD's 3Dnow! insns */
2N/A#define AV_386_AMD_3DNowx 0x00200 /* AMD's 3Dnow! extended insns */
#define AV_386_FXSR 0x00400 /* fxsave and fxrstor */
#define AV_386_SSE 0x00800 /* SSE insns and regs */
#define AV_386_SSE2 0x01000 /* SSE2 insns and regs */
#define AV_386_PAUSE 0x02000 /* use pause insn (in spin loops) */
#define AV_386_SSE3 0x04000 /* SSE3 insns and regs */
#define AV_386_MON 0x08000 /* monitor/mwait insns */
#define AV_386_CX16 0x10000 /* cmpxchg16b insn */
#define AV_386_AHF 0x20000 /* lahf/sahf insns */
#define AV_386_TSCP 0x40000 /* rdtscp instruction */
#define AV_386_AMD_SSE4A 0x80000 /* AMD's SSE4A insns */
#define AV_386_POPCNT 0x100000 /* POPCNT insn */
#define AV_386_AMD_LZCNT 0x200000 /* AMD's LZCNT insn */
#define AV_386_SSSE3 0x400000 /* Intel SSSE3 insns */
#define AV_386_SSE4_1 0x800000 /* Intel SSE4.1 insns */
#define AV_386_SSE4_2 0x1000000 /* Intel SSE4.2 insns */
#define FMT_AV_386 \
"\20" \
"\31sse4.2" \
"\30sse4.1\27ssse3\26amd_lzcnt\25popcnt" \
"\24amd_sse4a\23tscp\22ahf\21cx16" \
"\20mon\17sse3\16pause\15sse2\14sse\13fxsr\12amd3dx\11amd3d" \
"\10amdmmx\7mmx\6cmov\5amdsysc\4sep\3cx8\2tsc\1fpu"
#ifdef __cplusplus
}
#endif
#endif /* !_SYS_AUXV_386_H */