xgehal-ring.c revision a23fd118e437af0a7877dd313db8fdaa3537c675
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright (c) 2002-2005 Neterion, Inc.
* All right Reserved.
*
* FileName : hal-ring.c
*
* Description: Rx ring object implementation
*
* Created: 10 May 2004
*/
#include "xgehal-ring.h"
#include "xgehal-device.h"
#if defined(XGE_OS_DMA_REQUIRES_SYNC) && defined(XGE_HAL_DMA_DTR_STREAMING)
static ptrdiff_t
void *item)
{
int memblock_idx;
void *memblock;
/* get owner memblock index */
/* get owner memblock by memblock index */
}
#endif
static dma_addr_t
{
int memblock_idx;
void *memblock;
/* get owner memblock index */
/* get owner memblock by memblock index */
/* get memblock DMA object by memblock index */
/* calculate offset in the memblock of this item */
}
static void
{
/* get "from" RxD block */
/* get "to" RxD block */
/* return address of the beginning of previous RxD block */
/* set next pointer for this RxD block to point on
* previous item's DMA start address */
/* return "from" RxD block's DMA start address */
from_dma =
#if defined(XGE_OS_DMA_REQUIRES_SYNC) && defined(XGE_HAL_DMA_DTR_STREAMING)
/* we must sync "from" RxD block, so hardware will see it */
sizeof(u64),
#endif
(unsigned long long)to_dma);
}
static xge_hal_status_e
void *memblock,
int memblock_index,
void *item,
int index,
int is_last,
void *userdata)
{
int i;
/* format rxds array */
void *rxdblock_priv;
int memblock_item_idx;
/* Note: memblock_item_idx is index of the item within
* the memblock. For instance, in case of three RxD-blocks
* per memblock this value can be 0,1 or 2. */
rxdp = (xge_hal_ring_rxd_1_t *)
rxd_priv = (xge_hal_ring_rxd_priv_t *) (void *)
/* pre-format per-RxD Ring's private */
#ifdef XGE_DEBUG_ASSERT
#endif
/* pre-format Host_Control */
#if defined(XGE_HAL_USE_5B_MODE)
#if defined(XGE_OS_PLATFORM_64BIT)
xge_assert(i <= 0xFFFF);
/* store memblock's index */
/* store index of memblock's private */
ring->rxds_per_block + i);
#else
/* 32-bit case */
#endif
} else {
/* 1b and 3b modes */
}
#else
/* 1b and 3b modes */
#endif
}
if (is_last) {
/* link last one with first one */
}
if (index > 0 ) {
/* link this RxD block with previous one */
}
return XGE_HAL_OK;
}
{
while (__hal_channel_dtr_count(channel) > 0) {
reopen);
if (status != XGE_HAL_OK) {
return status;
}
}
}
return XGE_HAL_OK;
}
{
/* Note: at this point we have channel.devh and channel.pdev
* pre-set only! */
#if defined(XGE_HAL_RX_MULTI_RESERVE)
#elif defined(XGE_HAL_RX_MULTI_RESERVE_IRQ)
#endif
#if defined(XGE_HAL_RX_MULTI_POST)
#elif defined(XGE_HAL_RX_MULTI_POST_IRQ)
#endif
/* how many RxDs can fit into one block. Depends on configured
* buffer_mode. */
/* calculate actual RxD block private size */
return XGE_HAL_ERR_OUT_OF_MEMORY;
}
NULL, /* nothing to free */
ring);
return XGE_HAL_ERR_OUT_OF_MEMORY;
}
attr,
0 /* no threshold for ring! */);
if (status != XGE_HAL_OK) {
return status;
}
/* sanity check that everything formatted ok */
/* Note:
* Specifying dtr_init callback means two things:
* 1) dtrs need to be initialized by ULD at channel-open time;
* 2) dtrs need to be posted at channel-open time
* (that's what the initial_replenish() below does)
* Currently we don't have a case when the 1) is done without the 2).
*/
!= XGE_HAL_OK) {
return status;
}
}
return XGE_HAL_OK;
}
void
{
#if defined(XGE_HAL_RX_MULTI_RESERVE)||defined(XGE_HAL_RX_MULTI_RESERVE_IRQ)||\
defined(XGE_HAL_RX_MULTI_POST) || defined(XGE_HAL_RX_MULTI_POST_IRQ)
#endif
}
if (ring->reserved_rxds_arr) {
}
#if defined(XGE_HAL_RX_MULTI_RESERVE)
#elif defined(XGE_HAL_RX_MULTI_RESERVE_IRQ)
#endif
#if defined(XGE_HAL_RX_MULTI_POST)
#elif defined(XGE_HAL_RX_MULTI_POST_IRQ)
#endif
}
void
{
void *first_block;
int block_num;
bar0 = (xge_hal_pci_bar0_t *) (void *)
/* last block in fact becomes first. This is just the way it
* is filled up and linked by item_alloc() */
}
/* Beware: no snoop by the bridge if (no_snoop_bits) */
/* Herc: always use group_reads */
/* Configure Receive Protocol Assist */
/* Clean STRIP_VLAN_TAG bit and set as config from upper layer */
}
void
{
bar0 = (xge_hal_pci_bar0_t *) (void *)
}
void
{
int i, j;
/* Rx DMA intialization. */
val64 = 0;
for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++) {
continue;
(5 + (i * 8)), 3);
}
(unsigned long long)val64);
/* Configuring ring queues according to per-ring configuration */
val64 = 0;
for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++) {
continue;
}
&bar0->rx_queue_cfg);
(unsigned long long)val64);
/* Activate Rx steering */
&bar0->rts_qos_steering);
for (j = 0; j < 8 /* QoS max */; j++) {
for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++) {
continue;
}
}
&bar0->rts_qos_steering);
(unsigned long long)val64);
/* Note: If a queue does not exist, it should be assigned a maximum
* length of zero. Otherwise, packet loss could occur.
* P. 4-4 User guide.
*
* All configured rings will be properly set at device open time
* by utilizing device_mtu_set() API call. */
for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++) {
continue;
&bar0->rts_frm_len_n[i]);
}
#ifdef XGE_HAL_HERC_EMULATION
val64 |= 0x0000000000010000;
val64 |= 0x003a000000000000;
xge_os_mdelay(2000);
#endif
/* now enabling MC-RLDRAM after setting MC_QUEUE sizes */
&bar0->mc_rldram_mrs);
&bar0->mc_rldram_mrs);
xge_os_wmb();
&bar0->mc_rldram_mrs);
/* RLDRAM initialization procedure require 500us to complete */
xge_os_mdelay(1);
/* Temporary fixes for Herc RLDRAM */
(unsigned long long)val64);
val64 = 0x0003570003010300ULL;
xge_os_mdelay(1);
}
}
void
{
int i;
for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++) {
continue;
&bar0->rts_frm_len_n[i]);
} else {
&bar0->rts_frm_len_n[i]);
}
}
}