xgehal-ring.c revision 8347601bcb0a439f6e50fc36b4039a73d08700e1
a23fd118e437af0a7877dd313db8fdaa3537c675yl * CDDL HEADER START
a23fd118e437af0a7877dd313db8fdaa3537c675yl * The contents of this file are subject to the terms of the
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Common Development and Distribution License (the "License").
a23fd118e437af0a7877dd313db8fdaa3537c675yl * You may not use this file except in compliance with the License.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
a23fd118e437af0a7877dd313db8fdaa3537c675yl * See the License for the specific language governing permissions
a23fd118e437af0a7877dd313db8fdaa3537c675yl * and limitations under the License.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * When distributing Covered Code, include this CDDL HEADER in each
a23fd118e437af0a7877dd313db8fdaa3537c675yl * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
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a23fd118e437af0a7877dd313db8fdaa3537c675yl * information: Portions Copyright [yyyy] [name of copyright owner]
a23fd118e437af0a7877dd313db8fdaa3537c675yl * CDDL HEADER END
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * Copyright (c) 2002-2006 Neterion, Inc.
a23fd118e437af0a7877dd313db8fdaa3537c675yl#if defined(XGE_OS_DMA_REQUIRES_SYNC) && defined(XGE_HAL_DMA_DTR_STREAMING)
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* get owner memblock index */
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* get owner memblock by memblock index */
a23fd118e437af0a7877dd313db8fdaa3537c675yl memblock = __hal_mempool_memblock(mempoolh, memblock_idx);
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_ring_item_dma_addr(xge_hal_mempool_h mempoolh, void *item,
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* get owner memblock index */
8347601bcb0a439f6e50fc36b4039a73d08700e1yl memblock_idx = __hal_ring_block_memblock_idx((xge_hal_ring_block_t *) item);
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* get owner memblock by memblock index */
8347601bcb0a439f6e50fc36b4039a73d08700e1yl memblock = __hal_mempool_memblock((xge_hal_mempool_t *) mempoolh,
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* get memblock DMA object by memblock index */
8347601bcb0a439f6e50fc36b4039a73d08700e1yl __hal_mempool_memblock_dma((xge_hal_mempool_t *) mempoolh,
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* calculate offset in the memblock of this item */
a23fd118e437af0a7877dd313db8fdaa3537c675ylstatic void
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* get "from" RxD block */
8347601bcb0a439f6e50fc36b4039a73d08700e1yl __hal_mempool_item((xge_hal_mempool_t *) mempoolh, from);
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* get "to" RxD block */
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* return address of the beginning of previous RxD block */
a23fd118e437af0a7877dd313db8fdaa3537c675yl to_dma = __hal_ring_item_dma_addr(mempoolh, to_item, &to_dma_handle);
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* set next pointer for this RxD block to point on
a23fd118e437af0a7877dd313db8fdaa3537c675yl * previous item's DMA start address */
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* return "from" RxD block's DMA start address */
a23fd118e437af0a7877dd313db8fdaa3537c675yl __hal_ring_item_dma_addr(mempoolh, from_item, &from_dma_handle);
a23fd118e437af0a7877dd313db8fdaa3537c675yl#if defined(XGE_OS_DMA_REQUIRES_SYNC) && defined(XGE_HAL_DMA_DTR_STREAMING)
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* we must sync "from" RxD block, so hardware will see it */
8347601bcb0a439f6e50fc36b4039a73d08700e1yl xge_debug_ring(XGE_TRACE, "block%d:0x"XGE_OS_LLXFMT" => block%d:0x"XGE_OS_LLXFMT,
a23fd118e437af0a7877dd313db8fdaa3537c675yl (unsigned long long)to_dma);
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* format rxds array */
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* Note: memblock_item_idx is index of the item within
a23fd118e437af0a7877dd313db8fdaa3537c675yl * the memblock. For instance, in case of three RxD-blocks
a23fd118e437af0a7877dd313db8fdaa3537c675yl * per memblock this value can be 0,1 or 2. */
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* pre-format per-RxD Ring's private */
a23fd118e437af0a7877dd313db8fdaa3537c675yl rxd_priv->dma_addr = dma_object->addr + rxd_priv->dma_offset;
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* pre-format Host_Control */
a23fd118e437af0a7877dd313db8fdaa3537c675yl if (ring->buffer_mode == XGE_HAL_RING_QUEUE_BUFFER_MODE_5) {
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_ring_rxd_5_t *rxdp_5 = (xge_hal_ring_rxd_5_t *)rxdp;
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* store memblock's index */
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* store index of memblock's private */
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* 32-bit case */
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* 1b and 3b modes */
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* 1b and 3b modes */
8347601bcb0a439f6e50fc36b4039a73d08700e1yl __hal_ring_block_memblock_idx_set((xge_hal_ring_block_t *) item, memblock_index);
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* link last one with first one */
a23fd118e437af0a7877dd313db8fdaa3537c675yl if (index > 0 ) {
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* link this RxD block with previous one */
a23fd118e437af0a7877dd313db8fdaa3537c675yl __hal_ring_rxdblock_link(mempoolh, ring, index, index-1);
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_ring_open(xge_hal_channel_h channelh, xge_hal_channel_attr_t *attr)
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* Note: at this point we have channel.devh and channel.pdev
a23fd118e437af0a7877dd313db8fdaa3537c675yl * pre-set only! */
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_os_spin_lock_init(&ring->channel.reserve_lock, hldev->pdev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_os_spin_lock_init_irq(&ring->channel.reserve_lock, hldev->irqh);
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_os_spin_lock_init(&ring->channel.post_lock, hldev->pdev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_os_spin_lock_init_irq(&ring->channel.post_lock, hldev->irqh);
a23fd118e437af0a7877dd313db8fdaa3537c675yl ring->rxd_size = XGE_HAL_RING_RXD_SIZEOF(queue->buffer_mode);
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* how many RxDs can fit into one block. Depends on configured
a23fd118e437af0a7877dd313db8fdaa3537c675yl * buffer_mode. */
a23fd118e437af0a7877dd313db8fdaa3537c675yl ring->rxds_per_block = XGE_HAL_RING_RXDS_PER_BLOCK(queue->buffer_mode);
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* calculate actual RxD block private size */
a23fd118e437af0a7877dd313db8fdaa3537c675yl ring->rxdblock_priv_size = ring->rxd_priv_size * ring->rxds_per_block;
8347601bcb0a439f6e50fc36b4039a73d08700e1yl ring->reserved_rxds_arr = (void **) xge_os_malloc(ring->channel.pdev,
a23fd118e437af0a7877dd313db8fdaa3537c675yl 0 /* no threshold for ring! */);
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* sanity check that everything formatted ok */
a23fd118e437af0a7877dd313db8fdaa3537c675yl (ring->rxds_per_block * ring->rxd_size - ring->rxd_size));
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Specifying dtr_init callback means two things:
a23fd118e437af0a7877dd313db8fdaa3537c675yl * 1) dtrs need to be initialized by ULD at channel-open time;
a23fd118e437af0a7877dd313db8fdaa3537c675yl * 2) dtrs need to be posted at channel-open time
a23fd118e437af0a7877dd313db8fdaa3537c675yl * (that's what the initial_replenish() below does)
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Currently we don't have a case when the 1) is done without the 2).
8347601bcb0a439f6e50fc36b4039a73d08700e1yl /* initial replenish will increment the counter in its post() routine,
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * we have to reset it */
a23fd118e437af0a7877dd313db8fdaa3537c675yl#if defined(XGE_HAL_RX_MULTI_RESERVE)||defined(XGE_HAL_RX_MULTI_RESERVE_IRQ)||\
a23fd118e437af0a7877dd313db8fdaa3537c675yl defined(XGE_HAL_RX_MULTI_POST) || defined(XGE_HAL_RX_MULTI_POST_IRQ)
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_device_t *hldev = (xge_hal_device_t *)ring->channel.devh;
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_os_spin_lock_destroy(&ring->channel.reserve_lock, hldev->pdev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_os_spin_lock_destroy_irq(&ring->channel.reserve_lock, hldev->pdev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_os_spin_lock_destroy(&ring->channel.post_lock, hldev->pdev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_os_spin_lock_destroy_irq(&ring->channel.post_lock, hldev->pdev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_device_t *hldev = (xge_hal_device_t *)ring->channel.devh;
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* last block in fact becomes first. This is just the way it
a23fd118e437af0a7877dd313db8fdaa3537c675yl * is filled up and linked by item_alloc() */
a23fd118e437af0a7877dd313db8fdaa3537c675yl first_block = __hal_mempool_item(ring->mempool, block_num - 1);
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_os_pio_mem_write64(ring->channel.pdev, ring->channel.regh0,
8347601bcb0a439f6e50fc36b4039a73d08700e1yl xge_debug_ring(XGE_TRACE, "ring%d PRC DMA addr 0x"XGE_OS_LLXFMT" initialized",
a23fd118e437af0a7877dd313db8fdaa3537c675yl ring->channel.regh0, &bar0->prc_ctrl_n[ring->channel.post_qid]);
a23fd118e437af0a7877dd313db8fdaa3537c675yl if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC &&
a23fd118e437af0a7877dd313db8fdaa3537c675yl val64 |= vBIT((queue->buffer_mode >> 1),14,2);/* 1,3 or 5 => 0,1 or 2 */
a23fd118e437af0a7877dd313db8fdaa3537c675yl val64 &= ~XGE_HAL_PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
a23fd118e437af0a7877dd313db8fdaa3537c675yl (hldev->config.pci_freq_mherz * queue->backoff_interval_us));
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* Beware: no snoop by the bridge if (no_snoop_bits) */
a23fd118e437af0a7877dd313db8fdaa3537c675yl val64 |= XGE_HAL_PRC_CTRL_NO_SNOOP(queue->no_snoop_bits);
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* Herc: always use group_reads */
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_os_pio_mem_write64(ring->channel.pdev, ring->channel.regh0,
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* Configure Receive Protocol Assist */
a23fd118e437af0a7877dd313db8fdaa3537c675yl val64 |= XGE_HAL_RX_PA_CFG_SCATTER_MODE(ring->config->scatter_mode);
a23fd118e437af0a7877dd313db8fdaa3537c675yl val64 |= (XGE_HAL_RX_PA_CFG_IGNORE_SNAP_OUI | XGE_HAL_RX_PA_CFG_IGNORE_LLC_CTRL);
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* Clean STRIP_VLAN_TAG bit and set as config from upper layer */
a23fd118e437af0a7877dd313db8fdaa3537c675yl val64 |= XGE_HAL_RX_PA_CFG_STRIP_VLAN_TAG_MODE(ring->config->strip_vlan_tag);
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_os_pio_mem_write64(ring->channel.pdev, ring->channel.regh0,
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_debug_ring(XGE_TRACE, "ring%d enabled in buffer_mode %d",
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_os_pio_mem_write64(ring->channel.pdev, ring->channel.regh0,
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* Rx DMA intialization. */
a23fd118e437af0a7877dd313db8fdaa3537c675yl for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++) {
8347601bcb0a439f6e50fc36b4039a73d08700e1yl xge_debug_ring(XGE_TRACE, "Rings priority configured to 0x"XGE_OS_LLXFMT,
a23fd118e437af0a7877dd313db8fdaa3537c675yl (unsigned long long)val64);
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* Configuring ring queues according to per-ring configuration */
a23fd118e437af0a7877dd313db8fdaa3537c675yl for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++) {
a23fd118e437af0a7877dd313db8fdaa3537c675yl val64 |= vBIT(hldev->config.ring.queue[i].dram_size_mb,(i*8),8);
8347601bcb0a439f6e50fc36b4039a73d08700e1yl xge_debug_ring(XGE_TRACE, "DRAM configured to 0x"XGE_OS_LLXFMT,
a23fd118e437af0a7877dd313db8fdaa3537c675yl (unsigned long long)val64);
8347601bcb0a439f6e50fc36b4039a73d08700e1yl /* Activate Rx steering */
8347601bcb0a439f6e50fc36b4039a73d08700e1yl for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++)
8347601bcb0a439f6e50fc36b4039a73d08700e1yl xge_debug_ring(XGE_TRACE, "QoS steering configured to 0x"XGE_OS_LLXFMT,
8347601bcb0a439f6e50fc36b4039a73d08700e1yl (unsigned long long)val64);
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* Note: If a queue does not exist, it should be assigned a maximum
a23fd118e437af0a7877dd313db8fdaa3537c675yl * length of zero. Otherwise, packet loss could occur.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * P. 4-4 User guide.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * All configured rings will be properly set at device open time
a23fd118e437af0a7877dd313db8fdaa3537c675yl * by utilizing device_mtu_set() API call. */
a23fd118e437af0a7877dd313db8fdaa3537c675yl for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++) {
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* now enabling MC-RLDRAM after setting MC_QUEUE sizes */
a23fd118e437af0a7877dd313db8fdaa3537c675yl __hal_pio_mem_write32_upper(hldev->pdev, hldev->regh0, (u32)(val64>>32),
a23fd118e437af0a7877dd313db8fdaa3537c675yl __hal_pio_mem_write32_lower(hldev->pdev, hldev->regh0, (u32)val64,
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* RLDRAM initialization procedure require 500us to complete */
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* Temporary fixes for Herc RLDRAM */
a23fd118e437af0a7877dd313db8fdaa3537c675yl if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC) {
8347601bcb0a439f6e50fc36b4039a73d08700e1yl xge_debug_ring(XGE_TRACE, "default mc_rldram_mrs_herc 0x"XGE_OS_LLXFMT,
a23fd118e437af0a7877dd313db8fdaa3537c675yl (unsigned long long)val64);
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_debug_ring(XGE_TRACE, "%s", "ring channels initialized");
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
a23fd118e437af0a7877dd313db8fdaa3537c675yl for (i = 0; i < XGE_HAL_MAX_RING_NUM; i++) {