a23fd118e437af0a7877dd313db8fdaa3537c675yl * CDDL HEADER START
a23fd118e437af0a7877dd313db8fdaa3537c675yl * The contents of this file are subject to the terms of the
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Common Development and Distribution License (the "License").
a23fd118e437af0a7877dd313db8fdaa3537c675yl * You may not use this file except in compliance with the License.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
a23fd118e437af0a7877dd313db8fdaa3537c675yl * See the License for the specific language governing permissions
a23fd118e437af0a7877dd313db8fdaa3537c675yl * and limitations under the License.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * When distributing Covered Code, include this CDDL HEADER in each
a23fd118e437af0a7877dd313db8fdaa3537c675yl * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * If applicable, add the following below this CDDL HEADER, with the
a23fd118e437af0a7877dd313db8fdaa3537c675yl * fields enclosed by brackets "[]" replaced with your own identifying
a23fd118e437af0a7877dd313db8fdaa3537c675yl * information: Portions Copyright [yyyy] [name of copyright owner]
a23fd118e437af0a7877dd313db8fdaa3537c675yl * CDDL HEADER END
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * Copyright (c) 2002-2006 Neterion, Inc.
a23fd118e437af0a7877dd313db8fdaa3537c675yl/* HW ring configuration */
a23fd118e437af0a7877dd313db8fdaa3537c675yl/* control_1 and control_2 formatting - same for all buffer modes */
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_RXD_GET_L3_CKSUM(control_1) ((u16)(control_1>>16) & 0xFFFF)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_RXD_GET_L4_CKSUM(control_1) ((u16)(control_1 & 0xFFFF))
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_RXD_SET_VLAN_TAG(control_2, val) control_2 |= (u16)val
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_RXD_GET_VLAN_TAG(control_2) ((u16)(control_2 & 0xFFFF))
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_RXD_POSTED_4_XFRAME BIT(7) /* control_1 */
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_RXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15))
a23fd118e437af0a7877dd313db8fdaa3537c675yl (u8)(0x3 & ((control_1 & XGE_HAL_RXD_MASK_FRAME_TYPE) >> 37))
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_RXD_FRAME_TCP_OR_UDP (XGE_HAL_RXD_FRAME_PROTO_TCP | \
a23fd118e437af0a7877dd313db8fdaa3537c675yl * enum xge_hal_frame_type_e - Ethernet frame format.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_FRAME_TYPE_DIX: DIX (Ethernet II) format.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_FRAME_TYPE_LLC: LLC format.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_FRAME_TYPE_SNAP: SNAP format.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_FRAME_TYPE_IPX: IPX format.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Ethernet frame format.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * enum xge_hal_frame_proto_e - Higher-layer ethernet protocols.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_FRAME_PROTO_VLAN_TAGGED: VLAN.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_FRAME_PROTO_IPV4: IPv4.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_FRAME_PROTO_IPV6: IPv6.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_FRAME_PROTO_IP_FRAGMENTED: IP fragmented.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_FRAME_PROTO_TCP: TCP.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_FRAME_PROTO_UDP: UDP.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @XGE_HAL_FRAME_PROTO_TCP_OR_UDP: TCP or UDP.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Higher layer ethernet protocols and options.
a23fd118e437af0a7877dd313db8fdaa3537c675yl XGE_HAL_FRAME_PROTO_TCP_OR_UDP = (XGE_HAL_FRAME_PROTO_TCP | \
a23fd118e437af0a7877dd313db8fdaa3537c675yl * xge_hal_ring_rxd_1_t
a23fd118e437af0a7877dd313db8fdaa3537c675yltypedef struct {
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_RXD_1_SET_BUFFER0_SIZE(val) vBIT(val,0,16)
a23fd118e437af0a7877dd313db8fdaa3537c675yl * xge_hal_ring_rxd_3_t
a23fd118e437af0a7877dd313db8fdaa3537c675yltypedef struct {
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_RXD_3_MASK_BUFFER1_SIZE vBIT(0xFFFF,16,16)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_RXD_3_SET_BUFFER1_SIZE(val) vBIT(val,16,16)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_RXD_3_MASK_BUFFER2_SIZE vBIT(0xFFFF,32,16)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_RXD_3_SET_BUFFER2_SIZE(val) vBIT(val,32,16)
a23fd118e437af0a7877dd313db8fdaa3537c675yl * xge_hal_ring_rxd_5_t
a23fd118e437af0a7877dd313db8fdaa3537c675yltypedef struct {
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_RXD_5_MASK_BUFFER3_SIZE vBIT(0xFFFF,32,16)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_RXD_5_SET_BUFFER3_SIZE(val) vBIT(val,32,16)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_RXD_5_MASK_BUFFER4_SIZE vBIT(0xFFFF,48,16)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_RXD_5_SET_BUFFER4_SIZE(val) vBIT(val,48,16)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_RXD_5_SET_BUFFER0_SIZE(val) vBIT(val,0,16)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_RXD_5_MASK_BUFFER1_SIZE vBIT(0xFFFF,16,16)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_RXD_5_SET_BUFFER1_SIZE(val) vBIT(val,16,16)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_RXD_5_MASK_BUFFER2_SIZE vBIT(0xFFFF,32,16)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_RXD_5_SET_BUFFER2_SIZE(val) vBIT(val,32,16)
a23fd118e437af0a7877dd313db8fdaa3537c675yltypedef u8 xge_hal_ring_block_t[XGE_HAL_RING_RXDBLOCK_SIZE];
a23fd118e437af0a7877dd313db8fdaa3537c675yl * struct xge_hal_ring_rxd_priv_t - Receive descriptor HAL-private data.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @dma_addr: DMA (mapped) address of _this_ descriptor.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @dma_handle: DMA handle used to map the descriptor onto device.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @dma_offset: Descriptor's offset in the memory block. HAL allocates
a23fd118e437af0a7877dd313db8fdaa3537c675yl * descriptors in memory blocks of
a23fd118e437af0a7877dd313db8fdaa3537c675yl * %XGE_HAL_RING_RXDBLOCK_SIZE
a23fd118e437af0a7877dd313db8fdaa3537c675yl * bytes. Each memblock is contiguous DMA-able memory. Each
a23fd118e437af0a7877dd313db8fdaa3537c675yl * memblock contains 1 or more 4KB RxD blocks visible to the
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Xframe hardware.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @dma_object: DMA address and handle of the memory block that contains
a23fd118e437af0a7877dd313db8fdaa3537c675yl * the descriptor. This member is used only in the "checked"
a23fd118e437af0a7877dd313db8fdaa3537c675yl * version of the HAL (to enforce certain assertions);
a23fd118e437af0a7877dd313db8fdaa3537c675yl * otherwise it gets compiled out.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @allocated: True if the descriptor is reserved, 0 otherwise. Internal usage.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Per-receive decsriptor HAL-private data. HAL uses the space to keep DMA
a23fd118e437af0a7877dd313db8fdaa3537c675yl * information associated with the descriptor. Note that ULD can ask HAL
a23fd118e437af0a7877dd313db8fdaa3537c675yl * to allocate additional per-descriptor space for its own (ULD-specific)
a23fd118e437af0a7877dd313db8fdaa3537c675yl * purposes.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * struct xge_hal_ring_t - Ring channel.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @channel: Channel "base" of this ring, the common part of all HAL
a23fd118e437af0a7877dd313db8fdaa3537c675yl * channels.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @buffer_mode: 1, 3, or 5. The value specifies a receive buffer mode,
a23fd118e437af0a7877dd313db8fdaa3537c675yl * as per Xframe User Guide.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @indicate_max_pkts: Maximum number of packets processed within a single
a23fd118e437af0a7877dd313db8fdaa3537c675yl * interrupt. Can be used to limit the time spent inside hw
a23fd118e437af0a7877dd313db8fdaa3537c675yl * interrupt.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @config: Ring configuration, part of device configuration
a23fd118e437af0a7877dd313db8fdaa3537c675yl * (see xge_hal_device_config_t{}).
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @rxd_size: RxD sizes for 1-, 3- or 5- buffer modes. As per Xframe spec,
a23fd118e437af0a7877dd313db8fdaa3537c675yl * 1-buffer mode descriptor is 32 byte long, etc.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @rxd_priv_size: Per RxD size reserved (by HAL) for ULD to keep per-descriptor
a23fd118e437af0a7877dd313db8fdaa3537c675yl * data (e.g., DMA handle for Solaris)
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @rxds_per_block: Number of descriptors per hardware-defined RxD
a23fd118e437af0a7877dd313db8fdaa3537c675yl * block. Depends on the (1-,3-,5-) buffer mode.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @mempool: Memory pool, the pool from which descriptors get allocated.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @rxdblock_priv_size: Reserved at the end of each RxD block. HAL internal
a23fd118e437af0a7877dd313db8fdaa3537c675yl * usage. Not to confuse with @rxd_priv_size.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @reserved_rxds_arr: Array of RxD pointers. At any point in time each
a23fd118e437af0a7877dd313db8fdaa3537c675yl * entry in this array is available for allocation
a23fd118e437af0a7877dd313db8fdaa3537c675yl * (via xge_hal_ring_dtr_reserve()) and posting.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @cmpl_cnt: Completion counter. Is reset to zero upon entering the ISR.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Used in conjunction with @indicate_max_pkts.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Ring channel.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Note: The structure is cache line aligned to better utilize
a23fd118e437af0a7877dd313db8fdaa3537c675yl * CPU cache performance.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * struct xge_hal_dtr_info_t - Extended information associated with a
a23fd118e437af0a7877dd313db8fdaa3537c675yl * completed ring descriptor.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @l3_cksum: Result of IP checksum check (by Xframe hardware).
a23fd118e437af0a7877dd313db8fdaa3537c675yl * This field containing XGE_HAL_L3_CKSUM_OK would mean that
a23fd118e437af0a7877dd313db8fdaa3537c675yl * the checksum is correct, otherwise - the datagram is
a23fd118e437af0a7877dd313db8fdaa3537c675yl * corrupted.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @l4_cksum: Result of TCP/UDP checksum check (by Xframe hardware).
a23fd118e437af0a7877dd313db8fdaa3537c675yl * This field containing XGE_HAL_L4_CKSUM_OK would mean that
a23fd118e437af0a7877dd313db8fdaa3537c675yl * the checksum is correct. Otherwise - the packet is
a23fd118e437af0a7877dd313db8fdaa3537c675yl * corrupted.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @frame: See xge_hal_frame_type_e{}.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @proto: Reporting bits for various higher-layer protocols, including (but
a23fd118e437af0a7877dd313db8fdaa3537c675yl * note restricted to) TCP and UDP. See xge_hal_frame_proto_e{}.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @vlan: VLAN tag extracted from the received frame.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @rth_value: Receive Traffic Hashing(RTH) hash value. Produced by Xframe II
a23fd118e437af0a7877dd313db8fdaa3537c675yl * hardware if RTH is enabled.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @rth_it_hit: Set, If RTH hash value calculated by the Xframe II hardware
a23fd118e437af0a7877dd313db8fdaa3537c675yl * has a matching entry in the Indirection table.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @rth_spdm_hit: Set, If RTH hash value calculated by the Xframe II hardware
a23fd118e437af0a7877dd313db8fdaa3537c675yl * has a matching entry in the Socket Pair Direct Match table.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @rth_hash_type: RTH hash code of the function used to calculate the hash.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @reserved_pad: Unused byte.
a23fd118e437af0a7877dd313db8fdaa3537c675yl int frame; /* zero or more of xge_hal_frame_type_e flags */
a23fd118e437af0a7877dd313db8fdaa3537c675yl int proto; /* zero or more of xge_hal_frame_proto_e flags */
a23fd118e437af0a7877dd313db8fdaa3537c675yl/* ========================== RING PRIVATE API ============================ */
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_status_e __hal_ring_open(xge_hal_channel_h channelh,
a23fd118e437af0a7877dd313db8fdaa3537c675ylvoid __hal_ring_mtu_set(xge_hal_device_h devh, int new_mtu);
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_status_e __hal_ring_initial_replenish(xge_hal_channel_t *channel,
a23fd118e437af0a7877dd313db8fdaa3537c675yl#if defined(XGE_DEBUG_FP) && (XGE_DEBUG_FP & XGE_DEBUG_FP_RING)
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_ring_block_memblock_idx(xge_hal_ring_block_t *block);
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_ring_block_memblock_idx_set(xge_hal_ring_block_t*block, int memblock_idx);
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_ring_block_next_pointer(xge_hal_ring_block_t *block);
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_ring_block_next_pointer_set(xge_hal_ring_block_t*block,
a23fd118e437af0a7877dd313db8fdaa3537c675yl__HAL_STATIC_RING __HAL_INLINE_RING xge_hal_ring_rxd_priv_t*
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_ring_rxd_priv(xge_hal_ring_t *ring, xge_hal_dtr_h dtrh);
a23fd118e437af0a7877dd313db8fdaa3537c675yl/* =========================== RING PUBLIC API ============================ */
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_ring_dtr_reserve(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh);
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_ring_dtr_private(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_ring_dtr_1b_set(xge_hal_dtr_h dtrh, dma_addr_t dma_pointer, int size);
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_ring_dtr_info_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_ring_dtr_1b_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_ring_dtr_3b_set(xge_hal_dtr_h dtrh, dma_addr_t dma_pointers[],
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_ring_dtr_3b_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_ring_dtr_5b_set(xge_hal_dtr_h dtrh, dma_addr_t dma_pointers[],
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_ring_dtr_5b_get(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_ring_dtr_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_ring_dtr_pre_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_ring_dtr_post_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
7eced415e5dd557aef2d78483b5a7785f0e13670xwxge_hal_ring_dtr_post_post_wmb(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_ring_dtr_next_completed(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh,
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_ring_dtr_free(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
8347601bcb0a439f6e50fc36b4039a73d08700e1ylxge_hal_ring_is_next_dtr_completed(xge_hal_channel_h channelh);
a23fd118e437af0a7877dd313db8fdaa3537c675yl#else /* XGE_FASTPATH_EXTERN */
a23fd118e437af0a7877dd313db8fdaa3537c675yl#endif /* XGE_FASTPATH_INLINE */
a23fd118e437af0a7877dd313db8fdaa3537c675yl#endif /* XGE_HAL_RING_H */