a23fd118e437af0a7877dd313db8fdaa3537c675yl * CDDL HEADER START
a23fd118e437af0a7877dd313db8fdaa3537c675yl * The contents of this file are subject to the terms of the
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Common Development and Distribution License (the "License").
a23fd118e437af0a7877dd313db8fdaa3537c675yl * You may not use this file except in compliance with the License.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
a23fd118e437af0a7877dd313db8fdaa3537c675yl * See the License for the specific language governing permissions
a23fd118e437af0a7877dd313db8fdaa3537c675yl * and limitations under the License.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * When distributing Covered Code, include this CDDL HEADER in each
a23fd118e437af0a7877dd313db8fdaa3537c675yl * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * If applicable, add the following below this CDDL HEADER, with the
a23fd118e437af0a7877dd313db8fdaa3537c675yl * fields enclosed by brackets "[]" replaced with your own identifying
a23fd118e437af0a7877dd313db8fdaa3537c675yl * information: Portions Copyright [yyyy] [name of copyright owner]
a23fd118e437af0a7877dd313db8fdaa3537c675yl * CDDL HEADER END
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * Copyright (c) 2002-2006 Neterion, Inc.
a23fd118e437af0a7877dd313db8fdaa3537c675yl/* HW fifo configuration */
7eced415e5dd557aef2d78483b5a7785f0e13670xw/* HW FIFO Weight Calender */
a23fd118e437af0a7877dd313db8fdaa3537c675yl * xge_hal_fifo_hw_pair_t
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Represent a single fifo in the BAR1 memory space.
a23fd118e437af0a7877dd313db8fdaa3537c675yltypedef struct {
a23fd118e437af0a7877dd313db8fdaa3537c675yl/* Bad TxDL transfer codes */
a23fd118e437af0a7877dd313db8fdaa3537c675yl * struct xge_hal_fifo_txd_t - TxD.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @control_1: Control_1.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @control_2: Control_2.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @buffer_pointer: Buffer_Address.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @host_control: Host_Control.Opaque 64bit data stored by ULD inside the Xframe
a23fd118e437af0a7877dd313db8fdaa3537c675yl * descriptor prior to posting the latter on the channel
a23fd118e437af0a7877dd313db8fdaa3537c675yl * via xge_hal_fifo_dtr_post() or xge_hal_ring_dtr_post().
a23fd118e437af0a7877dd313db8fdaa3537c675yl * The %host_control is returned as is to the ULD with each
a23fd118e437af0a7877dd313db8fdaa3537c675yl * completed descriptor.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Transmit descriptor (TxD).Fifo descriptor contains configured number
a23fd118e437af0a7877dd313db8fdaa3537c675yl * (list) of TxDs. * For more details please refer to Xframe User Guide,
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Section 5.4.2 "Transmit Descriptor (TxD) Format".
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_TXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15))
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_GET_TXD_T_CODE(val) ((val & XGE_HAL_TXD_T_CODE)>>48)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_SET_TXD_T_CODE(x, val) (x |= (((u64)val & 0xF) << 48))
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGE_HAL_TXD_GET_LSO_BYTES_SENT(val) ((val & vBIT(0xFFFF,16,16))>>32)
a23fd118e437af0a7877dd313db8fdaa3537c675yl * struct xge_hal_fifo_t - Fifo channel.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @channel: Channel "base" of this fifo, the common part of all HAL
a23fd118e437af0a7877dd313db8fdaa3537c675yl * channels.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @post_lock_ptr: Points to a lock that serializes (pointer, control) PIOs.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Note that for Xena the serialization is done across all device
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @hw_pair: Per-fifo (Pointer, Control) pair used to send descriptors to the
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Xframe hardware (for details see Xframe user guide).
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @config: Fifo configuration, part of device configuration
a23fd118e437af0a7877dd313db8fdaa3537c675yl * (see xge_hal_device_config_t{}).
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @no_snoop_bits: See xge_hal_fifo_config_t{}.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @txdl_per_memblock: Number of TxDLs (TxD lists) per memblock.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * on TxDL please refer to Xframe UG.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @interrupt_type: FIXME: to-be-defined.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @txdl_size: Configured TxDL size (i.e., number of TxDs in a list), plus
a23fd118e437af0a7877dd313db8fdaa3537c675yl * per-TxDL HAL private space (xge_hal_fifo_txdl_priv_t).
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @priv_size: Per-Tx descriptor space reserved for upper-layer driver
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @mempool: Memory pool, from which descriptors get allocated.
7eced415e5dd557aef2d78483b5a7785f0e13670xw * @align_size: TBD
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Fifo channel.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Note: The structure is cache line aligned.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * struct xge_hal_fifo_txdl_priv_t - Transmit descriptor HAL-private
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @dma_addr: DMA (mapped) address of _this_ descriptor.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @dma_handle: DMA handle used to map the descriptor onto device.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @dma_offset: Descriptor's offset in the memory block. HAL allocates
a23fd118e437af0a7877dd313db8fdaa3537c675yl * descriptors in memory blocks (see
a23fd118e437af0a7877dd313db8fdaa3537c675yl * xge_hal_fifo_config_t{})
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Each memblock is a contiguous block of DMA-able memory.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @frags: Total number of fragments (that is, contiguous data buffers)
a23fd118e437af0a7877dd313db8fdaa3537c675yl * carried by this TxDL.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @align_vaddr_start: (TODO).
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @align_vaddr: Virtual address of the per-TxDL area in memory used for
a23fd118e437af0a7877dd313db8fdaa3537c675yl * alignement. Used to place one or more mis-aligned fragments
a23fd118e437af0a7877dd313db8fdaa3537c675yl * (the maximum defined by configration variable
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @max_aligned_frags).
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @align_dma_addr: DMA address translated from the @align_vaddr.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @align_dma_handle: DMA handle that corresponds to @align_dma_addr.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @align_dma_acch: DMA access handle corresponds to @align_dma_addr.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @align_dma_offset: The current offset into the @align_vaddr area.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Grows while filling the descriptor, gets reset.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @align_used_frags: (TODO).
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @alloc_frags: Total number of fragments allocated.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @dang_frags: Number of fragments kept from release until this TxDL is freed.
7eced415e5dd557aef2d78483b5a7785f0e13670xw * @bytes_sent: TODO
7eced415e5dd557aef2d78483b5a7785f0e13670xw * @unused: TODO
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @dang_txdl: (TODO).
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @next_txdl_priv: (TODO).
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @first_txdp: (TODO).
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @dang_dtrh: Pointer to TxDL (list) kept from release until this TxDL
a23fd118e437af0a7877dd313db8fdaa3537c675yl * is freed.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @linked_txdl_priv: Pointer to any linked TxDL for creating contiguous
a23fd118e437af0a7877dd313db8fdaa3537c675yl * TxDL list.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @dtrh: Corresponding dtrh to this TxDL.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @memblock: Pointer to the TxDL memory block or memory page.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * on the next send operation.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @dma_object: DMA address and handle of the memory block that contains
a23fd118e437af0a7877dd313db8fdaa3537c675yl * the descriptor. This member is used only in the "checked"
a23fd118e437af0a7877dd313db8fdaa3537c675yl * version of the HAL (to enforce certain assertions);
a23fd118e437af0a7877dd313db8fdaa3537c675yl * otherwise it gets compiled out.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @allocated: True if the descriptor is reserved, 0 otherwise. Internal usage.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Per-transmit decsriptor HAL-private data. HAL uses the space to keep DMA
a23fd118e437af0a7877dd313db8fdaa3537c675yl * information associated with the descriptor. Note that ULD can ask HAL
a23fd118e437af0a7877dd313db8fdaa3537c675yl * to allocate additional per-descriptor space for its own (ULD-specific)
a23fd118e437af0a7877dd313db8fdaa3537c675yl * purposes.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * See also: xge_hal_ring_rxd_priv_t{}.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * xge_hal_fifo_get_max_frags_cnt - Return the max fragments allocated
a23fd118e437af0a7877dd313db8fdaa3537c675yl * for the fifo.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @channelh: Channel handle.
a23fd118e437af0a7877dd313db8fdaa3537c675ylstatic inline int
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_fifo_get_max_frags_cnt(xge_hal_channel_h channelh)
a23fd118e437af0a7877dd313db8fdaa3537c675yl/* ========================= FIFO PRIVATE API ============================= */
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_status_e __hal_fifo_open(xge_hal_channel_h channelh,
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_fifo_dtr_align_alloc_map(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_fifo_dtr_align_free_unmap(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
a23fd118e437af0a7877dd313db8fdaa3537c675yl#if defined(XGE_DEBUG_FP) && (XGE_DEBUG_FP & XGE_DEBUG_FP_FIFO)
a23fd118e437af0a7877dd313db8fdaa3537c675yl__HAL_STATIC_FIFO __HAL_INLINE_FIFO xge_hal_fifo_txdl_priv_t*
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_fifo_dtr_post_single(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
a23fd118e437af0a7877dd313db8fdaa3537c675yl/* ========================= FIFO PUBLIC API ============================== */
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_fifo_dtr_reserve(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh);
7eced415e5dd557aef2d78483b5a7785f0e13670xwxge_hal_fifo_dtr_reserve_many(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh,
7eced415e5dd557aef2d78483b5a7785f0e13670xw const int frags);
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_fifo_dtr_reserve_sp(xge_hal_channel_h channel, int dtr_sp_size,
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_fifo_dtr_post(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh);
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_fifo_dtr_post_many(xge_hal_channel_h channelh, int num,
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_fifo_dtr_next_completed(xge_hal_channel_h channelh, xge_hal_dtr_h *dtrh,
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_fifo_dtr_free(xge_hal_channel_h channelh, xge_hal_dtr_h dtr);
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_fifo_dtr_buffer_set(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_fifo_dtr_buffer_set_aligned(xge_hal_channel_h channelh,
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_fifo_dtr_buffer_append(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_fifo_dtr_buffer_finalize(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh,
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_fifo_dtr_cksum_set_bits(xge_hal_dtr_h dtrh, u64 cksum_bits);
a23fd118e437af0a7877dd313db8fdaa3537c675ylxge_hal_fifo_dtr_vlan_set(xge_hal_dtr_h dtrh, u16 vlan_tag);
8347601bcb0a439f6e50fc36b4039a73d08700e1ylxge_hal_fifo_is_next_dtr_completed(xge_hal_channel_h channelh);
a23fd118e437af0a7877dd313db8fdaa3537c675yl#else /* XGE_FASTPATH_EXTERN */
a23fd118e437af0a7877dd313db8fdaa3537c675yl#endif /* XGE_FASTPATH_INLINE */
a23fd118e437af0a7877dd313db8fdaa3537c675yl#endif /* XGE_HAL_FIFO_H */