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8347601bcb0a439f6e50fc36b4039a73d08700e1yl * Copyright (c) 2002-2006 Neterion, Inc.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * struct xge_hal_tti_config_t - Xframe Tx interrupt configuration.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @enabled: Set to 1, if TTI feature is enabled.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @urange_a: Link utilization range A. The value from 0 to 100%.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @ufc_a: Frame count for the utilization range A. Interrupt will be generated
a23fd118e437af0a7877dd313db8fdaa3537c675yl * each time when (and only when) the line is utilized no more
a23fd118e437af0a7877dd313db8fdaa3537c675yl * than @urange_a percent in the transmit direction,
a23fd118e437af0a7877dd313db8fdaa3537c675yl * and number of transmitted frames is greater or equal @ufc_a.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @urange_b: Link utilization range B.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @ufc_b: Frame count for the utilization range B.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @urange_c: Link utilization range C.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @ufc_c: Frame count for the utilization range C.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @urange_d: Link utilization range D.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @ufc_d: Frame count for the utilization range D.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @timer_val_us: Interval of time, in microseconds, at which transmit timer
a23fd118e437af0a7877dd313db8fdaa3537c675yl * interrupt is to be generated. Note that unless @timer_ci_en
a23fd118e437af0a7877dd313db8fdaa3537c675yl * is set, the timer interrupt is generated only in presence
a23fd118e437af0a7877dd313db8fdaa3537c675yl * of the transmit traffic. Note also that timer interrupt
a23fd118e437af0a7877dd313db8fdaa3537c675yl * and utilization interrupt are two separate interrupt
a23fd118e437af0a7877dd313db8fdaa3537c675yl * sources.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @timer_ac_en: Enable auto-cancel. That is, reset the timer if utilization
a23fd118e437af0a7877dd313db8fdaa3537c675yl * interrupt was generated during the interval.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @timer_ci_en: Enable/disable continuous interrupt. Set this value
a23fd118e437af0a7877dd313db8fdaa3537c675yl * to 1 in order to generate continuous interrupt
a23fd118e437af0a7877dd313db8fdaa3537c675yl * at fixed @timer_val intervals of time, independently
a23fd118e437af0a7877dd313db8fdaa3537c675yl * of whether there is transmit traffic or not.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @enabled: Set to 1, if TTI feature is enabled.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Xframe transmit interrupt configuration.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * See Xframe User Guide, Section 3.5 "Device Interrupts"
a23fd118e437af0a7877dd313db8fdaa3537c675yl * for more details. Note also (min, max)
a23fd118e437af0a7877dd313db8fdaa3537c675yl * ranges in the body of the xge_hal_tx_intr_config_t structure.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Note: Valid (min, max) range for each attribute is specified in the body of
a23fd118e437af0a7877dd313db8fdaa3537c675yl * the xge_hal_tti_config_t{} structure. Please refer to the
a23fd118e437af0a7877dd313db8fdaa3537c675yl * corresponding header file.
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* Line utilization interrupts */
a23fd118e437af0a7877dd313db8fdaa3537c675yl * struct xge_hal_rti_config_t - Xframe Rx interrupt configuration.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @urange_a: Link utilization range A. The value from 0 to 100%.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @ufc_a: Frame count for the utilization range A. Interrupt will be generated
a23fd118e437af0a7877dd313db8fdaa3537c675yl * each time when (and only when) the line is utilized no more
a23fd118e437af0a7877dd313db8fdaa3537c675yl * than @urange_a percent inbound,
a23fd118e437af0a7877dd313db8fdaa3537c675yl * and number of received frames is greater or equal @ufc_a.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @urange_b: Link utilization range B.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @ufc_b: Frame count for the utilization range B.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @urange_c: Link utilization range C.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @ufc_c: Frame count for the utilization range C.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @urange_d: Link utilization range D.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @ufc_d: Frame count for the utilization range D.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @timer_ac_en: Enable auto-cancel. That is, reset the timer if utilization
a23fd118e437af0a7877dd313db8fdaa3537c675yl * interrupt was generated during the interval.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @timer_val_us: Interval of time, in microseconds, at which receive timer
a23fd118e437af0a7877dd313db8fdaa3537c675yl * interrupt is to be generated. The timer interrupt is generated
a23fd118e437af0a7877dd313db8fdaa3537c675yl * only in presence of the inbound traffic. Note also that timer
a23fd118e437af0a7877dd313db8fdaa3537c675yl * interrupt and utilization interrupt are two separate interrupt
a23fd118e437af0a7877dd313db8fdaa3537c675yl * sources.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Xframe receive interrupt configuration.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * See Xframe User Guide, Section 3.5 "Device Interrupts"
a23fd118e437af0a7877dd313db8fdaa3537c675yl * for more details. Note also (min, max)
a23fd118e437af0a7877dd313db8fdaa3537c675yl * ranges in the body of the xge_hal_intr_config_t structure.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Note: Valid (min, max) range for each attribute is specified in the body of
a23fd118e437af0a7877dd313db8fdaa3537c675yl * the xge_hal_rti_config_t{} structure. Please refer to the
a23fd118e437af0a7877dd313db8fdaa3537c675yl * corresponding header file.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * struct xge_hal_fifo_queue_t - Single fifo configuration.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @max: Max numbers of TxDLs (that is, lists of Tx descriptors) per queue.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @initial: Initial numbers of TxDLs per queue (can grow up to @max).
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @intr: Boolean. Use 1 to generate interrupt for each completed TxDL.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Use 0 otherwise.
7eced415e5dd557aef2d78483b5a7785f0e13670xw * @intr_vector: TBD
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @no_snoop_bits: If non-zero, specifies no-snoop PCI operation,
a23fd118e437af0a7877dd313db8fdaa3537c675yl * which generally improves latency of the host bridge operation
a23fd118e437af0a7877dd313db8fdaa3537c675yl * (see PCI specification). For valid values please refer
a23fd118e437af0a7877dd313db8fdaa3537c675yl * to xge_hal_fifo_queue_t{} in the driver sources.
7eced415e5dd557aef2d78483b5a7785f0e13670xw * @priority: TBD
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @configured: Boolean. Use 1 to specify that the fifo is configured.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Only "configured" fifos can be activated and used to post
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Tx descriptors. Any subset of 8 available fifos can be
a23fd118e437af0a7877dd313db8fdaa3537c675yl * "configured".
7eced415e5dd557aef2d78483b5a7785f0e13670xw * @tti: TBD
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Single fifo configuration.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Note: Valid (min, max) range for each attribute is specified in the body of
a23fd118e437af0a7877dd313db8fdaa3537c675yl * the xge_hal_fifo_queue_t{} structure. Please refer to the
a23fd118e437af0a7877dd313db8fdaa3537c675yl * corresponding header file.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * See also: xge_hal_fifo_config_t{}
a23fd118e437af0a7877dd313db8fdaa3537c675yl * struct xge_hal_fifo_config_t - Configuration of all 8 fifos.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @max_frags: Max number of Tx buffers per TxDL (that is, per single
a23fd118e437af0a7877dd313db8fdaa3537c675yl * transmit operation).
a23fd118e437af0a7877dd313db8fdaa3537c675yl * No more than 256 transmit buffers can be specified.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @max_aligned_frags: Number of fragments to be aligned out of
a23fd118e437af0a7877dd313db8fdaa3537c675yl * maximum fragments (see @max_frags).
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @reserve_threshold: Descriptor reservation threshold.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * At least @reserve_threshold descriptors will remain
a23fd118e437af0a7877dd313db8fdaa3537c675yl * unallocated at all times.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @memblock_size: Fifo descriptors are allocated in blocks of @mem_block_size
a23fd118e437af0a7877dd313db8fdaa3537c675yl * bytes. Setting @memblock_size to page size ensures
a23fd118e437af0a7877dd313db8fdaa3537c675yl * by-page allocation of descriptors. 128K bytes is the
a23fd118e437af0a7877dd313db8fdaa3537c675yl * maximum supported block size.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @queue: Array of per-fifo configurations.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @alignment_size: per Tx fragment DMA-able memory used to align transmit data
a23fd118e437af0a7877dd313db8fdaa3537c675yl * (e.g., to align on a cache line).
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Configuration of all Xframe fifos. Includes array of xge_hal_fifo_queue_t
a23fd118e437af0a7877dd313db8fdaa3537c675yl * structures.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Note: Valid (min, max) range for each attribute is specified in the body of
a23fd118e437af0a7877dd313db8fdaa3537c675yl * the xge_hal_fifo_config_t{} structure. Please refer to the
a23fd118e437af0a7877dd313db8fdaa3537c675yl * corresponding header file.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * See also: xge_hal_ring_queue_t{}.
a23fd118e437af0a7877dd313db8fdaa3537c675yl /* range: (1, @max_frags) */
7eced415e5dd557aef2d78483b5a7785f0e13670xw#define XGE_HAL_MAX_FIFO_NUM_TITAN (XGE_HAL_MAX_VIRTUAL_PATHS - 1)
7eced415e5dd557aef2d78483b5a7785f0e13670xw * struct xge_hal_rts_port_t - RTS port entry
7eced415e5dd557aef2d78483b5a7785f0e13670xw * @num: Port number
7eced415e5dd557aef2d78483b5a7785f0e13670xw * @udp: Port is UDP (default TCP)
7eced415e5dd557aef2d78483b5a7785f0e13670xw * @src: Port is Source (default Destination)
a23fd118e437af0a7877dd313db8fdaa3537c675yl * struct xge_hal_ring_queue_t - Single ring configuration.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @max: Max numbers of RxD blocks per queue
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @initial: Initial numbers of RxD blocks per queue
a23fd118e437af0a7877dd313db8fdaa3537c675yl * (can grow up to @max)
7eced415e5dd557aef2d78483b5a7785f0e13670xw * @buffer_mode: Receive buffer mode (1, 2, 3, or 5); for details please refer
a23fd118e437af0a7877dd313db8fdaa3537c675yl * to Xframe User Guide.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @dram_size_mb: Size (in MB) of Xframe DRAM used for _that_ ring.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Note that 64MB of available
a23fd118e437af0a7877dd313db8fdaa3537c675yl * on-board DRAM is shared between receive rings.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * If a single ring is used, @dram_size_mb can be set to 64.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Sum of all rings' @dram_size_mb cannot exceed 64.
7eced415e5dd557aef2d78483b5a7785f0e13670xw * @intr_vector: TBD
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @backoff_interval_us: Time (in microseconds), after which Xframe
a23fd118e437af0a7877dd313db8fdaa3537c675yl * tries to download RxDs posted by the host.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Note that the "backoff" does not happen if host posts receive
a23fd118e437af0a7877dd313db8fdaa3537c675yl * descriptors in the timely fashion.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @max_frm_len: Maximum frame length that can be received on _that_ ring.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Setting this field to -1 ensures that the ring will
a23fd118e437af0a7877dd313db8fdaa3537c675yl * "accept" MTU-size frames (note that MTU can be changed at
a23fd118e437af0a7877dd313db8fdaa3537c675yl * runtime).
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Any value other than (-1) specifies a certain "hard"
a23fd118e437af0a7877dd313db8fdaa3537c675yl * limit on the receive frame sizes.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * The field can be used to activate receive frame-length based
a23fd118e437af0a7877dd313db8fdaa3537c675yl * steering.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @priority: Ring priority. 0 - highest, 7 - lowest. The value is used
a23fd118e437af0a7877dd313db8fdaa3537c675yl * to give prioritized access to PCI-X. See Xframe documentation
a23fd118e437af0a7877dd313db8fdaa3537c675yl * for details.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @rth_en: Enable Receive Traffic Hashing (RTH).
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @no_snoop_bits: If non-zero, specifies no-snoop PCI operation,
a23fd118e437af0a7877dd313db8fdaa3537c675yl * which generally improves latency of the host bridge operation
a23fd118e437af0a7877dd313db8fdaa3537c675yl * (see PCI specification). For valid values please refer
a23fd118e437af0a7877dd313db8fdaa3537c675yl * to xge_hal_ring_queue_t{} in the driver sources.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @indicate_max_pkts: Sets maximum number of received frames to be processed
a23fd118e437af0a7877dd313db8fdaa3537c675yl * within single interrupt.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @configured: Boolean. Use 1 to specify that the ring is configured.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Only "configured" rings can be activated and used to post
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Rx descriptors. Any subset of 8 available rings can be
a23fd118e437af0a7877dd313db8fdaa3537c675yl * "configured".
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @rts_mac_en: 1 - To enable Receive MAC address steering.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * 0 - To disable Receive MAC address steering.
7eced415e5dd557aef2d78483b5a7785f0e13670xw * @rth_en: TBD
7eced415e5dd557aef2d78483b5a7785f0e13670xw * @rts_port_en: TBD
7eced415e5dd557aef2d78483b5a7785f0e13670xw * @rts_ports: TBD
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @rti: Xframe receive interrupt configuration.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Single ring configuration.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Note: Valid (min, max) range for each attribute is specified in the body of
a23fd118e437af0a7877dd313db8fdaa3537c675yl * the xge_hal_ring_queue_t{} structure. Please refer to the
a23fd118e437af0a7877dd313db8fdaa3537c675yl * corresponding header file.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * See also: xge_hal_fifo_config_t{}.
7eced415e5dd557aef2d78483b5a7785f0e13670xw xge_hal_rts_port_t rts_ports[XGE_HAL_MAX_STEERABLE_PORTS];
a23fd118e437af0a7877dd313db8fdaa3537c675yl * struct xge_hal_ring_config_t - Array of ring configurations.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @memblock_size: Ring descriptors are allocated in blocks of @mem_block_size
a23fd118e437af0a7877dd313db8fdaa3537c675yl * bytes. Setting @memblock_size to page size ensures
a23fd118e437af0a7877dd313db8fdaa3537c675yl * by-page allocation of descriptors. 128K bytes is the
a23fd118e437af0a7877dd313db8fdaa3537c675yl * upper limit.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @scatter_mode: Xframe supports two receive scatter modes: A and B.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * For details please refer to Xframe User Guide.
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * @strip_vlan_tag: TBD
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @queue: Array of all Xframe ring configurations.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Array of ring configurations.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * See also: xge_hal_ring_queue_t{}.
7eced415e5dd557aef2d78483b5a7785f0e13670xw#define XGE_HAL_MAX_RING_NUM_TITAN (XGE_HAL_MAX_VIRTUAL_PATHS - 1)
a23fd118e437af0a7877dd313db8fdaa3537c675yl * struct xge_hal_mac_config_t - MAC configuration.
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * @media: Transponder type.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @tmac_util_period: The sampling period over which the transmit utilization
a23fd118e437af0a7877dd313db8fdaa3537c675yl * is calculated.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @rmac_util_period: The sampling period over which the receive utilization
a23fd118e437af0a7877dd313db8fdaa3537c675yl * is calculated.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @rmac_strip_pad: Determines whether padding of received frames is removed by
a23fd118e437af0a7877dd313db8fdaa3537c675yl * the MAC or sent to the host.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @rmac_bcast_en: Enable frames containing broadcast address to be
a23fd118e437af0a7877dd313db8fdaa3537c675yl * passed to the host.
7eced415e5dd557aef2d78483b5a7785f0e13670xw * @rmac_pause_gen_en: Received pause generation enable.
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * @rmac_pause_rcv_en: Receive pause enable.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @rmac_pause_time: The value to be inserted in outgoing pause frames.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Has units of pause quanta (one pause quanta = 512 bit times).
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @mc_pause_threshold_q0q3: Contains thresholds for pause frame generation
a23fd118e437af0a7877dd313db8fdaa3537c675yl * for queues 0 through 3. The threshold value indicates portion of the
a23fd118e437af0a7877dd313db8fdaa3537c675yl * individual receive buffer queue size. Thresholds have a range of 0 to
a23fd118e437af0a7877dd313db8fdaa3537c675yl * 255, allowing 256 possible watermarks in a queue.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @mc_pause_threshold_q4q7: Contains thresholds for pause frame generation
a23fd118e437af0a7877dd313db8fdaa3537c675yl * for queues 4 through 7. The threshold value indicates portion of the
a23fd118e437af0a7877dd313db8fdaa3537c675yl * individual receive buffer queue size. Thresholds have a range of 0 to
a23fd118e437af0a7877dd313db8fdaa3537c675yl * 255, allowing 256 possible watermarks in a queue.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * MAC configuration. This includes various aspects of configuration, including:
a23fd118e437af0a7877dd313db8fdaa3537c675yl * - Pause frame threshold;
a23fd118e437af0a7877dd313db8fdaa3537c675yl * - sampling rate to calculate link utilization;
a23fd118e437af0a7877dd313db8fdaa3537c675yl * - enabling/disabling broadcasts.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * See Xframe User Guide for more details.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Note: Valid (min, max) range for each attribute is specified in the body of
a23fd118e437af0a7877dd313db8fdaa3537c675yl * the xge_hal_mac_config_t{} structure. Please refer to the
a23fd118e437af0a7877dd313db8fdaa3537c675yl * corresponding include file.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * struct xge_hal_device_config_t - Device configuration.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @mtu: Current mtu size.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @isr_polling_cnt: Maximum number of times to "poll" for Tx and Rx
a23fd118e437af0a7877dd313db8fdaa3537c675yl * completions. Used in xge_hal_device_handle_irq().
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @latency_timer: Specifies, in units of PCI bus clocks, and in conformance
a23fd118e437af0a7877dd313db8fdaa3537c675yl * with the PCI Specification, the value of the Latency Timer
a23fd118e437af0a7877dd313db8fdaa3537c675yl * for this PCI bus master.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Specify either zero or -1 to use BIOS default.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @napi_weight: (TODO)
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @max_splits_trans: Maximum number of PCI-X split transactions.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Specify (-1) to use BIOS default.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @mmrb_count: Maximum Memory Read Byte Count. Use (-1) to use default
a23fd118e437af0a7877dd313db8fdaa3537c675yl * BIOS value. Otherwise: mmrb_count = 0 corresponds to 512B;
a23fd118e437af0a7877dd313db8fdaa3537c675yl * 1 - 1KB, 2 - 2KB, and 3 - 4KB.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @shared_splits: The number of Outstanding Split Transactions that is
a23fd118e437af0a7877dd313db8fdaa3537c675yl * shared by Tx and Rx requests. The device stops issuing Tx
a23fd118e437af0a7877dd313db8fdaa3537c675yl * requests once the number of Outstanding Split Transactions is
a23fd118e437af0a7877dd313db8fdaa3537c675yl * equal to the value of Shared_Splits.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * A value of zero indicates that the Tx and Rx share all allocated
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Split Requests, i.e. the device can issue both types (Tx and Rx)
a23fd118e437af0a7877dd313db8fdaa3537c675yl * of read requests until the number of Maximum Outstanding Split
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Transactions is reached.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @stats_refresh_time_sec: Sets the default interval for automatic stats transfer
a23fd118e437af0a7877dd313db8fdaa3537c675yl * to the host. This includes MAC stats as well as PCI stats.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * See xge_hal_stats_hw_info_t{}.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @pci_freq_mherz: PCI clock frequency, e.g.: 133 for 133MHz.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @intr_mode: Line, MSI, or MSI-X interrupt.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @sched_timer_us: If greater than zero, specifies time interval
a23fd118e437af0a7877dd313db8fdaa3537c675yl * (in microseconds) for the device to generate
a23fd118e437af0a7877dd313db8fdaa3537c675yl * interrupt. Note that unlike tti and rti interrupts,
a23fd118e437af0a7877dd313db8fdaa3537c675yl * the scheduled interrupt is generated independently of
a23fd118e437af0a7877dd313db8fdaa3537c675yl * whether there is transmit or receive traffic, respectively.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @sched_timer_one_shot: 1 - generate scheduled interrupt only once.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * 0 - generate scheduled interrupt periodically at the specified
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @sched_timer_us interval.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @ring: See xge_hal_ring_config_t{}.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @mac: See xge_hal_mac_config_t{}.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @tti: See xge_hal_tti_config_t{}.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @fifo: See xge_hal_fifo_config_t{}.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @dump_on_serr: Dump adapter state ("about", statistics, registers) on SERR#.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @dump_on_eccerr: Dump adapter state ("about", statistics, registers) on
a23fd118e437af0a7877dd313db8fdaa3537c675yl * ECC error.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @dump_on_parityerr: Dump adapter state ("about", statistics, registers) on
a23fd118e437af0a7877dd313db8fdaa3537c675yl * parity error.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @rth_en: Enable Receive Traffic Hashing(RTH) using IT(Indirection Table).
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @rth_bucket_size: RTH bucket width (in bits). For valid range please see
a23fd118e437af0a7877dd313db8fdaa3537c675yl * xge_hal_device_config_t{} in the driver sources.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @rth_spdm_en: Enable Receive Traffic Hashing(RTH) using SPDM(Socket Pair
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Direct Match).
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @rth_spdm_use_l4: Set to 1, if the L4 ports are used in the calculation of
a23fd118e437af0a7877dd313db8fdaa3537c675yl * hash value in the RTH SPDM based steering.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @rxufca_intr_thres: (TODO)
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @rxufca_lo_lim: (TODO)
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @rxufca_hi_lim: (TODO)
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @rxufca_lbolt_period: (TODO)
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @link_valid_cnt: link-valid counting is done only at device-open time,
a23fd118e437af0a7877dd313db8fdaa3537c675yl * to determine with the specified certainty that the link is up. See also
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @link_retry_cnt.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @link_retry_cnt: Max number of polls for link-up. Done only at device
a23fd118e437af0a7877dd313db8fdaa3537c675yl * open time. Reducing this value as well as the previous @link_valid_cnt,
a23fd118e437af0a7877dd313db8fdaa3537c675yl * speeds up device startup, which may be important if the driver
a23fd118e437af0a7877dd313db8fdaa3537c675yl * is compiled into OS.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @link_stability_period: Specify the period for which the link must be
a23fd118e437af0a7877dd313db8fdaa3537c675yl * stable in order for the adapter to declare "LINK UP".
a23fd118e437af0a7877dd313db8fdaa3537c675yl * The enumerated settings (see Xframe-II UG) are:
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * 0 ........... instantaneous
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * 1 ........... 500 �s
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * 2 ........... 1 ms
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * 3 ........... 64 ms
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * 4 ........... 256 ms
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * 5 ........... 512 ms
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * 6 ........... 1 s
a23fd118e437af0a7877dd313db8fdaa3537c675yl * 7 ........... 2 s
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @device_poll_millis: Specify the interval (in mulliseconds) between
a23fd118e437af0a7877dd313db8fdaa3537c675yl * successive xge_hal_device_poll() runs.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * stable in order for the adapter to declare "LINK UP".
7eced415e5dd557aef2d78483b5a7785f0e13670xw * @no_isr_events: TBD
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * @lro_sg_size: TBD
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * @lro_frm_len: TBD
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * @bimodal_interrupts: Enable bimodal interrupts in device
7eced415e5dd557aef2d78483b5a7785f0e13670xw * @bimodal_timer_lo_us: TBD
7eced415e5dd557aef2d78483b5a7785f0e13670xw * @bimodal_timer_hi_us: TBD
7eced415e5dd557aef2d78483b5a7785f0e13670xw * @rts_mac_en: Enable Receive Traffic Steering using MAC destination address
7eced415e5dd557aef2d78483b5a7785f0e13670xw * @rts_qos_en: TBD
7eced415e5dd557aef2d78483b5a7785f0e13670xw * @rts_port_en: TBD
7eced415e5dd557aef2d78483b5a7785f0e13670xw * @vp_config: Configuration for virtual paths
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * @max_cqe_groups: The maximum number of adapter CQE group blocks a CQRQ
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * can own at any one time.
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * @max_num_wqe_od_groups: The maximum number of WQE Headers/OD Groups that
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * this S-RQ can own at any one time.
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * @no_wqe_threshold: Maximum number of times adapter polls WQE Hdr blocks for
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * WQEs before generating a message or interrupt.
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * @refill_threshold_high:This field provides a hysteresis upper bound for
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * automatic adapter refill operations.
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * @refill_threshold_low:This field provides a hysteresis lower bound for
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * automatic adapter refill operations.
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * @eol_policy:This field sets the policy for handling the end of list condition.
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * 2'b00 - When EOL is reached,poll until last block wrapper size is no longer 0.
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * 2'b01 - Send UMQ message when EOL is reached.
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * 2'b1x - Poll until the poll_count_max is reached and if still EOL,send UMQ message
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * @eol_poll_count_max:sets the maximum number of times the queue manager will poll for
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * a non-zero block wrapper before giving up and sending a UMQ message
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * @ack_blk_limit: Limit on the maximum number of ACK list blocks that can be held
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * by a session at any one time.
7eced415e5dd557aef2d78483b5a7785f0e13670xw * @poll_or_doorbell: TBD
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Xframe configuration.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Contains per-device configuration parameters, including:
a23fd118e437af0a7877dd313db8fdaa3537c675yl * - latency timer (settable via PCI configuration space);
a23fd118e437af0a7877dd313db8fdaa3537c675yl * - maximum number of split transactions;
a23fd118e437af0a7877dd313db8fdaa3537c675yl * - maximum number of shared splits;
a23fd118e437af0a7877dd313db8fdaa3537c675yl * - stats sampling interval, etc.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * In addition, xge_hal_device_config_t{} includes "subordinate"
a23fd118e437af0a7877dd313db8fdaa3537c675yl * configurations, including:
a23fd118e437af0a7877dd313db8fdaa3537c675yl * - fifos and rings;
a23fd118e437af0a7877dd313db8fdaa3537c675yl * - MAC (see xge_hal_mac_config_t{}).
a23fd118e437af0a7877dd313db8fdaa3537c675yl * See Xframe User Guide for more details.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Note: Valid (min, max) range for each attribute is specified in the body of
a23fd118e437af0a7877dd313db8fdaa3537c675yl * the xge_hal_device_config_t{} structure. Please refer to the
a23fd118e437af0a7877dd313db8fdaa3537c675yl * corresponding include file.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * See also: xge_hal_tti_config_t{}, xge_hal_stats_hw_info_t{},
a23fd118e437af0a7877dd313db8fdaa3537c675yl * xge_hal_mac_config_t{}.
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_MIN_LINK_STABILITY_PERIOD 0 /* instantaneous */
a23fd118e437af0a7877dd313db8fdaa3537c675yl * struct xge_hal_driver_config_t - HAL (layer) configuration.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @periodic_poll_interval_millis: Interval, in milliseconds, which is used to
a23fd118e437af0a7877dd313db8fdaa3537c675yl * periodically poll HAL, i.e, invoke
a23fd118e437af0a7877dd313db8fdaa3537c675yl * xge_hal_device_poll().
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Note that HAL does not maintain its own
a23fd118e437af0a7877dd313db8fdaa3537c675yl * polling context. HAL relies on ULD to
a23fd118e437af0a7877dd313db8fdaa3537c675yl * provide one.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @queue_size_initial: Initial size of the HAL protected event queue.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * The queue is shared by HAL and upper-layer drivers.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * The queue is used to exchange and process slow-path
a23fd118e437af0a7877dd313db8fdaa3537c675yl * events. See xge_hal_event_e.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @queue_size_max: Maximum size of the HAL queue. Depending on the load,
a23fd118e437af0a7877dd313db8fdaa3537c675yl * the queue may grow at run-time up to @queue_max_size.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * @tracebuf_size: Size of the trace buffer. Set it to '0' to disable.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * HAL configuration. (Note: do not confuse HAL layer with (possibly multiple)
a23fd118e437af0a7877dd313db8fdaa3537c675yl * HAL devices.)
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Currently this structure contains just a few basic values.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Note: Valid (min, max) range for each attribute is specified in the body of
a23fd118e437af0a7877dd313db8fdaa3537c675yl * the structure. Please refer to the corresponding header file.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * See also: xge_hal_device_poll()
a23fd118e437af0a7877dd313db8fdaa3537c675yl/* ========================== PRIVATE API ================================= */
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_device_config_check_common (xge_hal_device_config_t *new_config);
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_device_config_check_xena (xge_hal_device_config_t *new_config);
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_device_config_check_herc (xge_hal_device_config_t *new_config);
a23fd118e437af0a7877dd313db8fdaa3537c675yl__hal_driver_config_check (xge_hal_driver_config_t *new_config);
a23fd118e437af0a7877dd313db8fdaa3537c675yl#endif /* XGE_HAL_CONFIG_H */