a23fd118e437af0a7877dd313db8fdaa3537c675yl * CDDL HEADER START
a23fd118e437af0a7877dd313db8fdaa3537c675yl * The contents of this file are subject to the terms of the
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Common Development and Distribution License (the "License").
a23fd118e437af0a7877dd313db8fdaa3537c675yl * You may not use this file except in compliance with the License.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
a23fd118e437af0a7877dd313db8fdaa3537c675yl * See the License for the specific language governing permissions
a23fd118e437af0a7877dd313db8fdaa3537c675yl * and limitations under the License.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * When distributing Covered Code, include this CDDL HEADER in each
a23fd118e437af0a7877dd313db8fdaa3537c675yl * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * If applicable, add the following below this CDDL HEADER, with the
a23fd118e437af0a7877dd313db8fdaa3537c675yl * fields enclosed by brackets "[]" replaced with your own identifying
a23fd118e437af0a7877dd313db8fdaa3537c675yl * information: Portions Copyright [yyyy] [name of copyright owner]
a23fd118e437af0a7877dd313db8fdaa3537c675yl * CDDL HEADER END
0dc2366f7b9f9f36e10909b1e95edbf2a261c2acVenugopal Iyer * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Use is subject to license terms.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Copyright (c) 2002-2005 Neterion, Inc.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * All right Reserved.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * FileName : xgell.h
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Description: Link Layer driver declaration
a23fd118e437af0a7877dd313db8fdaa3537c675ylextern "C" {
7eced415e5dd557aef2d78483b5a7785f0e13670xw * The definition of XGELL_RX_BUFFER_RECYCLE_CACHE is an experimental value.
7eced415e5dd557aef2d78483b5a7785f0e13670xw * With this value, the lock contention between xgell_rx_buffer_recycle()
7eced415e5dd557aef2d78483b5a7785f0e13670xw * and xgell_rx_1b_compl() is reduced to great extent. And multiple rx rings
7eced415e5dd557aef2d78483b5a7785f0e13670xw * alleviate the lock contention further since each rx ring has its own mutex.
7eced415e5dd557aef2d78483b5a7785f0e13670xw#define XGELL_RX_BUFFER_RECYCLE_CACHE XGE_HAL_RING_RXDS_PER_BLOCK(1) * 2
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * These default values can be overridden by vaules in xge.conf.
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * In xge.conf user has to specify actual (not percentages) values.
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGELL_RX_BUFFER_TOTAL XGE_HAL_RING_RXDS_PER_BLOCK(1) * 6
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGELL_RX_BUFFER_POST_HIWAT XGE_HAL_RING_RXDS_PER_BLOCK(1) * 5
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng * Multiple rings configuration
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGELL_RX_RING_NUM_DEFAULT XGELL_RX_RING_NUM_MAX
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGELL_TX_RING_NUM_DEFAULT XGELL_TX_RING_NUM_MAX
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng (XGELL_RX_RING_NUM_MAX + XGELL_TX_RING_NUM_MAX + 1)
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGELL_MINTR_NUM_DEFAULT XGELL_MINTR_NUM_MAX
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGELL_CONF_GROUP_POLICY_DEFAULT XGELL_CONF_GROUP_POLICY_PERF
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGELL_CONF_GROUP_POLICY_DEFAULT XGELL_CONF_GROUP_POLICY_VIRT
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng * The _PERF configuration enable a fat group of all rx rings, as approachs
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng * better fanout performance of the primary interface.
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGELL_CONF_GROUP_POLICY_DEFAULT XGELL_CONF_GROUP_POLICY_PERF
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng/* Control driver to copy or DMA inbound/outbound packets */
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * Try to collapse up to XGELL_RX_PKT_BURST packets into single mblk
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * sequence before mac_rx() is called.
a23fd118e437af0a7877dd313db8fdaa3537c675yl/* About 1s */
8347601bcb0a439f6e50fc36b4039a73d08700e1yl/* LRO configuration */
7eced415e5dd557aef2d78483b5a7785f0e13670xw#define XGE_HAL_DEFAULT_LRO_SG_SIZE 2 /* <=2 LRO fix not required */
7eced415e5dd557aef2d78483b5a7785f0e13670xw * Default values for tunables used in HAL. Please refer to xgehal-config.h
7eced415e5dd557aef2d78483b5a7785f0e13670xw * for more details.
7eced415e5dd557aef2d78483b5a7785f0e13670xw/* Bimodal adaptive schema defaults - ENABLED */
7eced415e5dd557aef2d78483b5a7785f0e13670xw/* Interrupt moderation/utilization defaults */
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGE_HAL_DEFAULT_INDICATE_MAX_PKTS_B 512 /* bimodal */
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGE_HAL_DEFAULT_INDICATE_MAX_PKTS_N 256 /* normal UFC */
7eced415e5dd557aef2d78483b5a7785f0e13670xw * This will force HAL to allocate extra copied buffer per TXDL which
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * size calculated by formula:
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * (ALIGNMENT_SIZE * ALIGNED_FRAGS)
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_DEFAULT_INITIAL_MTU XGE_HAL_DEFAULT_MTU /* 1500 */
7eced415e5dd557aef2d78483b5a7785f0e13670xw#if defined(__sparc)
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGE_HAL_DEFAULT_MMRB_COUNT XGE_HAL_MAX_MMRB_COUNT
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGE_HAL_DEFAULT_SPLIT_TRANSACTION XGE_HAL_EIGHT_SPLIT_TRANSACTION
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGE_HAL_DEFAULT_SPLIT_TRANSACTION XGE_HAL_TWO_SPLIT_TRANSACTION
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng * Default the size of buffers allocated for ndd interface functions
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng * Multiple mac address definitions
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng * We'll use whole MAC Addresses Configuration Memory for unicast addresses,
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng * since current multicast implementation in HAL is by enabling promise mode.
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGE_RX_MULTI_MAC_ADDRESSES_MAX 8 /* per ring group */
a23fd118e437af0a7877dd313db8fdaa3537c675yltypedef struct {
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng/* Buffer pool for one rx ring */
7eced415e5dd557aef2d78483b5a7785f0e13670xw xgell_rx_buffer_t *recycle_head; /* recycle list's head */
7eced415e5dd557aef2d78483b5a7785f0e13670xw xgell_rx_buffer_t *recycle_tail; /* recycle list's tail */
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng ether_addr_t mac_addr[XGE_RX_MULTI_MAC_ADDRESSES_MAX];
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng boolean_t mac_addr_set[XGE_RX_MULTI_MAC_ADDRESSES_MAX];
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng ddi_intr_handle_t *handle; /* DDI interrupt handle */
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng xge_hal_channel_h channelh; /* hardware channel */
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng mac_ring_handle_t ring_handle; /* call back ring handle */
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng mac_group_handle_t group_handle; /* call back group handle */
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng xgell_multi_mac_t mmac; /* per group multiple addrs */
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng xgell_rx_buffer_pool_t bf_pool; /* per ring buffer pool */
0dc2366f7b9f9f36e10909b1e95edbf2a261c2acVenugopal Iyer uint64_t rx_pkts; /* total received packets */
0dc2366f7b9f9f36e10909b1e95edbf2a261c2acVenugopal Iyer uint64_t rx_bytes; /* total received bytes */
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng xge_hal_channel_h channelh; /* hardware channel */
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng mac_ring_handle_t ring_handle; /* call back ring handle */
0dc2366f7b9f9f36e10909b1e95edbf2a261c2acVenugopal Iyer uint64_t tx_bytes; /* bytes sent though the ring */
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng xgell_rx_ring_t rx_ring[XGELL_RX_RING_NUM_DEFAULT];
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng xgell_tx_ring_t tx_ring[XGELL_TX_RING_NUM_DEFAULT];
a23fd118e437af0a7877dd313db8fdaa3537c675yltypedef struct {
a23fd118e437af0a7877dd313db8fdaa3537c675yl ddi_dma_handle_t dma_handles[XGE_HAL_DEFAULT_FIFO_FRAGS];
a23fd118e437af0a7877dd313db8fdaa3537c675yltypedef struct {
a23fd118e437af0a7877dd313db8fdaa3537c675ylint xgell_device_alloc(xge_hal_device_h devh, dev_info_t *dev_info,
a23fd118e437af0a7877dd313db8fdaa3537c675ylint xgell_device_register(xgelldev_t *lldev, xgell_config_t *config);
0dc2366f7b9f9f36e10909b1e95edbf2a261c2acVenugopal Iyerint xgell_rx_ring_stat(mac_ring_driver_t rh, uint_t stat, uint64_t *val);
0dc2366f7b9f9f36e10909b1e95edbf2a261c2acVenugopal Iyerint xgell_tx_ring_stat(mac_ring_driver_t rh, uint_t stat, uint64_t *val);
a23fd118e437af0a7877dd313db8fdaa3537c675yl#endif /* _SYS_XGELL_H */