a23fd118e437af0a7877dd313db8fdaa3537c675yl/*
a23fd118e437af0a7877dd313db8fdaa3537c675yl * CDDL HEADER START
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * The contents of this file are subject to the terms of the
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Common Development and Distribution License (the "License").
a23fd118e437af0a7877dd313db8fdaa3537c675yl * You may not use this file except in compliance with the License.
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
a23fd118e437af0a7877dd313db8fdaa3537c675yl * or http://www.opensolaris.org/os/licensing.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * See the License for the specific language governing permissions
a23fd118e437af0a7877dd313db8fdaa3537c675yl * and limitations under the License.
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * When distributing Covered Code, include this CDDL HEADER in each
a23fd118e437af0a7877dd313db8fdaa3537c675yl * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * If applicable, add the following below this CDDL HEADER, with the
a23fd118e437af0a7877dd313db8fdaa3537c675yl * fields enclosed by brackets "[]" replaced with your own identifying
a23fd118e437af0a7877dd313db8fdaa3537c675yl * information: Portions Copyright [yyyy] [name of copyright owner]
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * CDDL HEADER END
a23fd118e437af0a7877dd313db8fdaa3537c675yl */
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl/*
0dc2366f7b9f9f36e10909b1e95edbf2a261c2acVenugopal Iyer * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Use is subject to license terms.
a23fd118e437af0a7877dd313db8fdaa3537c675yl */
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl/*
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Copyright (c) 2002-2005 Neterion, Inc.
a23fd118e437af0a7877dd313db8fdaa3537c675yl * All right Reserved.
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * FileName : xgell.h
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl * Description: Link Layer driver declaration
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
a23fd118e437af0a7877dd313db8fdaa3537c675yl */
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl#ifndef _SYS_XGELL_H
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define _SYS_XGELL_H
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl#include <sys/types.h>
a23fd118e437af0a7877dd313db8fdaa3537c675yl#include <sys/errno.h>
a23fd118e437af0a7877dd313db8fdaa3537c675yl#include <sys/param.h>
a23fd118e437af0a7877dd313db8fdaa3537c675yl#include <sys/stropts.h>
a23fd118e437af0a7877dd313db8fdaa3537c675yl#include <sys/stream.h>
a23fd118e437af0a7877dd313db8fdaa3537c675yl#include <sys/strsubr.h>
a23fd118e437af0a7877dd313db8fdaa3537c675yl#include <sys/kmem.h>
a23fd118e437af0a7877dd313db8fdaa3537c675yl#include <sys/conf.h>
a23fd118e437af0a7877dd313db8fdaa3537c675yl#include <sys/devops.h>
a23fd118e437af0a7877dd313db8fdaa3537c675yl#include <sys/ksynch.h>
a23fd118e437af0a7877dd313db8fdaa3537c675yl#include <sys/stat.h>
a23fd118e437af0a7877dd313db8fdaa3537c675yl#include <sys/modctl.h>
a23fd118e437af0a7877dd313db8fdaa3537c675yl#include <sys/debug.h>
a23fd118e437af0a7877dd313db8fdaa3537c675yl#include <sys/pci.h>
a23fd118e437af0a7877dd313db8fdaa3537c675yl#include <sys/ethernet.h>
a23fd118e437af0a7877dd313db8fdaa3537c675yl#include <sys/vlan.h>
a23fd118e437af0a7877dd313db8fdaa3537c675yl#include <sys/dlpi.h>
a23fd118e437af0a7877dd313db8fdaa3537c675yl#include <sys/taskq.h>
a23fd118e437af0a7877dd313db8fdaa3537c675yl#include <sys/cyclic.h>
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl#include <sys/pattr.h>
a23fd118e437af0a7877dd313db8fdaa3537c675yl#include <sys/strsun.h>
a23fd118e437af0a7877dd313db8fdaa3537c675yl
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#include <sys/mac_provider.h>
ba2e4443695ee6a6f420a35cd4fc3d3346d22932seb#include <sys/mac_ether.h>
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl#ifdef __cplusplus
a23fd118e437af0a7877dd313db8fdaa3537c675ylextern "C" {
a23fd118e437af0a7877dd313db8fdaa3537c675yl#endif
a23fd118e437af0a7877dd313db8fdaa3537c675yl
193974072f41a843678abf5f61979c748687e66bSherry Moore#define XGELL_DESC "Xframe I/II 10Gb Ethernet"
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGELL_IFNAME "xge"
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl#include <xgehal.h>
a23fd118e437af0a7877dd313db8fdaa3537c675yl
7eced415e5dd557aef2d78483b5a7785f0e13670xw/*
7eced415e5dd557aef2d78483b5a7785f0e13670xw * The definition of XGELL_RX_BUFFER_RECYCLE_CACHE is an experimental value.
7eced415e5dd557aef2d78483b5a7785f0e13670xw * With this value, the lock contention between xgell_rx_buffer_recycle()
7eced415e5dd557aef2d78483b5a7785f0e13670xw * and xgell_rx_1b_compl() is reduced to great extent. And multiple rx rings
7eced415e5dd557aef2d78483b5a7785f0e13670xw * alleviate the lock contention further since each rx ring has its own mutex.
7eced415e5dd557aef2d78483b5a7785f0e13670xw */
7eced415e5dd557aef2d78483b5a7785f0e13670xw#define XGELL_RX_BUFFER_RECYCLE_CACHE XGE_HAL_RING_RXDS_PER_BLOCK(1) * 2
7eced415e5dd557aef2d78483b5a7785f0e13670xw#define MSG_SIZE 64
7eced415e5dd557aef2d78483b5a7785f0e13670xw
8347601bcb0a439f6e50fc36b4039a73d08700e1yl/*
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * These default values can be overridden by vaules in xge.conf.
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * In xge.conf user has to specify actual (not percentages) values.
8347601bcb0a439f6e50fc36b4039a73d08700e1yl */
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGELL_RX_BUFFER_TOTAL XGE_HAL_RING_RXDS_PER_BLOCK(1) * 6
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGELL_RX_BUFFER_POST_HIWAT XGE_HAL_RING_RXDS_PER_BLOCK(1) * 5
a23fd118e437af0a7877dd313db8fdaa3537c675yl
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng/*
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng * Multiple rings configuration
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng */
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGELL_RX_RING_MAIN 0
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGELL_TX_RING_MAIN 0
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGELL_RX_RING_NUM_MIN 1
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGELL_TX_RING_NUM_MIN 1
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGELL_RX_RING_NUM_MAX 8
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGELL_TX_RING_NUM_MAX 1 /* TODO */
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGELL_RX_RING_NUM_DEFAULT XGELL_RX_RING_NUM_MAX
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGELL_TX_RING_NUM_DEFAULT XGELL_TX_RING_NUM_MAX
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGELL_MINTR_NUM_MIN 1
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGELL_MINTR_NUM_MAX \
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng (XGELL_RX_RING_NUM_MAX + XGELL_TX_RING_NUM_MAX + 1)
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGELL_MINTR_NUM_DEFAULT XGELL_MINTR_NUM_MAX
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGELL_CONF_GROUP_POLICY_BASIC 0
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGELL_CONF_GROUP_POLICY_VIRT 1
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGELL_CONF_GROUP_POLICY_PERF 2
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#if 0
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#if defined(__sparc)
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGELL_CONF_GROUP_POLICY_DEFAULT XGELL_CONF_GROUP_POLICY_PERF
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#else
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGELL_CONF_GROUP_POLICY_DEFAULT XGELL_CONF_GROUP_POLICY_VIRT
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#endif
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#else
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng/*
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng * The _PERF configuration enable a fat group of all rx rings, as approachs
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng * better fanout performance of the primary interface.
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng */
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGELL_CONF_GROUP_POLICY_DEFAULT XGELL_CONF_GROUP_POLICY_PERF
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#endif
a23fd118e437af0a7877dd313db8fdaa3537c675yl
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGELL_TX_LEVEL_LOW 8
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGELL_TX_LEVEL_HIGH 32
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGELL_TX_LEVEL_CHECK 3
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGELL_MAX_RING_DEFAULT 8
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGELL_MAX_FIFO_DEFAULT 1
a23fd118e437af0a7877dd313db8fdaa3537c675yl
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng/* Control driver to copy or DMA inbound/outbound packets */
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#if defined(__sparc)
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGELL_RX_DMA_LOWAT 256
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGELL_TX_DMA_LOWAT 512
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#else
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGELL_RX_DMA_LOWAT 256
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGELL_TX_DMA_LOWAT 128
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#endif
8347601bcb0a439f6e50fc36b4039a73d08700e1yl
8347601bcb0a439f6e50fc36b4039a73d08700e1yl/*
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * Try to collapse up to XGELL_RX_PKT_BURST packets into single mblk
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * sequence before mac_rx() is called.
8347601bcb0a439f6e50fc36b4039a73d08700e1yl */
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGELL_RX_PKT_BURST 32
8347601bcb0a439f6e50fc36b4039a73d08700e1yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl/* About 1s */
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGE_DEV_POLL_TICKS drv_usectohz(1000000)
a23fd118e437af0a7877dd313db8fdaa3537c675yl
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGELL_LSO_MAXLEN 65535
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGELL_CONF_ENABLE_BY_DEFAULT 1
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGELL_CONF_DISABLE_BY_DEFAULT 0
8347601bcb0a439f6e50fc36b4039a73d08700e1yl
8347601bcb0a439f6e50fc36b4039a73d08700e1yl/* LRO configuration */
7eced415e5dd557aef2d78483b5a7785f0e13670xw#define XGE_HAL_DEFAULT_LRO_SG_SIZE 2 /* <=2 LRO fix not required */
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGE_HAL_DEFAULT_LRO_FRM_LEN 65535
8347601bcb0a439f6e50fc36b4039a73d08700e1yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl/*
7eced415e5dd557aef2d78483b5a7785f0e13670xw * Default values for tunables used in HAL. Please refer to xgehal-config.h
7eced415e5dd557aef2d78483b5a7785f0e13670xw * for more details.
a23fd118e437af0a7877dd313db8fdaa3537c675yl */
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_DEFAULT_USE_HARDCODE -1
a23fd118e437af0a7877dd313db8fdaa3537c675yl
7eced415e5dd557aef2d78483b5a7785f0e13670xw/* Bimodal adaptive schema defaults - ENABLED */
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGE_HAL_DEFAULT_BIMODAL_INTERRUPTS -1
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGE_HAL_DEFAULT_BIMODAL_TIMER_LO_US 24
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGE_HAL_DEFAULT_BIMODAL_TIMER_HI_US 256
8347601bcb0a439f6e50fc36b4039a73d08700e1yl
7eced415e5dd557aef2d78483b5a7785f0e13670xw/* Interrupt moderation/utilization defaults */
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGE_HAL_DEFAULT_TX_URANGE_A 5
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGE_HAL_DEFAULT_TX_URANGE_B 15
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGE_HAL_DEFAULT_TX_URANGE_C 30
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGE_HAL_DEFAULT_TX_UFC_A 15
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGE_HAL_DEFAULT_TX_UFC_B 30
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGE_HAL_DEFAULT_TX_UFC_C 45
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGE_HAL_DEFAULT_TX_UFC_D 60
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_DEFAULT_TX_TIMER_CI_EN 1
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_DEFAULT_TX_TIMER_AC_EN 1
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGE_HAL_DEFAULT_TX_TIMER_VAL 10000
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGE_HAL_DEFAULT_INDICATE_MAX_PKTS_B 512 /* bimodal */
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGE_HAL_DEFAULT_INDICATE_MAX_PKTS_N 256 /* normal UFC */
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_DEFAULT_RX_URANGE_A 10
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGE_HAL_DEFAULT_RX_URANGE_B 30
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_DEFAULT_RX_URANGE_C 50
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGE_HAL_DEFAULT_RX_UFC_A 1
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGE_HAL_DEFAULT_RX_UFC_B_J 2
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGE_HAL_DEFAULT_RX_UFC_B_N 8
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGE_HAL_DEFAULT_RX_UFC_C_J 4
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGE_HAL_DEFAULT_RX_UFC_C_N 16
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGE_HAL_DEFAULT_RX_UFC_D 32
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_DEFAULT_RX_TIMER_AC_EN 1
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGE_HAL_DEFAULT_RX_TIMER_VAL 384
a23fd118e437af0a7877dd313db8fdaa3537c675yl
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGE_HAL_DEFAULT_FIFO_QUEUE_LENGTH_A 1024
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_DEFAULT_FIFO_QUEUE_LENGTH_J 2048
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_DEFAULT_FIFO_QUEUE_LENGTH_N 4096
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_DEFAULT_FIFO_QUEUE_INTR 0
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_DEFAULT_FIFO_RESERVE_THRESHOLD 0
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_DEFAULT_FIFO_MEMBLOCK_SIZE PAGESIZE
a23fd118e437af0a7877dd313db8fdaa3537c675yl
8347601bcb0a439f6e50fc36b4039a73d08700e1yl/*
7eced415e5dd557aef2d78483b5a7785f0e13670xw * This will force HAL to allocate extra copied buffer per TXDL which
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * size calculated by formula:
8347601bcb0a439f6e50fc36b4039a73d08700e1yl *
8347601bcb0a439f6e50fc36b4039a73d08700e1yl * (ALIGNMENT_SIZE * ALIGNED_FRAGS)
8347601bcb0a439f6e50fc36b4039a73d08700e1yl */
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGE_HAL_DEFAULT_FIFO_ALIGNMENT_SIZE 4096
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_DEFAULT_FIFO_MAX_ALIGNED_FRAGS 1
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#if defined(__sparc)
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGE_HAL_DEFAULT_FIFO_FRAGS 64
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#else
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGE_HAL_DEFAULT_FIFO_FRAGS 128
a23fd118e437af0a7877dd313db8fdaa3537c675yl#endif
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGE_HAL_DEFAULT_FIFO_FRAGS_THRESHOLD 18
a23fd118e437af0a7877dd313db8fdaa3537c675yl
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGE_HAL_DEFAULT_RING_QUEUE_BLOCKS 2
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_RING_QUEUE_BUFFER_MODE_DEFAULT 1
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGE_HAL_DEFAULT_BACKOFF_INTERVAL_US 64
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_DEFAULT_RING_PRIORITY 0
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_DEFAULT_RING_MEMBLOCK_SIZE PAGESIZE
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_DEFAULT_RING_NUM 8
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_DEFAULT_TMAC_UTIL_PERIOD 5
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_DEFAULT_RMAC_UTIL_PERIOD 5
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_DEFAULT_RMAC_HIGH_PTIME 65535
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_DEFAULT_MC_PAUSE_THRESHOLD_Q0Q3 187
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_DEFAULT_MC_PAUSE_THRESHOLD_Q4Q7 187
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGE_HAL_DEFAULT_RMAC_PAUSE_GEN_EN 1
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGE_HAL_DEFAULT_RMAC_PAUSE_GEN_DIS 0
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGE_HAL_DEFAULT_RMAC_PAUSE_RCV_EN 1
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGE_HAL_DEFAULT_RMAC_PAUSE_RCV_DIS 0
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_DEFAULT_INITIAL_MTU XGE_HAL_DEFAULT_MTU /* 1500 */
8347601bcb0a439f6e50fc36b4039a73d08700e1yl#define XGE_HAL_DEFAULT_ISR_POLLING_CNT 0
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_DEFAULT_LATENCY_TIMER 255
7eced415e5dd557aef2d78483b5a7785f0e13670xw#define XGE_HAL_DEFAULT_SHARED_SPLITS 0
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGE_HAL_DEFAULT_STATS_REFRESH_TIME 1
a23fd118e437af0a7877dd313db8fdaa3537c675yl
7eced415e5dd557aef2d78483b5a7785f0e13670xw#if defined(__sparc)
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGE_HAL_DEFAULT_MMRB_COUNT XGE_HAL_MAX_MMRB_COUNT
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGE_HAL_DEFAULT_SPLIT_TRANSACTION XGE_HAL_EIGHT_SPLIT_TRANSACTION
7eced415e5dd557aef2d78483b5a7785f0e13670xw#else
7eced415e5dd557aef2d78483b5a7785f0e13670xw#define XGE_HAL_DEFAULT_MMRB_COUNT 1 /* 1k */
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGE_HAL_DEFAULT_SPLIT_TRANSACTION XGE_HAL_TWO_SPLIT_TRANSACTION
7eced415e5dd557aef2d78483b5a7785f0e13670xw#endif
7eced415e5dd557aef2d78483b5a7785f0e13670xw
a23fd118e437af0a7877dd313db8fdaa3537c675yl/*
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng * Default the size of buffers allocated for ndd interface functions
a23fd118e437af0a7877dd313db8fdaa3537c675yl */
7eced415e5dd557aef2d78483b5a7785f0e13670xw#define XGELL_STATS_BUFSIZE 8192
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGELL_PCICONF_BUFSIZE 2048
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGELL_ABOUT_BUFSIZE 512
a23fd118e437af0a7877dd313db8fdaa3537c675yl#define XGELL_IOCTL_BUFSIZE 64
7eced415e5dd557aef2d78483b5a7785f0e13670xw#define XGELL_DEVCONF_BUFSIZE 8192
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl/*
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng * Multiple mac address definitions
a23fd118e437af0a7877dd313db8fdaa3537c675yl *
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng * We'll use whole MAC Addresses Configuration Memory for unicast addresses,
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng * since current multicast implementation in HAL is by enabling promise mode.
a23fd118e437af0a7877dd313db8fdaa3537c675yl */
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng#define XGE_RX_MULTI_MAC_ADDRESSES_MAX 8 /* per ring group */
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yltypedef struct {
8347601bcb0a439f6e50fc36b4039a73d08700e1yl int rx_pkt_burst;
a23fd118e437af0a7877dd313db8fdaa3537c675yl int rx_buffer_total;
a23fd118e437af0a7877dd313db8fdaa3537c675yl int rx_buffer_post_hiwat;
8347601bcb0a439f6e50fc36b4039a73d08700e1yl int rx_dma_lowat;
8347601bcb0a439f6e50fc36b4039a73d08700e1yl int tx_dma_lowat;
8347601bcb0a439f6e50fc36b4039a73d08700e1yl int lso_enable;
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng int msix_enable;
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng int grouping;
a23fd118e437af0a7877dd313db8fdaa3537c675yl} xgell_config_t;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
da14cebe459d3275048785f25bd869cb09b5307fEric Chengtypedef struct xgell_multi_mac xgell_multi_mac_t;
da14cebe459d3275048785f25bd869cb09b5307fEric Chengtypedef struct xgell_rx_ring xgell_rx_ring_t;
da14cebe459d3275048785f25bd869cb09b5307fEric Chengtypedef struct xgell_tx_ring xgell_tx_ring_t;
da14cebe459d3275048785f25bd869cb09b5307fEric Chengtypedef struct xgelldev xgelldev_t;
7eced415e5dd557aef2d78483b5a7785f0e13670xw
a23fd118e437af0a7877dd313db8fdaa3537c675yltypedef struct xgell_rx_buffer_t {
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng struct xgell_rx_buffer_t *next;
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng void *vaddr;
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng dma_addr_t dma_addr;
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng ddi_dma_handle_t dma_handle;
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng ddi_acc_handle_t dma_acch;
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng xgell_rx_ring_t *ring;
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng frtn_t frtn;
a23fd118e437af0a7877dd313db8fdaa3537c675yl} xgell_rx_buffer_t;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng/* Buffer pool for one rx ring */
a23fd118e437af0a7877dd313db8fdaa3537c675yltypedef struct xgell_rx_buffer_pool_t {
a23fd118e437af0a7877dd313db8fdaa3537c675yl uint_t total; /* total buffers */
a23fd118e437af0a7877dd313db8fdaa3537c675yl uint_t size; /* buffer size */
a23fd118e437af0a7877dd313db8fdaa3537c675yl xgell_rx_buffer_t *head; /* header pointer */
a23fd118e437af0a7877dd313db8fdaa3537c675yl uint_t free; /* free buffers */
a23fd118e437af0a7877dd313db8fdaa3537c675yl uint_t post; /* posted buffers */
a23fd118e437af0a7877dd313db8fdaa3537c675yl uint_t post_hiwat; /* hiwat to stop post */
a23fd118e437af0a7877dd313db8fdaa3537c675yl spinlock_t pool_lock; /* buffer pool lock */
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng boolean_t live; /* pool status */
7eced415e5dd557aef2d78483b5a7785f0e13670xw xgell_rx_buffer_t *recycle_head; /* recycle list's head */
7eced415e5dd557aef2d78483b5a7785f0e13670xw xgell_rx_buffer_t *recycle_tail; /* recycle list's tail */
7eced415e5dd557aef2d78483b5a7785f0e13670xw uint_t recycle; /* # of rx buffers recycled */
7eced415e5dd557aef2d78483b5a7785f0e13670xw spinlock_t recycle_lock; /* buffer recycle lock */
a23fd118e437af0a7877dd313db8fdaa3537c675yl} xgell_rx_buffer_pool_t;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
da14cebe459d3275048785f25bd869cb09b5307fEric Chengstruct xgell_multi_mac {
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng int naddr; /* total supported addresses */
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng int naddrfree; /* free addresses slots */
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng ether_addr_t mac_addr[XGE_RX_MULTI_MAC_ADDRESSES_MAX];
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng boolean_t mac_addr_set[XGE_RX_MULTI_MAC_ADDRESSES_MAX];
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng};
ba2e4443695ee6a6f420a35cd4fc3d3346d22932seb
da14cebe459d3275048785f25bd869cb09b5307fEric Chengtypedef uint_t (*intr_func_t)(caddr_t, caddr_t);
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng
da14cebe459d3275048785f25bd869cb09b5307fEric Chengtypedef struct xgell_intr {
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng uint_t index;
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng ddi_intr_handle_t *handle; /* DDI interrupt handle */
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng intr_func_t *function; /* interrupt function */
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng caddr_t arg; /* interrupt source */
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng} xgell_intr_t;
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng
da14cebe459d3275048785f25bd869cb09b5307fEric Chengstruct xgell_rx_ring {
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng int index;
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng boolean_t live; /* ring active status */
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng xge_hal_channel_h channelh; /* hardware channel */
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng xgelldev_t *lldev; /* driver device */
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng mac_ring_handle_t ring_handle; /* call back ring handle */
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng mac_group_handle_t group_handle; /* call back group handle */
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng uint64_t ring_gen_num;
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng xgell_multi_mac_t mmac; /* per group multiple addrs */
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng xgell_rx_buffer_pool_t bf_pool; /* per ring buffer pool */
0dc2366f7b9f9f36e10909b1e95edbf2a261c2acVenugopal Iyer uint64_t rx_pkts; /* total received packets */
0dc2366f7b9f9f36e10909b1e95edbf2a261c2acVenugopal Iyer uint64_t rx_bytes; /* total received bytes */
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng int poll_bytes; /* bytes to be polled up */
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng int polled_bytes; /* total polled bytes */
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng mblk_t *poll_mp; /* polled messages */
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng spinlock_t ring_lock; /* per ring lock */
7eced415e5dd557aef2d78483b5a7785f0e13670xw};
7eced415e5dd557aef2d78483b5a7785f0e13670xw
da14cebe459d3275048785f25bd869cb09b5307fEric Chengstruct xgell_tx_ring {
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng int index;
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng boolean_t live; /* ring active status */
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng xge_hal_channel_h channelh; /* hardware channel */
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng xgelldev_t *lldev; /* driver device */
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng mac_ring_handle_t ring_handle; /* call back ring handle */
0dc2366f7b9f9f36e10909b1e95edbf2a261c2acVenugopal Iyer uint64_t tx_pkts; /* packets sent */
0dc2366f7b9f9f36e10909b1e95edbf2a261c2acVenugopal Iyer uint64_t tx_bytes; /* bytes sent though the ring */
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng boolean_t need_resched;
7eced415e5dd557aef2d78483b5a7785f0e13670xw};
a23fd118e437af0a7877dd313db8fdaa3537c675yl
ba2e4443695ee6a6f420a35cd4fc3d3346d22932sebstruct xgelldev {
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng volatile int is_initialized;
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng volatile int in_reset;
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng kmutex_t genlock;
ba2e4443695ee6a6f420a35cd4fc3d3346d22932seb mac_handle_t mh;
a23fd118e437af0a7877dd313db8fdaa3537c675yl int instance;
a23fd118e437af0a7877dd313db8fdaa3537c675yl dev_info_t *dev_info;
a23fd118e437af0a7877dd313db8fdaa3537c675yl xge_hal_device_h devh;
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng caddr_t ndp;
a23fd118e437af0a7877dd313db8fdaa3537c675yl timeout_id_t timeout_id;
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng int init_rx_rings;
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng int init_tx_rings;
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng int init_rx_groups;
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng int live_rx_rings;
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng int live_tx_rings;
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng xgell_rx_ring_t rx_ring[XGELL_RX_RING_NUM_DEFAULT];
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng xgell_tx_ring_t tx_ring[XGELL_TX_RING_NUM_DEFAULT];
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng int tx_copied_max;
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng xgell_intr_t intrs[XGELL_MINTR_NUM_DEFAULT];
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng
7eced415e5dd557aef2d78483b5a7785f0e13670xw ddi_intr_handle_t *intr_table;
7eced415e5dd557aef2d78483b5a7785f0e13670xw uint_t intr_table_size;
7eced415e5dd557aef2d78483b5a7785f0e13670xw int intr_type;
7eced415e5dd557aef2d78483b5a7785f0e13670xw int intr_cnt;
7eced415e5dd557aef2d78483b5a7785f0e13670xw uint_t intr_pri;
7eced415e5dd557aef2d78483b5a7785f0e13670xw int intr_cap;
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng
da14cebe459d3275048785f25bd869cb09b5307fEric Cheng xgell_config_t config;
ba2e4443695ee6a6f420a35cd4fc3d3346d22932seb};
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yltypedef struct {
a23fd118e437af0a7877dd313db8fdaa3537c675yl mblk_t *mblk;
a23fd118e437af0a7877dd313db8fdaa3537c675yl ddi_dma_handle_t dma_handles[XGE_HAL_DEFAULT_FIFO_FRAGS];
a23fd118e437af0a7877dd313db8fdaa3537c675yl int handle_cnt;
a23fd118e437af0a7877dd313db8fdaa3537c675yl} xgell_txd_priv_t;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yltypedef struct {
a23fd118e437af0a7877dd313db8fdaa3537c675yl xgell_rx_buffer_t *rx_buffer;
a23fd118e437af0a7877dd313db8fdaa3537c675yl} xgell_rxd_priv_t;
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylint xgell_device_alloc(xge_hal_device_h devh, dev_info_t *dev_info,
a23fd118e437af0a7877dd313db8fdaa3537c675yl xgelldev_t **lldev_out);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylvoid xgell_device_free(xgelldev_t *lldev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylint xgell_device_register(xgelldev_t *lldev, xgell_config_t *config);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylint xgell_device_unregister(xgelldev_t *lldev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylvoid xgell_callback_link_up(void *userdata);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylvoid xgell_callback_link_down(void *userdata);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylint xgell_onerr_reset(xgelldev_t *lldev);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675ylvoid xge_device_poll_now(void *data);
a23fd118e437af0a7877dd313db8fdaa3537c675yl
7eced415e5dd557aef2d78483b5a7785f0e13670xwint xge_add_intrs(xgelldev_t *lldev);
7eced415e5dd557aef2d78483b5a7785f0e13670xw
7eced415e5dd557aef2d78483b5a7785f0e13670xwint xge_enable_intrs(xgelldev_t *lldev);
7eced415e5dd557aef2d78483b5a7785f0e13670xw
7eced415e5dd557aef2d78483b5a7785f0e13670xwvoid xge_disable_intrs(xgelldev_t *lldev);
7eced415e5dd557aef2d78483b5a7785f0e13670xw
7eced415e5dd557aef2d78483b5a7785f0e13670xwvoid xge_rem_intrs(xgelldev_t *lldev);
7eced415e5dd557aef2d78483b5a7785f0e13670xw
0dc2366f7b9f9f36e10909b1e95edbf2a261c2acVenugopal Iyerint xgell_rx_ring_stat(mac_ring_driver_t rh, uint_t stat, uint64_t *val);
7eced415e5dd557aef2d78483b5a7785f0e13670xw
0dc2366f7b9f9f36e10909b1e95edbf2a261c2acVenugopal Iyerint xgell_tx_ring_stat(mac_ring_driver_t rh, uint_t stat, uint64_t *val);
7eced415e5dd557aef2d78483b5a7785f0e13670xw
a23fd118e437af0a7877dd313db8fdaa3537c675yl#ifdef __cplusplus
a23fd118e437af0a7877dd313db8fdaa3537c675yl}
a23fd118e437af0a7877dd313db8fdaa3537c675yl#endif
a23fd118e437af0a7877dd313db8fdaa3537c675yl
a23fd118e437af0a7877dd313db8fdaa3537c675yl#endif /* _SYS_XGELL_H */