vr_impl.h revision 2ca5b6595b95478e6568b0e77c6c83c8a870867a
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
/*
* Register definitions for the VIA Rhine ethernet adapters
*/
#ifndef _VRREG_H
#define _VRREG_H
#ifdef __cplusplus
extern "C" {
#endif
/*
* Some definitions for the MII because miiregs doesn't have them
*/
#define MII_EXTSTATUS 0x9
#define MII_EXTSTATUS_1000BASE_X_FD 0x8000
#define MII_EXTSTATUS_1000BASE_X 0x4000
#define MII_EXTSTATUS_1000BASE_T_FD 0x2000
#define MII_EXTSTATUS_1000BASE_T 0x1000
/*
* MAC address
*/
#define VR_ETHERADDR 0x00
/*
* Receive Configuration
* The thresholds denote the level in the FIFO before transmission
* to host memory starts.
*/
#define VR_RXCFG 0x06
#define VR_RXCFG_ACCEPTERROR (1 << 0)
#define VR_RXCFG_FIFO_THRESHOLD_BITS (VR_RXCFG_FIFO_THRESHOLD_0 | \
#define VR_RXCFG_FIFO_THRESHOLD_64 (0)
#define VR_RXCFG_FIFO_THRESHOLD_256 (VR_RXCFG_FIFO_THRESHOLD_0 | \
#define VR_RXCFG_FIFO_THRESHOLD_768 (VR_RXCFG_FIFO_THRESHOLD_0 | \
#define VR_RXCFG_FIFO_THRESHOLD_1024 (VR_RXCFG_FIFO_THRESHOLD_2 | \
/*
* Transmit Configuration
* The transmission starts when the data in the FIFO reaches the threshold.
* Store and Forward means that a transmission starts when a complete frame
* is in the FIFO.
*/
#define VR_TXCFG 0x07
#define VR_TXCFG_FIFO_THRESHOLD_BITS (VR_TXCFG_FIFO_THRESHOLD_0 | \
#define VR_TXCFG_FIFO_THRESHOLD_128 (0)
#define VR_TXCFG_FIFO_THRESHOLD_1024 (VR_TXCFG_FIFO_THRESHOLD_0 | \
/*
* Chip control
*/
#define VR_CTRL0 0x08
#define VR_CTRL0_RESERVED (1 << 0)
#define VR_CTRL0_DMA_GO (VR_CTRL0_DMA_ENABLE | \
#define VR_CTRL1 0x09
#define VR_CTRL1_RESERVED (1 << 0)
/*
* Interrupt Status
* This register reflects NIC status
* The host reads it to determine the cause of the interrupt
* This register must be cleared after power-up
*/
#define VR_ISR0 0x0C
#define VR_ISR0_RX_DONE (1 << 0)
/*
* Interrupt Configuration
* All bits in this register correspond to the bits in the Interrupt Status
* register Setting individual bits will enable the corresponding interrupt
* This register defaults to all zeros on power up
*/
#define VR_ICR0 0x0E
#define VR_ICR0_RX_DONE VR_ISR0_RX_DONE
#define VR_ICR0_TX_DONE VR_ISR0_TX_DONE
#define VR_ICR0_RX_ERR VR_ISR0_RX_ERR
#define VR_ICR0_TX_ERR VR_ISR0_TX_ERR
#define VR_ICR0_RX_LINKERR VR_ISR0_RX_LINKERR
#define VR_ICR0_BUSERR VR_ISR0_BUSERR
#define VR_ICR0_STATSMAX VR_ISR0_STATSMAX
#define VR_ICR0_RX_EARLY VR_ISR0_RX_EARLY
#define VR_ICR0_RX_DROPPED VR_ISR0_RX_DROPPED
#define VR_ICR0_RX_NOBUF VR_ISR0_RX_NOBUF
#define VR_ICR0_TX_ABORT VR_ISR0_TX_ABORT
#define VR_ICR0_LINKSTATUS VR_ISR0_LINKSTATUS
#define VR_ICR0_GENERAL VR_ISR0_GENERAL
/*
* Mulicast address registers (MAR), 8 bytes
*/
/*
* CAM data port
*/
#define VR_MCAM1 0x11
#define VR_MCAM2 0x12
#define VR_MCAM3 0x13
#define VR_MCAM4 0x14
#define VR_MCAM5 0x15
#define VR_VCAM0 0x16
#define VR_VCAM1 0x17
/*
* Start addresses of receive and transmit ring
*/
/*
* VT6105M has 8 TX queues
*/
#define VR_TX7_ADDR 0x1C
#define VR_TX6_ADDR 0x20
#define VR_TX5_ADDR 0x24
#define VR_TX4_ADDR 0x28
#define VR_TX3_ADDR 0x2C
#define VR_TX2_ADDR 0x30
#define VR_TX1_ADDR 0x34
#define VR_TX0_ADDR 0x38
/*
* Current and receive- and transmit descriptors.
* These are listed in the VT6102 manual but not in the VT6105.
*/
/* VIA secrets here */
#define VR_INTRLINE 0x3c
#define VR_INTRPIN 0x3d
/* VIA secrets here */
#define VR_MODE0 0x50
#define VR_MODE0_QPKTDS 0x80
#define VR_MODE1 0x51
#define VR_FIFOTST 0x51
/*
* These are not in the datasheet but used in the 'fet' driver
*/
#define VR_MODE2 0x52
#define VR_MODE2_DISABT 0x40
#define VR_MODE2_MODE10T 0x02
#define VR_MODE3 0x53
#define VR_MODE3_XONOPT 0x80
#define VR_MODE3_TPACEN 0x40
#define VR_MODE3_BACKOPT 0x20
#define VR_MODE3_DLTSEL 0x10
#define VR_MODE3_MIIDMY 0x08
#define VR_MODE3_MIION 0x04
#define VR_PCI_DELAY_TIMER 0x54
#define VR_FIFOCMD 0x56
#define VR_FIFOSTA 0x57
/* VIA secrets here */
/*
* MII Configuration
*/
#define VR_MIIPHYADDR 0x6C
#define VR_MIIPHYADDR_ADDR0 (1 << 0)
#define VR_MIIPHYADDR_ADDRBITS (VR_MIIPHYADDR_ADDR0 | \
/*
* MII status
*/
#define VR_MIISR 0x6D
/*
* Bus control
*/
#define VR_BCR0_DMA0 (1 << 0)
#define VR_BCR0_DMA32 (0)
#define VR_BCR0_DMA64 (VR_BCR0_DMA0)
#define VR_BCR0_DMA128 (VR_BCR0_DMA1)
#define VR_BCR0_DMA512 (VR_BCR0_DMA2)
#define VR_BCR0_DMASTFW (VR_BCR0_DMABITS)
#define VR_BCR0_RX_FIFO_THRESHOLD_64 (0)
#define VR_BCR0_RX_FIFO_THRESHOLD_256 (VR_BCR0_RX_FIFO_THRESHOLD_0 | \
#define VR_BCR0_RX_FIFO_THRESHOLD_768 (VR_BCR0_RX_FIFO_THRESHOLD_0 | \
#define VR_BCR1_POLLT_0 (1 << 0)
#define VR_BCR1_TX_FIFO_THRESHOLD_128 (0)
/*
* MII Configuration
*/
#define VR_MIICMD 0x70
#define VR_MIICMD_MD_CLOCK (1 << 0)
#define VR_MIIADDR 0x71
#define VR_MIIADDR_MAD0 (1 << 0)
#define VR_MIIADDR_BITS (VR_MIIADDR_MAD0 | \
VR_MIIADDR_MAD1 | \
VR_MIIADDR_MAD2 | \
VR_MIIADDR_MAD3 | \
#define VR_MIIDATA 0x72
#define VR_MIIDATA_1 0x72
#define VR_MIIDATA_2 0x73
/*
* EEPROM Config / Status
*/
#define VR_PROMCTL 0x74
#define VR_PROMCTL_DATAOUT (1 << 0)
/*
* Chip Configuration A
*/
#define VR_CFGA 0x78
/*
* Chip Configuration B
*/
#define VR_CFGB 0x79
#define VR_CFGB_LATENCYTIMER (1 << 0)
/*
* Chip Configuration C
*/
#define VR_CFGC 0x7A
#define VR_CFGC_BPS0 (1 << 0)
/*
* Chip Configuration D
*/
#define VR_CFGD 0x7B
#define VR_CFGD_BAKOPT (1 << 0)
/*
* Tally counters
*/
/*
* Misceleneous register 0
*/
#define VR_MISC0 0x80
#define VR_MISC0_TIMER0_EN (1 << 0)
/*
* Misceleneous register 1
*/
#define VR_MISC1 0x81
#define VR_MISC1_TIMER1_EN (1 << 0)
/*
* Power management
*/
#define VR_PWR 0x83
#define VR_PWR_DS0 (1 << 0)
/*
* Second interrupt register status
*/
#define VR_ISR1 0x84
#define VR_ISR1_TIMER0 (1 << 0)
/*
* Second interrupt register configuration
*/
#define VR_ICR1 0x86
#define VR_ICR1_TIMER0 VR_ISR1_TIMER0
#define VR_ICR1_TIMER1 VR_ISR1_TIMER1
#define VR_ICR1_PHYEVENT VR_ISR1_PHYEVENT
#define VR_ICR1_TDERR VR_ISR1_TDERR
#define VR_ICR1_SSRCI VR_ISR1_SSRCI
#define VR_ICR1_UINTR_SET VR_ISR1_UINTR_SET
#define VR_ICR1_UINTR_CLR VR_ISR1_UINTR_CLR
#define VR_ICR1_PWEI VR_ISR1_PWEI
/*
* Content Addressable Memory (CAM) stuff for the VT6105M
*/
#define VR_CAM_MASK 0x88
#define VR_CAM_CTRL 0x92
#define VR_CAM_CTRL_ENABLE (1 << 0)
#define VR_CAM_CTRL_RW (VR_CAM_CTRL_ENABLE | \
#define VR_CAM_CTRL_DONE (0)
#define VR_CAM_ADDR 0x93
/*
* MIB Control register
*/
#define VR_MIB_CTRL 0x94
/*
* MIB port
*/
#define VR_MIB_PORT 0x96
/*
* MIB data
*/
#define VR_MIB_DATA 0x97
/*
* Power configuration
*/
#define VR_PWRCFG_WOLEN (1 << 0)
/*
* Flow control, VT6105 and above
*/
#define VR_FCR0 0x98
#define VR_FCR0_RXBUFCOUNT VR_FCR0
#define VR_FCR1 0x99
#define VR_FCR1_HD_EN (1 << 0)
#define VR_FCR2 0x9a
#define VR_FCR2_PAUSE (VR_FCR2)
#define VR_TIMER0 0x9c
#define VR_TIMER1 0x9e
/*
* Receive desctriptor
*/
#define VR_RDES0_RXERR (1 << 0)
/*
* Transmit descriptor
*/
/* VLAN stuff is for VT6105M only */
(1 << 23) | (1 << 22) | (1 << 21) | \
(1 << 20) | (1 << 19) | (1 << 18) | \
(1 << 17) | (1 << 16))
(1 << 4) | (1 << 5) | (1 << 6) | \
(1 << 7) | (1 << 8) | (1 << 9) | (1 << 10))
#define VR_TDES3_SUPPRESS_INTR (1 << 0)
#endif /* _VRREG_H */