2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * CDDL HEADER START
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * The contents of this file are subject to the terms of the
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * Common Development and Distribution License (the "License").
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * You may not use this file except in compliance with the License.
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * See the License for the specific language governing permissions
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * and limitations under the License.
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * When distributing Covered Code, include this CDDL HEADER in each
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * If applicable, add the following below this CDDL HEADER, with the
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * fields enclosed by brackets "[]" replaced with your own identifying
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * information: Portions Copyright [yyyy] [name of copyright owner]
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * CDDL HEADER END
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * Use is subject to license terms.
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * Register definitions for the VIA Rhine ethernet adapters
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * MAC address
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * Receive Configuration
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * The thresholds denote the level in the FIFO before transmission
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * to host memory starts.
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_RXCFG_FIFO_THRESHOLD_BITS (VR_RXCFG_FIFO_THRESHOLD_0 | \
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_RXCFG_FIFO_THRESHOLD_32 (VR_RXCFG_FIFO_THRESHOLD_0)
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_RXCFG_FIFO_THRESHOLD_128 (VR_RXCFG_FIFO_THRESHOLD_1)
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_RXCFG_FIFO_THRESHOLD_256 (VR_RXCFG_FIFO_THRESHOLD_0 | \
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_RXCFG_FIFO_THRESHOLD_512 (VR_RXCFG_FIFO_THRESHOLD_2)
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_RXCFG_FIFO_THRESHOLD_768 (VR_RXCFG_FIFO_THRESHOLD_0 | \
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_RXCFG_FIFO_THRESHOLD_1024 (VR_RXCFG_FIFO_THRESHOLD_2 | \
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_RXCFG_FIFO_THRESHOLD_STFW (VR_RXCFG_FIFO_THRESHOLD_BITS)
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * Transmit Configuration
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * The transmission starts when the data in the FIFO reaches the threshold.
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * Store and Forward means that a transmission starts when a complete frame
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * is in the FIFO.
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_TXCFG_8021PQ_EN (1 << 0) /* VT6105M */
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_TXCFG_BACKOFF_NATIONAL (1 << 3) /* < VT6105M */
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_TXCFG_FIFO_THRESHOLD_BITS (VR_TXCFG_FIFO_THRESHOLD_0 | \
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_TXCFG_FIFO_THRESHOLD_256 (VR_TXCFG_FIFO_THRESHOLD_0)
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_TXCFG_FIFO_THRESHOLD_512 (VR_TXCFG_FIFO_THRESHOLD_1)
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_TXCFG_FIFO_THRESHOLD_1024 (VR_TXCFG_FIFO_THRESHOLD_0 | \
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_TXCFG_FIFO_THRESHOLD_STFW (VR_TXCFG_FIFO_THRESHOLD_BITS)
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * Chip control
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_CTRL0_DMA_GO (VR_CTRL0_DMA_ENABLE | \
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * Interrupt Status
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * This register reflects NIC status
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * The host reads it to determine the cause of the interrupt
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * This register must be cleared after power-up
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * Interrupt Configuration
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * All bits in this register correspond to the bits in the Interrupt Status
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * register Setting individual bits will enable the corresponding interrupt
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * This register defaults to all zeros on power up
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_ICR0_TX_BUF_UFLOW VR_ISR0_TX_BUF_UFLOW
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_ICR0_TX_FIFO_UFLOW VR_ISR0_TX_FIFO_UFLOW
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_ICR0_RX_FIFO_OFLOW VR_ISR0_RX_FIFO_OFLOW
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * Mulicast address registers (MAR), 8 bytes
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * VT6105M has a multicast/vlan filter and the hash bits are also used as
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * CAM data port
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * Start addresses of receive and transmit ring
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * VT6105M has 8 TX queues
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * Current and receive- and transmit descriptors.
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * These are listed in the VT6102 manual but not in the VT6105.
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders/* VIA secrets here */
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders/* VIA secrets here */
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * These are not in the datasheet but used in the 'fet' driver
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_MODE2_PCEROPT 0x80 /* VT6102 only */
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_MODE2_MRDPL 0x08 /* VT6107A1 and above */
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders/* VIA secrets here */
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * MII Configuration
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_MIIPHYADDR_ADDRBITS (VR_MIIPHYADDR_ADDR0 | \
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_MIIPHYADDR_POLLBITS ((1 << 7) | (1 << 6))
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_MIIPHYADDR_POLL1024 ((0 << 7) | (0 << 6))
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_MIIPHYADDR_POLL512 ((0 << 7) | (1 << 6))
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_MIIPHYADDR_POLL128 ((1 << 7) | (0 << 6))
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_MIIPHYADDR_POLL64 ((1 << 7) | (1 << 6))
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_MIISR_SPEED (1 << 0) /* VT6102 and VT6105 */
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_MIISR_LINKFAIL (1 << 1) /* VT6102 and VT6105 */
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_MIISR_DUPLEX (1 << 2) /* VT6105 only */
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_MIISR_PHYERR (1 << 3) /* VT6102 and VT6105 */
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_MIISR_PHYOPT (1 << 4) /* VT6102 only */
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_MIISR_NWAYLINKOK (1 << 4) /* VT6105 only */
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_MIISR_NWAYPAUSE (1 << 5) /* VT6105M */
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_MIISR_NWAYASMPAUSE (1 << 6) /* VT6105M */
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * Bus control
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_BCR0_DMABITS (VR_BCR0_DMA0|VR_BCR0_DMA1 | \
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_BCR0_DMA256 (VR_BCR0_DMA0|VR_BCR0_DMA1)
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_BCR0_DMA1024 (VR_BCR0_DMA0|VR_BCR0_DMA2)
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_BCR0_RX_FIFO_THRESHOLD_BITS (VR_BCR0_RX_FIFO_THRESHOLD_0 | \
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_BCR0_RX_FIFO_THRESHOLD_32 (VR_BCR0_RX_FIFO_THRESHOLD_0)
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_BCR0_RX_FIFO_THRESHOLD_128 (VR_BCR0_RX_FIFO_THRESHOLD_1)
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_BCR0_RX_FIFO_THRESHOLD_256 (VR_BCR0_RX_FIFO_THRESHOLD_0 | \
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_BCR0_RX_FIFO_THRESHOLD_512 (VR_BCR0_RX_FIFO_THRESHOLD_2)
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_BCR0_RX_FIFO_THRESHOLD_768 (VR_BCR0_RX_FIFO_THRESHOLD_0 | \
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_BCR0_RX_FIFO_THRESHOLD_1024 (VR_BCR0_RX_FIFO_THRESHOLD_1 | \
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_BCR0_RX_FIFO_THRESHOLD_STFW (VR_BCR0_RX_FIFO_THRESHOLD_BITS)
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_BCR1_TX_FIFO_THRESHOLD_BITS (VR_BCR1_TX_FIFO_THRESHOLD_0 | \
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_BCR1_TX_FIFO_THRESHOLD_256 (VR_BCR1_TX_FIFO_THRESHOLD_0)
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_BCR1_TX_FIFO_THRESHOLD_512 (VR_BCR1_TX_FIFO_THRESHOLD_1)
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_BCR1_TX_FIFO_THRESHOLD_1024 (VR_BCR1_TX_FIFO_THRESHOLD_0 | \
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_BCR1_TX_FIFO_THRESHOLD_STFW (VR_BCR1_FIFO_THRESHOLD_BITS)
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_BCR1_VLANFILTER (1 << 7) /* VT6105M */
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * MII Configuration
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * EEPROM Config / Status
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * Chip Configuration A
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_CFGA_PRE_ACPI_WAKEUP (1 << 0) /* VT6105M */
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_CFGA_WAKEUP_PANIC (1 << 1) /* VT6105M */
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_CFGA_VLANTAG_INCRC (1 << 5) /* VT6105M */
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * Chip Configuration B
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * Chip Configuration C
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * Chip Configuration D
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_CFGD_TAG_ON_SNAP (1 << 5) /* VT6105M */
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * Tally counters
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * Misceleneous register 0
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * Misceleneous register 1
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * Power management
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * Second interrupt register status
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * Second interrupt register configuration
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * Content Addressable Memory (CAM) stuff for the VT6105M
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_CAM_CTRL_WRITE (VR_CAM_CTRL_ENABLE | VR_CAM_CTRL_WR)
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_CAM_CTRL_READ (VR_CAM_CTRL_ENABLE | VR_CAM_CTRL_RD)
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * MIB Control register
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * Power configuration
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * Flow control, VT6105 and above
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_FCR1_PAUSEOFFBITS ((1 << 5) | (1 << 4))
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_FCR1_PAUSEOFF_24 ((0 << 5) | (0 << 4))
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_FCR1_PAUSEOFF_32 ((0 << 5) | (1 << 4))
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_FCR1_PAUSEOFF_48 ((1 << 5) | (0 << 4))
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_FCR1_PAUSEOFF_64 ((1 << 5) | (1 << 4))
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_FCR1_PAUSEONBITS ((1 << 7) | (1 << 6))
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_FCR1_PAUSEON_04 ((0 << 7) | (0 << 6))
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_FCR1_PAUSEON_08 ((0 << 7) | (1 << 6))
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_FCR1_PAUSEON_16 ((1 << 7) | (0 << 6))
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_FCR1_PAUSEON_24 ((1 << 7) | (1 << 6))
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_TIMER0_TIMEOUT VR_TIMER0 /* 16 bits */
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_TIMER1_TIMEOUT VR_TIMER1 /* 16 bits */
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_CRC_PATTERN0 0xb0 /* 32 bits, VT6105M */
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_CRC_PATTERN1 0xb4 /* 32 bits, VT6105M */
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_CRC_PATTERN2 0xb8 /* 32 bits, VT6105M */
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_CRC_PATTERN3 0xbC /* 32 bits, VT6105M */
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * Receive desctriptor
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_RDES0_VIDHIT (1 << 14) /* VT6105M or reserved */
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_RDES0_ABN ((1 << 27) | (1 << 28) | (1 << 29) | (1 << 30))
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders * Transmit descriptor
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_TDES0_NCR ((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3))
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders/* VLAN stuff is for VT6105M only */
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_TDES0_VLANID ((1 << 27) | (1 << 26) | (1 << 25) | (1 << 24) \
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_TDES0_VLANPRI ((1 << 30) | (1 << 29) | (1 << 28))
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_TDES1_LEN ((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | \
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#define VR_TDES1_STP (1 << 21) /* EDP/STP are flipped in DS6105! */
2ca5b6595b95478e6568b0e77c6c83c8a870867aJoost Mulders#endif /* _VRREG_H */