urtw_reg.h revision dfa03ef6809f806ad32c097e1f909a56bcaa247e
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
/*
* Copyright (c) 2008 Weongyo Jeong
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
* redistribution must be conditioned upon including a substantially
* similar Disclaimer requirement for further binary redistribution.
*
* NO WARRANTY
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGES.
*/
#ifndef _URTW_REG_H
#define _URTW_REG_H
#ifdef __cplusplus
extern "C" {
#endif
/*
* Known hardware revisions.
*/
#define URTW_HWREV_8187 0x01
#define URTW_HWREV_8187_B 0x02
#define URTW_HWREV_8187_D 0x04
#define URTW_HWREV_8187B 0x08
#define URTW_HWREV_8187B_B 0x10
#define URTW_HWREV_8187B_D 0x20
#define URTW_HWREV_8187B_E 0x40
/* for 8187 */
#define URTW_BRSR_MBR_8185 (0x0fff)
#define URTW_RESP_MAX_RATE_SHIFT (4)
#define URTW_RESP_MIN_RATE_SHIFT (0)
#define URTW_CMD_TX_ENABLE (0x4)
#define URTW_CMD_RX_ENABLE (0x8)
#define URTW_CMD_RST (0x10)
#define URTW_TX_LONGRETRY (7 << 0)
#define URTW_TX_LOOPBACK_SHIFT (17)
#define URTW_TX_LOOPBACK_NONE (0 << URTW_TX_LOOPBACK_SHIFT)
#define URTW_TX_LOOPBACK_MASK (0x60000)
#define URTW_TX_DPRETRY_MASK (0xff00)
#define URTW_TX_RTSRETRY_MASK (0xff)
#define URTW_TX_DPRETRY_SHIFT (0)
#define URTW_TX_RTSRETRY_SHIFT (8)
#define URTW_TX_NOCRC (0x10000)
#define URTW_TX_MXDMA_MASK (0xe00000)
#define URTW_TX_MXDMA_SHIFT (21)
#define URTW_TX_CWMIN (0x80000000)
#define URTW_TX_NOICV (0x80000)
#define URTW_RX_FILTER_MASK \
(1 << 21) |\
#define URTW_RX_FILTER_ALLMAC (0x00000001)
#define URTW_RX_FILTER_NICMAC (0x00000002)
#define URTW_RX_FILTER_MCAST (0x00000004)
#define URTW_RX_FILTER_BCAST (0x00000008)
#define URTW_RX_FILTER_CRCERR (0x00000020)
#define URTW_RX_FILTER_ICVERR (0x00001000)
#define URTW_RX_FILTER_DATA (0x00040000)
#define URTW_RX_FILTER_CTL (0x00080000)
#define URTW_RX_FILTER_MNG (0x00100000)
#define URTW_RX_FILTER_PWR (0x00400000)
#define URTW_RX_CHECK_BSSID (0x00800000)
#define URTW_RX_FIFO_THRESHOLD_SHIFT (13)
#define URTW_RX_FIFO_THRESHOLD_128 (3)
#define URTW_RX_FIFO_THRESHOLD_256 (4)
#define URTW_RX_FIFO_THRESHOLD_512 (5)
#define URTW_RX_FIFO_THRESHOLD_1024 (6)
#define URTW_RX_AUTORESETPHY_SHIFT (28)
#define URTW_MAX_RX_DMA_2048 (0x1c00)
#define URTW_MAX_RX_DMA_1024 (6)
#define URTW_MAX_RX_DMA_SHIFT (10)
#define URTW_RCR_ONLYERLPKT (0x80000000)
#define URTW_EPROM_CMD_NORMAL (0x0)
#define URTW_EPROM_CMD_NORMAL_MODE \
#define URTW_EPROM_CMD_LOAD (0x1)
#define URTW_EPROM_CMD_PROGRAM (0x2)
#define URTW_EPROM_CMD_PROGRAM_MODE \
#define URTW_EPROM_CMD_CONFIG (0x3)
#define URTW_EPROM_CMD_SHIFT (6)
#define URTW_EPROM_READBIT (0x1)
#define URTW_EPROM_WRITEBIT (0x2)
#define URTW_EPROM_CK (0x4)
#define URTW_EPROM_CS (0x8)
#define URTW_8187_8225_ANAPARAM_ON (0xa0000a59)
#define URTW_8187B_8225_ANAPARAM_ON (0x45090658)
#define URTW_MSR_LINK_SHIFT (2)
#define URTW_MSR_LINK_NONE (0 << URTW_MSR_LINK_SHIFT)
#define URTW_CONFIG3_ANAPARAM_WRITE (0x40)
#define URTW_CONFIG3_ANAPARAM_W_SHIFT (6)
#define URTW_CONFIG3_GNT_SELECT (0x80)
#define URTW_8187_8225_ANAPARAM2_ON (0x860c7312)
#define URTW_8187B_8225_ANAPARAM2_ON (0x727f3f52)
#define URTW_HSSI_PARA 0x0094
#define URTW_TX_AGC_CTL_PERPACKET_GAIN (0x1)
#define URTW_TX_AGC_CTL_PERPACKET_ANTSEL (0x2)
#define URTW_TX_AGC_CTL_FEEDBACK_ANT (0x4)
#define URTW_CW_CONF_PERPACKET_RETRY (0x2)
#define URTW_CW_CONF_PERPACKET_CW (0x1)
#define URTW_RATE_FALLBACK_ENABLE (0x80)
#define URTW_8187B_HWREV_8187B_B (0x0)
#define URTW_8187B_HWREV_8187B_D (0x1)
#define URTW_8187B_HWREV_8187B_E (0x2)
#define URTW_8187B_8225_ANAPARAM3_ON (0x0)
/* for EEPROM */
#define URTW_EPROM_TXPW_BASE 0x05
#define URTW_EPROM_RFCHIPID 0x06
#define URTW_EPROM_RFCHIPID_RTL8225U (5)
#define URTW_EPROM_MACADDR 0x07
#define URTW_EPROM_TXPW0 0x16
#define URTW_EPROM_TXPW2 0x1b
#define URTW_EPROM_TXPW1 0x3d
#define URTW_EPROM_SWREV 0x3f
#define URTW_EPROM_CID_MASK (0xff)
#define URTW_EPROM_CID_RSVD0 (0x00)
#define URTW_EPROM_CID_RSVD1 (0xff)
#define URTW_EPROM_CID_ALPHA0 (0x01)
#define URTW_EPROM_CID_SERCOMM_PS (0x02)
#define URTW_EPROM_CID_HW_LED (0x03)
/* LED */
#define URTW_CID_DEFAULT 0
#define URTW_CID_8187_ALPHA0 1
#define URTW_CID_8187_SERCOMM_PS 2
#define URTW_CID_8187_HW_LED 3
#define URTW_SW_LED_MODE0 0
#define URTW_SW_LED_MODE1 1
#define URTW_SW_LED_MODE2 2
#define URTW_SW_LED_MODE3 3
#define URTW_HW_LED 4
#define URTW_LED_CTL_POWER_ON 0
#define URTW_LED_CTL_LINK 2
#define URTW_LED_CTL_TX 4
#define URTW_LED_PIN_GPIO0 0
#define URTW_LED_PIN_LED0 1
#define URTW_LED_PIN_LED1 2
#define URTW_LED_UNKNOWN 0
#define URTW_LED_ON 1
#define URTW_LED_OFF 2
#define URTW_LED_BLINK_NORMAL 3
#define URTW_LED_BLINK_SLOWLY 4
#define URTW_LED_POWER_ON_BLINK 5
#define URTW_LED_SCAN_BLINK 6
#define URTW_LED_NO_LINK_BLINK 7
#define URTW_LED_BLINK_CM3 8
/* for extra area */
#define URTW_EPROM_DISABLE 0
#define URTW_EPROM_ENABLE 1
#define URTW_EPROM_DELAY 10
#define URTW_8187_GETREGS_REQ 5
#define URTW_8187_SETREGS_REQ 5
#define URTW_8225_RF_MAX_SENS 6
#define URTW_8225_RF_DEF_SENS 4
#define URTW_DEFAULT_RTS_RETRY 7
#define URTW_DEFAULT_TX_RETRY 7
#define URTW_DEFAULT_RTS_THRESHOLD 2342U
#ifdef __cplusplus
}
#endif
#endif /* _URTW_REG_H */