/*
* @(#)adm8511reg.h 1.1 09/06/20
* Register dehinitsions of ADMtek ADM8511 Fast Ethernet to USB controller.
* Codeded by Masayuki Murayama(KHF04453@nifty.ne.jp)
* This file is public domain.
*/
#ifndef __ADM8511_H__
#define __ADM8511_H__
/* Ethernet control register 0: offset 0 */
#define EC0_BITS \
"\020" \
"\010TXE" \
"\007RXE" \
"\006RXFCE" \
"\005WOE" \
"\004RXSA" \
"\003SBO" \
"\002RXMA" \
"\001RXCS"
/* Ethernet control register 1: offset 1 */
#define EC1_BITS \
"\020" \
"\006FD" \
"\005100M" \
"\004RM"
/* Ethernet control register 2: offset 2 */
#define EC2_BITS \
"\020" \
"\010MEPS" \
"\007RPNC" \
"\006LEEPRS" \
"\005EEPRW" \
"\004LB" \
"\003PROM" \
"\002RXBP" \
"\001EP3RC"
/* Recieve Packet number based Flow Control register: offset 0x1a */
/* Occupied Recieve FIFO based Flow Control register: offset 0x1b */
/* EP1 control register: offset 0x1c */
#define EP1C_BITS \
"\020" \
"\010EP1S0E"
/* Rx FIFO Control register: offset 0x1d */
/* EEPROM offset register: offset 0x20 */
/* EEPROM access control register: offset 0x23 */
#define EECTRL_BITS \
"\020" \
"\003DONE" \
"\002RD" \
"\001WR"
/* PHY control register: offset 28 */
#define PHYCTRL_BITS \
"\020" \
"\010DO" \
"\007RDPHY" \
"\006WRPHY"
/* Internal PHY control register: offset 7b */
#define IPHYC_BITS \
"\020" \
"\002EPHY" \
"\001PHYR"
/* GPIO45 register: offset 7c */
/* GPIO01 register: offset 7e */
/* GPIO23 register: offset 7f */
/* rx status at the end of received packets */
/* byte 0 and 1 is packet length in little endian */
/* byte 2 is receive status */
#define RSR_ERRORS \
#define RSR_BITS \
"\020" \
"\005DRIBBLE" \
"\004CRC" \
"\003RUNT" \
"\002LONG" \
"\001MULTI"
/* byte 3 is reserved */
/* TEST register: offset 80 */
#endif /* __ADM8511_H__ */