49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * Copyright (c) 2009-2015 Solarflare Communications Inc.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * All rights reserved.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * Redistribution and use in source and binary forms, with or without
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * modification, are permitted provided that the following conditions are met:
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * 1. Redistributions of source code must retain the above copyright notice,
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * this list of conditions and the following disclaimer.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * 2. Redistributions in binary form must reproduce the above copyright notice,
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * this list of conditions and the following disclaimer in the documentation
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * and/or other materials provided with the distribution.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * The views and conclusions contained in the software and documentation are
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * those of the authors and should not be interpreted as representing official
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * policies, either expressed or implied, of the FreeBSD Project.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA);
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore /* Initialize the transmit descriptor cache */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_TX_DC_BASE_ADR, tx_base);
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore EFX_BAR_WRITEO(enp, FR_AZ_SRM_TX_DC_CFG_REG, &oword);
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore EFX_POPULATE_OWORD_1(oword, FRF_AZ_TX_DC_SIZE, EFX_TXQ_DC_SIZE);
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore EFX_BAR_WRITEO(enp, FR_AZ_TX_DC_CFG_REG, &oword);
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore /* Initialize the receive descriptor cache */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_RX_DC_BASE_ADR, rx_base);
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore EFX_BAR_WRITEO(enp, FR_AZ_SRM_RX_DC_CFG_REG, &oword);
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DC_SIZE, EFX_RXQ_DC_SIZE);
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore EFX_BAR_WRITEO(enp, FR_AZ_RX_DC_CFG_REG, &oword);
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore /* Set receive descriptor pre-fetch low water mark */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DC_PF_LWM, 56);
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore EFX_BAR_WRITEO(enp, FR_AZ_RX_DC_PF_WM_REG, &oword);
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore /* Set the event queue to use for SRAM updates */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_UPD_EVQ_ID, 0);
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore EFX_BAR_WRITEO(enp, FR_AZ_SRM_UPD_EVQ_REG, &oword);
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA);
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore /* Reconfigure into HALF buffer table mode */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore EFX_POPULATE_OWORD_1(oword, FRF_AZ_BUF_TBL_MODE, 0);
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_CFG_REG, &oword);
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * Move the descriptor caches up to the top of SRAM, and test
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * all of SRAM below them. We only miss out one row here.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_RX_DC_BASE_ADR, rows);
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore EFX_BAR_WRITEO(enp, FR_AZ_SRM_RX_DC_CFG_REG, &oword);
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_TX_DC_BASE_ADR, rows + 1);
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore EFX_BAR_WRITEO(enp, FR_AZ_SRM_TX_DC_CFG_REG, &oword);
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * Write the pattern through BUF_HALF_TBL. Write
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * in 64 entry batches, waiting 1us in between each batch
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * to guarantee not to overflow the SRAM fifo
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore for (wptr = 0, rptr = 0; wptr < rows; ++wptr) {
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore EFX_BAR_TBL_WRITEQ(enp, FR_AZ_BUF_HALF_TBL, wptr, &qword);
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore EFX_BAR_TBL_READQ(enp, FR_AZ_BUF_HALF_TBL, rptr,
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore /* And do the same negated */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore for (wptr = 0, rptr = 0; wptr < rows; ++wptr) {
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore EFX_BAR_TBL_WRITEQ(enp, FR_AZ_BUF_HALF_TBL, wptr, &qword);
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore EFX_BAR_TBL_READQ(enp, FR_AZ_BUF_HALF_TBL, rptr,
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore /* Restore back to FULL buffer table mode */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore EFX_POPULATE_OWORD_1(oword, FRF_AZ_BUF_TBL_MODE, 1);
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_CFG_REG, &oword);
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * We don't need to reconfigure SRAM again because the API
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * requires efx_nic_fini() to be called after an sram test.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore /* Restore back to FULL buffer table mode */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore EFX_POPULATE_OWORD_1(oword, FRF_AZ_BUF_TBL_MODE, 1);
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_CFG_REG, &oword);
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#endif /* EFSYS_OPT_DIAG */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#endif /* EFSYS_OPT_SIENA */