49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * Copyright (c) 2012-2015 Solarflare Communications Inc.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * All rights reserved.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * Redistribution and use in source and binary forms, with or without
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * modification, are permitted provided that the following conditions are met:
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * 1. Redistributions of source code must retain the above copyright notice,
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * this list of conditions and the following disclaimer.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * 2. Redistributions in binary form must reproduce the above copyright notice,
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * this list of conditions and the following disclaimer in the documentation
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * and/or other materials provided with the distribution.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * The views and conclusions contained in the software and documentation are
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * those of the authors and should not be interpreted as representing official
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * policies, either expressed or implied, of the FreeBSD Project.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore/* These structures define the layouts for the TLV items stored in static and
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * dynamic configuration partitions in NVRAM for EF10 (Huntington etc.).
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * They contain the same sort of information that was kept in the
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * siena_mc_static_config_hdr_t and siena_mc_dynamic_config_hdr_t structures
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * (defined in <ci/mgmt/mc_flash_layout.h> and <ci/mgmt/mc_dynamic_cfg.h>) for
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * These are used directly by the MC and should also be usable directly on host
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * systems which are little-endian and do not do strange things with structure
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * padding. (Big-endian host systems will require some byte-swapping.)
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * Please refer to SF-108797-SW for a general overview of the TLV partition
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * The current tag IDs have a general structure: with the exception of the
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * special values defined in the document, they are of the form 0xLTTTNNNN,
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * - L is a location, indicating where this tag is expected to be found:
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * 0: static configuration
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * 1: dynamic configuration
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * 2: firmware internal use
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * 3: license partition
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * - TTT is a type, which is just a unique value. The same type value
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * might appear in both locations, indicating a relationship between
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * the items (e.g. static and dynamic VPD below).
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * - NNNN is an index of some form. Some item types are per-port, some
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * are per-PF, some are per-partition-type.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * As with the previous Siena structures, each structure here is laid out
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * carefully: values are aligned to their natural boundary, with explicit
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * padding fields added where necessary. (No, technically this does not
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * absolutely guarantee portability. But, in practice, compilers are generally
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * sensible enough not to introduce completely pointless padding, and it works
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * well enough.)
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore/* ----------------------------------------------------------------------------
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * General structure (defined by SF-108797-SW)
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * ----------------------------------------------------------------------------
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore/* The "end" tag.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * (Note that this is *not* followed by length or value fields: anything after
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * the tag itself is irrelevant.)
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore/* Other special reserved tag values.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore/* TLV partition header.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * In a TLV partition, this must be the first item in the sequence, at offset
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_TAG_PARTITION_HEADER (0xEF10DA7A)
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore/* 0 indicates the default segment (always located at offset 0), while other values
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * are for RFID-selectable presets that should immediately follow the default segment.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * The default segment may also have preset > 0, which means that it is a preset
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * selected through an RFID command and copied by FW to the location at offset 0. */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore/* TLV partition trailer.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * In a TLV partition, this must be the last item in the sequence, immediately
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * preceding the TLV_TAG_END word.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_TAG_PARTITION_TRAILER (0xEF101A57)
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore/* Appendable TLV partition header.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * In an appendable TLV partition, this must be the first item in the sequence,
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * at offset 0. (Note that, unlike the configuration partitions, there is no
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * trailer before the TLV_TAG_END word.)
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_TAG_APPENDABLE_PARTITION_HEADER (0xEF10ADA7)
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore/* ----------------------------------------------------------------------------
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * Configuration items
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * ----------------------------------------------------------------------------
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore/* NIC global capabilities.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_TAG_GLOBAL_CAPABILITIES (0x00010000)
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore/* Siena-style per-port MAC address allocation.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * There are <count> addresses, starting at <base_address> and incrementing
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * by adding <stride> to the low-order byte(s).
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * (See also TLV_TAG_GLOBAL_MAC for an alternative, specifying a global pool
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * of contiguous MAC addresses for the firmware to allocate as it sees fit.)
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_TAG_PORT_MAC(port) (0x00020000 + (port))
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore/* Static VPD.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * This is the portion of VPD which is set at manufacturing time and not
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * expected to change. It is formatted as a standard PCI VPD block. There are
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * global and per-pf TLVs for this, the global TLV is new for Medford and is
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * used in preference to the per-pf TLV.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_TAG_PF_STATIC_VPD(pf) (0x00030000 + (pf))
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_TAG_GLOBAL_STATIC_VPD (0x001f0000)
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore/* Dynamic VPD.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * This is the portion of VPD which may be changed (e.g. by firmware updates).
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * It is formatted as a standard PCI VPD block. There are global and per-pf TLVs
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * for this, the global TLV is new for Medford and is used in preference to the
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * per-pf TLV.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_TAG_PF_DYNAMIC_VPD(pf) (0x10030000 + (pf))
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_TAG_GLOBAL_DYNAMIC_VPD (0x10200000)
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore/* "DBI" PCI config space changes.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * This is a set of edits made to the default PCI config space values before
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * the device is allowed to enumerate. There are global and per-pf TLVs for
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * this, the global TLV is new for Medford and is used in preference to the
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * per-pf TLV.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_TAG_PF_DBI(pf) (0x00040000 + (pf))
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore/* Partition subtype codes.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * A subtype may optionally be stored for each type of partition present in
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * the NVRAM. For example, this may be used to allow a generic firmware update
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * utility to select a specific variant of firmware for a specific variant of
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * The description[] field is an optional string which is returned in the
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * MC_CMD_NVRAM_METADATA response if present.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_TAG_PARTITION_SUBTYPE(type) (0x00050000 + (type))
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore/* Partition version codes.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * A version may optionally be stored for each type of partition present in
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * the NVRAM. This provides a standard way of tracking the currently stored
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * version of each of the various component images.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_TAG_PARTITION_VERSION(type) (0x10060000 + (type))
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore/* Global PCIe configuration */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_TAG_GLOBAL_PCIE_CONFIG (0x10070000)
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore int16_t max_pf_number; /**< Largest PF RID (lower PFs may be hidden) */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore uint16_t pf_aper; /**< BIU aperture for PF BAR2 */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore uint16_t vf_aper; /**< BIU aperture for VF BAR0 */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_MAX_PF_DEFAULT (-1) /* Use FW default for largest PF RID */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_APER_DEFAULT (0xFFFF) /* Use FW default for a given aperture */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore/* Per-PF configuration. Note that not all these fields are necessarily useful
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * as the apertures are constrained by the BIU settings (the one case we do
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * use is to make BAR2 bigger than the BIU thinks to reserve space), but we can
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * tidy things up later */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_TAG_PF_PCIE_CONFIG(pf) (0x10080000 + (pf))
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore/* Development ONLY. This is a single TLV tag for all the gubbins
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * that can be set through the MC command-line other than the PCIe
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * settings. This is a temporary measure. */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_TAG_TMP_GUBBINS (0x10090000) /* legacy symbol - do not use */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_TAG_TMP_GUBBINS_HUNT TLV_TAG_TMP_GUBBINS
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore /* Consumed by dpcpu.c */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_DPCPU_TX_STRIPE (1) /* No longer used, has no effect */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_DPCPU_BIU_TAGS (2) /* Use BIU tag manager */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_DPCPU_TX0_TAGS (4) /* tx0_tags is valid */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_DPCPU_TX1_TAGS (8) /* tx1_tags is valid */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_DPCPU_DL_TAGS (16) /* dl_tags is valid */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore /* Consumed by features.c */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore uint32_t dut_features; /* All 1s -> leave alone */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore int8_t with_rmon; /* 0 -> off, 1 -> on, -1 -> leave alone */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore /* Consumed by clocks_hunt.c */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore int8_t clk_mode; /* 0 -> off, 1 -> on, -1 -> leave alone */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore /* No longer used, superseded by TLV_TAG_DESCRIPTOR_CACHE_CONFIG. */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore/* Global port configuration
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * This is now deprecated in favour of a platform-provided default
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * and dynamic config override via tlv_global_port_options.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_TAG_GLOBAL_PORT_CONFIG (0x000a0000)
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore/* Firmware options.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * This is intended for user-configurable selection of optional firmware
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * features and variants.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * Initially, this consists only of the satellite CPU firmware variant
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * selection, but this tag could be extended in the future (using the
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * tag length to determine whether additional fields are present).
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_TAG_FIRMWARE_OPTIONS (0x100b0000)
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_FIRMWARE_VARIANT_DRIVER_SELECTED (0xffffffff)
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore/* These are the values for overriding the driver's choice; the definitions
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * are taken from MCDI so that they don't get out of step. Include
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * <ci/mgmt/mc_driver_pcol.h> or the equivalent from your driver's tree if
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * you need to use these constants.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_FIRMWARE_VARIANT_FULL_FEATURED MC_CMD_FW_FULL_FEATURED
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_FIRMWARE_VARIANT_LOW_LATENCY MC_CMD_FW_LOW_LATENCY
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_FIRMWARE_VARIANT_PACKED_STREAM MC_CMD_FW_PACKED_STREAM
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_FIRMWARE_VARIANT_HIGH_TX_RATE MC_CMD_FW_HIGH_TX_RATE
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_FIRMWARE_VARIANT_PACKED_STREAM_HASH_MODE_1 \
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore/* Voltage settings
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * Intended for boards with A0 silicon where the core voltage may
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * need tweaking. Most likely set once when the pass voltage is
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * determined. */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore uint16_t flags; /* Boards with high 0v9 settings may need active cooling */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore uint16_t target_voltage; /* In millivolts */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore /* Since the limits are meant to be centred to the target (and must at least
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * contain it) they need setting as well. */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore/* Clock configuration */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_TAG_CLOCK_CONFIG (0x000d0000) /* legacy symbol - do not use */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_TAG_CLOCK_CONFIG_HUNT TLV_TAG_CLOCK_CONFIG
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_TAG_CLOCK_CONFIG_MEDFORD (0x00100000)
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore/* EF10-style global pool of MAC addresses.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * There are <count> addresses, starting at <base_address>, which are
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * contiguous. Firmware is responsible for allocating addresses from this
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * pool to ports / PFs as appropriate.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_TAG_ATB_0V9_TARGET (0x000f0000) /* legacy symbol - do not use */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_TAG_ATB_0V9_TARGET_HUNT TLV_TAG_ATB_0V9_TARGET
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore/* The target value for the 0v9 power rail measured on-chip at the
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * analogue test bus */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore/* Global PCIe configuration, second revision. This represents the visible PFs
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * by a bitmap rather than having the number of the highest visible one. As such
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * it can (for a 16-PF chip) represent a superset of what TLV_TAG_GLOBAL_PCIE_CONFIG
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * can and it should be used in place of that tag in future (but compatibility with
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * the old tag will be left in the firmware indefinitely). */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_TAG_GLOBAL_PCIE_CONFIG_R2 (0x10100000)
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore uint16_t visible_pfs; /**< Bitmap of visible PFs */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore uint16_t pf_aper; /**< BIU aperture for PF BAR2 */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore uint16_t vf_aper; /**< BIU aperture for VF BAR0 */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore uint16_t int_aper; /**< BIU aperture for PF BAR4 and VF BAR2 */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore/* Dynamic port mode.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * Allows selecting alternate port configuration for platforms that support it
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * (e.g. 1x40G vs 2x10G on Milano, 1x40G vs 4x10G on Medford). This affects the
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * number of externally visible ports (and, hence, PF to port mapping), so must
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * be done at boot time.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * This tag supercedes tlv_global_port_config.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_TAG_GLOBAL_PORT_MODE (0x10110000)
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_PORT_MODE_DEFAULT (0xffffffff) /* Default for given platform */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_PORT_MODE_10G (0) /* 10G, single SFP/10G-KR */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_PORT_MODE_40G (1) /* 40G, single QSFP/40G-KR */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_PORT_MODE_10G_10G (2) /* 2x10G, dual SFP/10G-KR or single QSFP */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_PORT_MODE_40G_40G (3) /* 40G + 40G, dual QSFP/40G-KR (Greenport, Medford) */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_PORT_MODE_10G_10G_10G_10G (4) /* 2x10G + 2x10G, quad SFP/10G-KR or dual QSFP (Greenport, Medford) */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_PORT_MODE_10G_10G_10G_10G_Q (5) /* 4x10G, single QSFP, cage 0 (Medford) */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_PORT_MODE_40G_10G_10G (6) /* 1x40G + 2x10G, dual QSFP (Greenport, Medford) */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_PORT_MODE_10G_10G_40G (7) /* 2x10G + 1x40G, dual QSFP (Greenport, Medford) */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_PORT_MODE_10G_10G_10G_10G_Q2 (8) /* 4x10G, single QSFP, cage 1 (Medford) */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_PORT_MODE_MAX TLV_PORT_MODE_10G_10G_10G_10G_Q2
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore/* Type of the v-switch created implicitly by the firmware */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_TAG_VSWITCH_TYPE(port) (0x10120000 + (port))
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_VSWITCH_TYPE_DEFAULT (0xffffffff) /* Firmware default; equivalent to no TLV present for a given port */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore/* A VLAN tag for the v-port created implicitly by the firmware */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_TAG_VPORT_VLAN_TAG(pf) (0x10130000 + (pf))
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_VPORT_NO_VLAN_TAG (0xFFFFFFFF) /* Default in the absence of TLV for a given PF */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore/* Offset to be applied to the 0v9 setting, wherever it came from */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore/* A privilege mask given on reset to all non-admin PCIe functions (that is other than first-PF-per-port).
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * The meaning of particular bits is defined in mcdi_ef10.yml under MC_CMD_PRIVILEGE_MASK, see also bug 44583.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * TLV_TAG_PRIVILEGE_MASK_ADD specifies bits that should be added (ORed) to firmware default while
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * TLV_TAG_PRIVILEGE_MASK_REM specifies bits that should be removed (ANDed) from firmware default:
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * Initial_privilege_mask = (firmware_default_mask | privilege_mask_add) & ~privilege_mask_rem */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_TAG_PRIVILEGE_MASK (0x10150000) /* legacy symbol - do not use */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amorestruct tlv_privilege_mask { /* legacy structure - do not use */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_TAG_PRIVILEGE_MASK_ADD (0x10150000)
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_TAG_PRIVILEGE_MASK_REM (0x10160000)
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore/* Additional privileges given to all PFs.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_TAG_PRIVILEGE_MASK_ADD_ALL_PFS (0x10190000)
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore/* Additional privileges given to a selected PF.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * This tag takes precedence over TLV_TAG_PRIVILEGE_MASK_REM. */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_TAG_PRIVILEGE_MASK_ADD_SINGLE_PF(pf) (0x101A0000 + (pf))
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore/* Turning on/off the PFIOV mode.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * This tag only takes effect if TLV_TAG_VSWITCH_TYPE is missing or set to DEFAULT. */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_TAG_PFIOV(port) (0x10170000 + (port))
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore/* Multicast filter chaining mode selection.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * When enabled, multicast packets are delivered to all recipients of all
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * matching multicast filters, with the exception that IP multicast filters
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * will steal traffic from MAC multicast filters on a per-function basis.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * (New behaviour.)
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * When disabled, multicast packets will always be delivered only to the
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * recipients of the highest priority matching multicast filter.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * (Legacy behaviour.)
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * The DEFAULT mode (which is the same as the tag not being present at all)
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * is equivalent to ENABLED in production builds, and DISABLED in eftest
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * This option is intended to provide run-time control over this feature
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * while it is being stabilised and may be withdrawn at some point in the
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * future; the new behaviour is intended to become the standard behaviour.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_TAG_MCAST_FILTER_CHAINING (0x10180000)
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_MCAST_FILTER_CHAINING_DEFAULT (0xffffffff)
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_MCAST_FILTER_CHAINING_DISABLED (0)
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_MCAST_FILTER_CHAINING_ENABLED (1)
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore/* Pacer rate limit per PF */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_TAG_RATE_LIMIT(pf) (0x101b0000 + (pf))
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * This setting allows OCSD to be disabled. This is a requirement for HP
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * servers to support PCI passthrough for virtualization.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * The DEFAULT mode (which is the same as the tag not being present) is
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * equivalent to ENABLED.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * This option is not used by the MCFW, and is entirely handled by the various
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * drivers that support OCSD, by reading the setting before they attempt
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * to enable OCSD.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore/* Descriptor cache config.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * Sets the sizes of the TX and RX descriptor caches as a power of 2. It also
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * sets the total number of VIs. When the number of VIs is reduced VIs are taken
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * away from the highest numbered port first, so a vi_count of 1024 means 1024
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * VIs on the first port and 0 on the second (on a Torino).
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_TAG_DESCRIPTOR_CACHE_CONFIG (0x101d0000)
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore/* RX event merging config (read batching).
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * Sets the global maximum number of events for the merging bins, and the
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore * global timeout configuration for the bins.
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_TAG_RX_EVENT_MERGING_CONFIG (0x101e0000)
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_RX_EVENT_MERGING_CONFIG_MAX_EVENTS_MAX ((1 << 4) - 1)
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_RX_EVENT_MERGING_MAX_EVENTS_DEFAULT 7
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_RX_EVENT_MERGING_TIMEOUT_NS_DEFAULT 8740
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#define TLV_TAG_PCIE_LINK_SETTINGS (0x101f0000)
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore uint16_t gen; /* Target PCIe generation: 1, 2, 3 */
49ef7e0638c8b771d8a136eae78b1c0f99acc8e0Garrett D'Amore#endif /* CI_MGMT_TLV_LAYOUT_H */