sfereg.h revision 23d366e350386ec109bfa9b2cf91225729a1a26b
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff * sfereg.h: SiS900/DP83815 register definition
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff * Copyright (c) 2002-2007 Masayuki Murayama. All rights reserved.
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff * Redistribution and use in source and binary forms, with or without
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff * modification, are permitted provided that the following conditions are met:
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff * 1. Redistributions of source code must retain the above copyright notice,
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff * this list of conditions and the following disclaimer.
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff * 2. Redistributions in binary form must reproduce the above copyright notice,
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff * this list of conditions and the following disclaimer in the documentation
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff * and/or other materials provided with the distribution.
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff * 3. Neither the name of the author nor the names of its contributors may be
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff * used to endorse or promote products derived from this software without
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f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#pragma ident "%Z%%M% %I% %E% SMI" /* sfe device driver */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff * Tx/Rx descriptor
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff volatile uint32_t d_cmdsts; /* command/status field */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff volatile uint32_t d_bufptr; /* ptr to the first fragment */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff/* CMDSTS common Bit Definition */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define CMDSTS_OWN 0x80000000U /* 1: data consumer owns */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define CMDSTS_MORE 0x40000000U /* Not the last descriptor */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define CMDSTS_SIZE 0x00000fffU /* Descriptor byte count */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff/* Transmit Status Bit Definition */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define CMDSTS_TFU 0x02000000U /* Transmit FIFO Underrun */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define CMDSTS_CRS 0x01000000U /* Carrier sense lost */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define CMDSTS_ED 0x00400000U /* Exessive deferrral */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define CMDSTS_OWC 0x00200000U /* Out of window collision */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define CMDSTS_EC 0x00100000U /* Excessive collision */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\040Own" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\037More" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\036Intr" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\035SupCrc" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\033Abort" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\032UnderRun" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\031NoCarrier" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\030Deferd" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\027ExcDefer" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\026OWColl" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\025ExcColl"
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\040Own" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\037More" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\036Intr" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\035IncCrc" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\032OverRun" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\031MCast" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\030UniMatch" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\027TooLong" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\026Runt" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\025RxISErr" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\024CrcErr" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\023FaErr" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\022LoopBk" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\021RxCol"
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff/* Receive Status Bit Definitions */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define CMDSTS_DEST 0x01800000U /* Destination class */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define CMDSTS_LONG 0x00400000U /* Too long packet received */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define CMDSTS_RUNT 0x00200000U /* Runt packet received */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define CMDSTS_ISE 0x00100000U /* Invalid symbol error */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define CMDSTS_COL 0x00010000U /* Collision activety */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff * Offsets of MAC Operational Registers
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define MEAR 0x08 /* alias for MII access register (sis900) */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define TXDP 0x20 /* Transmit descriptor pointer reg */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define TXCFG 0x24 /* Transmit configuration register */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define RXDP 0x30 /* Receive descriptor pointer reg */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define RXCFG 0x34 /* Receive configration register */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define FLOWCTL 0x38 /* Flow control register (sis900) */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define CCSR 0x3c /* Clock run status register (dp83815) */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define PCR 0x44 /* Pause control register (dp83815) */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define RFCR 0x48 /* Receive filter control register */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define PMCTL 0xb0 /* Power management control register */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define PMEVT 0xb4 /* Power management wake-up event reg */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define WAKECRC 0xbc /* Wake-up sample frame CRC register */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define WAKEMASK 0xc0 /* Wake-up sample frame mask register */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff/* Command register */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\011Reset" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\010SWI" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\006RxReset" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\005TxReset" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\004RxDisable" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\003RxEnable" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\002TxDisable" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\001TxEnable"
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff/* Configration register */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define CFG_SPEED100 0x40000000U /* 100Mbps (83815) */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define CFG_FDUP 0x20000000U /* full duplex (83815) */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define CFG_POL 0x10000000U /* 10Mbps polarity indication (83815) */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define CFG_ANEG_DN 0x08000000U /* auto negotiation done (83815) */
23d366e350386ec109bfa9b2cf91225729a1a26bduboff#define CFG_PHY_CFG 0x00fc0000U /* internal PHY configuration (83815) */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define CFG_PINT_ACEN 0x00020000U /* PHY interrupt auto clear (83815) */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define CFG_PAUSE_ADV 0x00010000U /* Advertise pause (83815) */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define CFG_ANEG_SEL 0x0000e000U /* Auto-nego default (83815) */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define CFG_EDB_MASTER 0x00002000U /* sis635, sis900B, sis96x */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define CFG_EXT_PHY 0x00001000U /* External PHY support (83815) */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define CFG_PHY_RST 0x00000400U /* Internal PHY reset (83815) */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define CFG_PHY_DIS 0x00000200U /* Internal PHY disable (83815) */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define CFG_FAIR_BCKOFF 0x00000200U /* sis635 & 900B */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define CFG_EUPHCOMP 0x00000100U /* DP83810 compatibility (83815) */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define CFG_REQALG 0x00000080U /* PCI Bus request algorithm */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define CFG_POW 0x00000020U /* Program out of window timer */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define CFG_EXD 0x00000010U /* Excessive deferral timer disable */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define CFG_PESEL 0x00000008U /* Parity error detection action */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define CFG_BROM_DIS 0x00000004U /* BootRom disable (83815) */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\040CFG_LNKSTS" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\037SPEED100" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\036FDUP" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\035POL" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\034ANEG_DN" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\022PINT_ACEN" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\021PAUSE_ADV" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\015EXT_PHY" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\013PHY_RST" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\012PHY_DIS" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\011EUPHCOMP" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\010REQALG" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\006POW" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\005EXD" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\004PESEL" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\003BROM_DIS" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\016EDB_EN" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\013RND_CNT" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\010REQALG" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\006POW" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\005EXD" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\004PESEL" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff/* Serial EEPROM access register */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define EROMAR_EECS 0x00000008U /* EEPROM chip select */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define EROMAR_EESK 0x00000004U /* EEPROM serial clock */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define EROMAR_EEDI 0x00000001U /* EEPROM data in + */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define EROMAR_EEREQ 0x00000400U /* for sis963 eeprom mamagement */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define EROMAR_EEDONE 0x00000200U /* for sis963 eeprom mamagement */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define EROMAR_EEGNT 0x00000100U /* for sis963 eeprom mamagement */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff/* PCI Test Control register */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define DISCARD_TEST 0x40000000U /* Discard timer test mode */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff/* Interrupt status register */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define ISR_DPERR 0x00800000U /* Detected parity error */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define ISR_SSERR 0x00400000U /* Signaled system error */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define ISR_RMABT 0x00200000U /* Received master abort */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define ISR_RTABT 0x00100000U /* Received target abort */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define ISR_RXSOVR 0x00010000U /* Received status FIFO overrun */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\035WakeEvt" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\034PauseEnd" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\033PauseST" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\032TXRCMP" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\031RXRCMP" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\030DPErr" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\027SSErr" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\026RMAbt" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\025RTAbt" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\021RxSOVR" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\020HIBErr" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\015SWI" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\013TxUrn" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\012TxIdle" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\011TxErr" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\010TxDesc" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\007TxOk" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\006RxORN" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\005RxIdle" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\004RxEarly" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\003RxErr" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\002RxDesc" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff/* Interrupt enable reigster */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff/* Enhanced PHY acces register */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff/* Transmit configuration register */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define TXCFG_CSI 0x80000000U /* carrier sense ignore */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define TXCFG_ATP 0x10000000U /* Automatic transmit padding */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define TXCFG_MXDMA 0x00700000U /* max dma burst size */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define TXCFG_FLTH 0x00003f00U /* Tx fill threshold */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define TXCFG_DRTH 0x0000003fU /* Tx drain threshold */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff/* RXCFG:43 Reveive configuration register */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define RXCFG_AEP 0x80000000U /* accept error packets */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define RXCFG_ARP 0x40000000U /* accept runt packets */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define RXCFG_ATX 0x10000000U /* accept transmit packets */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define RXCFG_AJAB 0x08000000U /* accept jabber packets */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define RXCFG_ALP_DP83815 0x08000000U /* accept long pakets */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define RXCFG_MXDMA 0x00700000U /* max dma burst size */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define RXCFG_DRTH 0x0000003eU /* Rx drain threshold */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define RXCFG_BITS "\020\040AEP\037ARP\035ATX\034AJAB"
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff/* FLWCRL:0x38 Flow Control register */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define FLOWCTL_FLOWEN 0x00000001U /* flow control enable */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff/* CCSR:0x3c Clock run Control status register */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff/* PCR:0x44 Pause control/status register (DP83815) */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define PCR_PS_MCAST 0x40000000U /* Pause on multicast */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define PCR_PS_RCVD 0x00400000U /* Pause frame receved */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define PCR_MLD_EN 0x00010000U /* Manual load enable */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define PCR_PAUSE_CNT 0x0000ffffU /* Pause counter value */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\040PCR_PSEN" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\037PCR_PS_MCAST" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\036PCR_PS_DA" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\030PCR_PS_ACT" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\027PCR_PS_RCVD" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\026PCR_PSNEG" \
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff "\021PCR_MLD_EN"
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff/* RFCR:0x48 Receive filter control register */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define RFCR_RFEN 0x80000000U /* receive filter enable */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define RFCR_AAB 0x40000000U /* accept all broadcast */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define RFCR_AAM 0x20000000U /* accept all multicast */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define RFCR_AAP 0x10000000U /* accept all physical */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define RFCR_APM_DP83815 0x08000000U /* accept perfect match */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define RFCR_APAT_DP83815 0x07800000U /* accept on pattern match */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define RFCR_AARP_DP83815 0x00400000U /* accept arp packets */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define RFCR_MHEN_DP83815 0x00200000U /* multicast hash enable */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define RFCR_UHEN_DP83815 0x00100000U /* unicast hash enable */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define RFCR_ULM_DP83815 0x00080000U /* U/L bit mask */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#define RFCR_RFADDR_SIS900 0x000f0000U /* receive filter address */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff/* Receive filter offset */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff/* Receive filter data register */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff/* dp83815 Silicon revision register */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff/* sis900 revisions */
f8919bdadda3ebb97bd55cc14a16e0271ed57615duboff#endif /* _SFEREG_H_ */