sdhost.h revision 9a5113a6958e1e7b93b09e74189ebc16d2a68aff
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2009 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#ifndef _SYS_SDCARD_SDHOST_H
#define _SYS_SDCARD_SDHOST_H
/*
* The entire contents of this file are private the SD Host driver
* implementation.
*/
#include <sys/inttypes.h>
#define BIT(x) (1 << (x))
/*
* SD Host Spec says that a controller can support up to 6 different
* slots, each with its own register set.
*/
#define SDHOST_MAXSLOTS 6
/*
* SD Host specific PCI configuration register.
*/
#define SLOTINFO 0x40
#define SLOTINFO_NSLOT_SHFT 4
#define SLOTINFO_BAR_SHFT 0
#define SLOTINFO_NSLOT(x) \
#define SLOTINFO_BAR(x) \
(((x) & SLOTINFO_BAR_MSK) >> SLOTINFO_BAR_SHFT)
/*
* Slot-specific CSRs
*/
/* REG_BLKSZ bits */
#define BLKSZ_XFR_BLK_SIZE_MASK (0x0fff)
#define BLKSZ_BOUNDARY_4K (0 << 12)
/* REG_XFR_MODE bits */
#define XFR_MODE_DMA_EN BIT(0)
/* REG_COMMAND bits */
#define COMMAND_TYPE
#define COMMAND_TYPE_NORM (0 << 6)
#define COMMAND_RESP_NONE 0
/* REG_PRS bits */
#define PRS_CMD_INHIBIT BIT(0)
#define PRS_INHIBIT \
#define PRS_DAT_SIG \
/* REG_HOST_CONTROL bits */
#define HOST_CONTROL_LED_ON BIT(0)
#define HOST_CONTROL_DMA_SDMA (0 << 3)
/* REG_POWER_CONTROL bits */
#define POWER_CONTROL_BUS_POWER BIT(0)
/* REG_BLOCK_GAP_CONTROL bits */
#define BLOCK_GAP_CONTROL_STOP BIT(0)
/* REG_WAKEUP_CONTROL bits */
#define WAKEUP_CONTROL_INTERRUPT BIT(0)
/* REG_CLOCK_CONTROL bits */
#define CLOCK_CONTROL_INT_CLOCK_EN BIT(0)
#define CLOCK_CONTROL_FREQ_SHIFT 8
/* REG_TIMEOUT_CONTROL bits */
#define TIMEOUT_TIMECLK_2_27 (0xe)
/* not listing them all here... but it goes on */
#define TIMEOUT_TIMECLK_2_13 (0x0)
/* REG_SOFT_RESET bits */
#define SOFT_RESET_ALL BIT(0)
/* REG_INT_{STAT,EN,MASK} bits */
/* REG_ERR_{STAT,EN,MASK} bits */
#define ERR_CMD_TMO BIT(0)
/* REG_ACMD12_ERROR bits */
#define ACMD12_ERROR_NOT_EXECUTED BIT(0)
/* REG_CAPAB bits */
#define CAPAB_TIMEOUT_FREQ_SHIFT 0
#define CAPAB_TIMEOUT_FREQ_MASK (0x3f << 0)
#define CAPAB_BASE_FREQ_SHIFT 8
#define CAPAB_MAXBLK_512 (0 << 16)
/* REG_MAX_CURRENT bits */
#define MAX_CURRENT_33V_SHIFT 0
#define MAX_CURRENT_33V_MASK (0xff << 0)
#define MAX_CURRENT_30V_SHIFT 8
#define MAX_CURRENT_18V_SHIFT 16
/* REG_VERSION bits */
#define VERSION_VENDOR_SHIFT 8
#define VERSION_SDHOST_MASK 0xff
#define VERSION_SDHOST_1 0
#define VERSION_SDHOST_2 1
/* REG_ADMA_ERROR bits */
#define ADMA_ERROR_STATE_ST_STOP 0
#define ADMA_ERROR_STATE_ST_FDS 1
#define ADMA_ERROR_STATE_ST_TFR 3
#define ADMA_ERROR_STATE_MASK 0x3
/*
* Properties.
*/
#define SDHOST_PROP_ENABLE_MSI "enable-msi"
#define SDHOST_PROP_ENABLE_MSIX "enable-msix"
#define SDHOST_PROP_FORCE_PIO "force-pio"
#define SDHOST_PROP_FORCE_DMA "force-dma"
#endif /* _SYS_SDCARD_SDHOST_H */