4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore * CDDL HEADER START
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore * The contents of this file are subject to the terms of the
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore * Common Development and Distribution License (the "License").
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore * You may not use this file except in compliance with the License.
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore * or http://www.opensolaris.org/os/licensing.
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore * See the License for the specific language governing permissions
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore * and limitations under the License.
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore * When distributing Covered Code, include this CDDL HEADER in each
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore * If applicable, add the following below this CDDL HEADER, with the
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore * fields enclosed by brackets "[]" replaced with your own identifying
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore * information: Portions Copyright [yyyy] [name of copyright owner]
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore * CDDL HEADER END
9a5113a6958e1e7b93b09e74189ebc16d2a68affGarrett D'Amore * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore * Use is subject to license terms.
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore * The entire contents of this file are private the SD Host driver
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore * implementation.
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore * SD Host Spec says that a controller can support up to 6 different
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore * slots, each with its own register set.
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore * SD Host specific PCI configuration register.
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore#define SLOTINFO_NSLOT_MSK (0x3 << SLOTINFO_NSLOT_SHFT)
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore#define SLOTINFO_BAR_MSK (0x3 << SLOTINFO_BAR_SHFT)
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore ((((x) & SLOTINFO_NSLOT_MSK) >> SLOTINFO_NSLOT_SHFT) + 1)
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore (((x) & SLOTINFO_BAR_MSK) >> SLOTINFO_BAR_SHFT)
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore * Slot-specific CSRs
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore#define REG_POWER_CONTROL 0x0029 /* 8 bits */
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore#define REG_BLOCK_GAP_CONTROL 0x002A /* 8 bits */
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore#define REG_WAKEUP_CONTROL 0x002B /* 8 bits */
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore#define REG_CLOCK_CONTROL 0x002C /* 16 bits */
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore#define REG_TIMEOUT_CONTROL 0x002E /* 8 bits */
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore#define REG_ACMD12_ERROR 0x003C /* 16 bits */
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore#define REG_SLOT_INT_STAT 0x00FC /* 16 bits */
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore#define REG_ACMD12_ERROR_FORCE 0x0050 /* 16 bits */
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore/* REG_BLKSZ bits */
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore/* REG_XFR_MODE bits */
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore#define XFR_MODE_READ BIT(4) /* 1 = read, 0 = write */
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore#define XFR_MODE_MULTI BIT(5) /* 1 = multi, 0 = single */
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore/* REG_COMMAND bits */
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore#define COMMAND_RESP_48 2 /* R1, R3, R6, R7 */
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore/* REG_PRS bits */
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore (PRS_DAT0_SIG | PRS_DAT1_SIG | PRS_DAT2_SIG | PRS_DAT3_SIG)
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore/* REG_HOST_CONTROL bits */
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore/* REG_POWER_CONTROL bits */
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore/* REG_BLOCK_GAP_CONTROL bits */
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore/* REG_WAKEUP_CONTROL bits */
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore/* REG_CLOCK_CONTROL bits */
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore#define CLOCK_CONTROL_INT_CLOCK_STABLE BIT(1)
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore/* REG_TIMEOUT_CONTROL bits */
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore/* not listing them all here... but it goes on */
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore/* REG_SOFT_RESET bits */
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore/* REG_INT_{STAT,EN,MASK} bits */
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore#define INT_MASK (INT_XFR | INT_DMA | INT_PIO | INT_HOTPLUG)
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore/* REG_ERR_{STAT,EN,MASK} bits */
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore#define ERR_CMD (ERR_CMD_IDX | ERR_CMD_END | ERR_CMD_CRC | ERR_CMD_TMO)
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore#define ERR_CMD_CFL (ERR_CMD_CRC | ERR_CMD_TMO)
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore#define ERR_DAT (ERR_DAT_END | ERR_DAT_CRC | ERR_DAT_TMO)
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore/* REG_ACMD12_ERROR bits */
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore/* REG_CAPAB bits */
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore#define CAPAB_TIMEOUT_UNITS BIT(7) /* 1 == MHz, 0 = kHz */
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore#define CAPAB_VOLTS (CAPAB_33V | CAPAB_30V | CAPAB_18V)
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore/* REG_MAX_CURRENT bits */
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore/* REG_VERSION bits */
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore/* REG_ADMA_ERROR bits */
9a5113a6958e1e7b93b09e74189ebc16d2a68affGarrett D'Amore * Properties.
9a5113a6958e1e7b93b09e74189ebc16d2a68affGarrett D'Amore#define SDHOST_PROP_ENABLE_MSIX "enable-msix"
4bb7efa72ed531c10f097919636e67724ec4c25aGarrett D'Amore#endif /* _SYS_SDCARD_SDHOST_H */