ahci.c revision 2fcbc377041d659446ded306a92901b4b0753b68
/*
* CDDL HEADER START
*
* The contents of this file are subject to the terms of the
* Common Development and Distribution License (the "License").
* You may not use this file except in compliance with the License.
*
* You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
* See the License for the specific language governing permissions
* and limitations under the License.
*
* When distributing Covered Code, include this CDDL HEADER in each
* file and include the License file at usr/src/OPENSOLARIS.LICENSE.
* If applicable, add the following below this CDDL HEADER, with the
* fields enclosed by brackets "[]" replaced with your own identifying
* information: Portions Copyright [yyyy] [name of copyright owner]
*
* CDDL HEADER END
*/
/*
* Copyright 2006 Sun Microsystems, Inc. All rights reserved.
* Use is subject to license terms.
*/
#pragma ident "%Z%%M% %I% %E% SMI"
/*
* AHCI (Advanced Host Controller Interface) SATA HBA Driver
*/
/*
* Function prototypes for driver entry points
*/
/*
* Function prototypes for SATA Framework interfaces
*/
static int ahci_unregister_sata_hba_tran(ahci_ctl_t *);
#if defined(__lock_lint)
#endif
/*
* Local function prototypes
*/
static int ahci_initialize_controller(ahci_ctl_t *);
static void ahci_deallocate_controller(ahci_ctl_t *);
uint8_t, sata_pkt_t *);
int, sata_pkt_t *);
static void ahci_set_sense_data(sata_pkt_t *, int);
static int ahci_hba_reset(ahci_ctl_t *);
static int ahci_reset_hba_reject_pkts(ahci_ctl_t *);
uint8_t);
uint8_t, int);
static int ahci_recovery_fatal_error(ahci_ctl_t *,
static void ahci_watchdog_handler(ahci_ctl_t *);
static int ahci_add_legacy_intrs(ahci_ctl_t *);
static int ahci_add_msi_intrs(ahci_ctl_t *);
static void ahci_rem_intrs(ahci_ctl_t *);
static void ahci_enable_all_intrs(ahci_ctl_t *);
static void ahci_disable_all_intrs(ahci_ctl_t *);
uint8_t);
static int ahci_intr_device_mechanical_presence_status(ahci_ctl_t *,
ahci_port_t *, uint8_t);
static int ahci_intr_incorrect_port_multiplier(ahci_ctl_t *,
ahci_port_t *, uint8_t);
static int ahci_intr_interface_non_fatal_error(ahci_ctl_t *,
ahci_port_t *, uint8_t);
uint8_t);
uint8_t);
static int ahci_get_num_implemented_ports(uint32_t);
/*
* DMA attributes for the data buffer
*
* dma_attr_addr_hi will be changed to 0xffffffffull if the HBA
* does not support 64-bit addressing
*/
static ddi_dma_attr_t buffer_dma_attr = {
DMA_ATTR_V0, /* dma_attr_version */
0, /* dma_attr_addr_lo: lowest bus address */
0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */
0x3fffffull, /* dma_attr_count_max i.e. for one cookie */
2, /* dma_attr_align: word aligned */
1, /* dma_attr_burstsizes */
1, /* dma_attr_minxfer */
0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */
0xffffffffull, /* dma_attr_seg */
AHCI_PRDT_NUMBER, /* dma_attr_sgllen */
512, /* dma_attr_granular */
0, /* dma_attr_flags */
};
/*
* DMA attributes for the rcvd FIS
*
* dma_attr_addr_hi will be changed to 0xffffffffull if the HBA
* does not support 64-bit addressing
*/
static ddi_dma_attr_t rcvd_fis_dma_attr = {
DMA_ATTR_V0, /* dma_attr_version */
0, /* dma_attr_addr_lo: lowest bus address */
0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */
0xffffffffull, /* dma_attr_count_max i.e. for one cookie */
0x100, /* dma_attr_align: 256-byte aligned */
1, /* dma_attr_burstsizes */
1, /* dma_attr_minxfer */
0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */
0xffffffffull, /* dma_attr_seg */
1, /* dma_attr_sgllen */
1, /* dma_attr_granular */
0, /* dma_attr_flags */
};
/*
* DMA attributes for the command list
*
* dma_attr_addr_hi will be changed to 0xffffffffull if the HBA
* does not support 64-bit addressing
*/
static ddi_dma_attr_t cmd_list_dma_attr = {
DMA_ATTR_V0, /* dma_attr_version */
0, /* dma_attr_addr_lo: lowest bus address */
0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */
0xffffffffull, /* dma_attr_count_max i.e. for one cookie */
0x400, /* dma_attr_align: 1K-byte aligned */
1, /* dma_attr_burstsizes */
1, /* dma_attr_minxfer */
0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */
0xffffffffull, /* dma_attr_seg */
1, /* dma_attr_sgllen */
1, /* dma_attr_granular */
0, /* dma_attr_flags */
};
/*
* DMA attributes for cmd tables
*
* dma_attr_addr_hi will be changed to 0xffffffffull if the HBA
* does not support 64-bit addressing
*/
static ddi_dma_attr_t cmd_table_dma_attr = {
DMA_ATTR_V0, /* dma_attr_version */
0, /* dma_attr_addr_lo: lowest bus address */
0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */
0xffffffffull, /* dma_attr_count_max i.e. for one cookie */
0x80, /* dma_attr_align: 128-byte aligned */
1, /* dma_attr_burstsizes */
1, /* dma_attr_minxfer */
0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */
0xffffffffull, /* dma_attr_seg */
1, /* dma_attr_sgllen */
1, /* dma_attr_granular */
0, /* dma_attr_flags */
};
/* Device access attributes */
static ddi_device_acc_attr_t accattr = {
};
static struct dev_ops ahcictl_dev_ops = {
DEVO_REV, /* devo_rev */
0, /* refcnt */
ahci_getinfo, /* info */
nulldev, /* identify */
nulldev, /* probe */
ahci_attach, /* attach */
ahci_detach, /* detach */
nodev, /* no reset */
(struct cb_ops *)0, /* driver operations */
NULL, /* bus operations */
NULL /* power */
};
static sata_tran_hotplug_ops_t ahci_tran_hotplug_ops = {
};
extern struct mod_ops mod_driverops;
&mod_driverops, /* driverops */
"ahci driver %I%",
&ahcictl_dev_ops, /* driver ops */
};
static struct modlinkage modlinkage = {
&modldrv,
};
static int ahci_watchdog_tick;
/* The following is needed for ahci_log() */
static kmutex_t ahci_log_mutex;
static char ahci_log_buf[512];
static size_t ahci_cmd_table_size;
/* The number of Physical Region Descriptor Table(PRDT) in Command Table */
/*
* AHCI MSI tunable:
*
* MSI will be enabled in phase 2.
*/
#if AHCI_DEBUG
uint32_t ahci_debug_flags = 0;
#endif
/* Opaque state pointer initialized by ddi_soft_state_init() */
static void *ahci_statep = NULL;
/*
* ahci module initialization.
*/
int
_init(void)
{
int ret;
if (ret != 0) {
goto err_out;
}
goto err_out;
}
if (ret != 0) {
goto err_out;
}
/* watchdog tick */
return (ret);
return (ret);
}
/*
* ahci module uninitialize.
*/
int
_fini(void)
{
int ret;
if (ret != 0) {
return (ret);
}
/* Remove the resources allocated in _init(). */
return (ret);
}
/*
* _info entry point
*/
int
{
}
/*
* The attach entry point for dev_ops.
*/
static int
{
int status;
int attach_state;
int intr_types;
switch (cmd) {
case DDI_ATTACH:
break;
case DDI_RESUME:
/* It will be implemented in Phase 2 */
return (DDI_FAILURE);
default:
return (DDI_FAILURE);
}
/* Allocate soft state */
if (status != DDI_SUCCESS) {
goto err_out;
}
/*
* Now map the AHCI base address; which includes global
* registers and port control registers
*/
0,
0,
&accattr,
if (status != DDI_SUCCESS) {
goto err_out;
}
/* Get the AHCI version information */
(ahci_version & 0x000000ff)));
/* We don't support controllers whose versions are lower than 1.0 */
if (!(ahci_version & 0xffff0000)) {
"AHCI version 1.0");
goto err_out;
}
/* Get the HBA capabilities information */
/* Get the max number of ports supported by the HBA */
/* Get the number of command slots supported by the HBA */
((cap_status & AHCI_HBA_CAP_NCS) >>
AHCI_HBA_CAP_NCS_SHIFT) + 1;
/* Get the bit map which indicates ports implemented by the HBA */
/* Get the number of implemented ports by the HBA */
"hba number of implemented ports: 0x%x",
if (!(cap_status & AHCI_HBA_CAP_S64A)) {
"hba does not support 64-bit addressing");
0xffffffffull;
}
/*
* Modify dma_attr_align of ahcictl_buffer_dma_attr. For VT8251, those
* controllers with 0x00 revision id work on 4-byte aligned buffer,
* which is a bug and was fixed after 0x00 revision id controllers.
*/
!= DDI_SUCCESS) {
goto err_out;
}
"revision id = 0x%x", revision);
if (revision == 0x00) {
"change ddi_attr_align to 0x4");
}
}
/*
* Disable the whole controller interrupts before adding
* interrupt handlers(s).
*/
/* Get supported interrupt types */
"ddi_intr_get_supported_types failed");
goto err_out;
}
"ddi_intr_get_supported_types() returned: 0x%x",
/*
* Try MSI first, but fall back to FIXED if failed
*/
"Using MSI interrupt type");
goto intr_done;
}
"MSI registration failed, "
"trying FIXED interrupts");
}
if (intr_types & DDI_INTR_TYPE_FIXED) {
"Using FIXED interrupt type");
goto intr_done;
}
"FIXED interrupt registration failed");
}
goto err_out;
/* Initialize the controller mutex */
if (ahci_dma_prdt_number < AHCI_MIN_PRDT_NUMBER) {
} else if (ahci_dma_prdt_number > AHCI_MAX_PRDT_NUMBER) {
}
ahci_cmd_table_size = (sizeof (ahci_cmd_table_t) +
sizeof (ahci_prdt_item_t));
"ahci_attach: ahci_dma_prdt_number set by user is 0x%x,"
" ahci_cmd_table_size is 0x%x",
if (ahci_dma_prdt_number != AHCI_PRDT_NUMBER)
/*
* Initialize the controller and driver core.
*/
if (status != AHCI_SUCCESS) {
goto err_out;
}
/* Start one thread to check packet timeouts */
(void (*)(void *))ahci_watchdog_handler,
"ahci: setting sata hba tran failed");
goto err_out;
}
return (DDI_SUCCESS);
ahci_ctlp->ahcictl_timeout_id = 0;
}
if (attach_state & AHCI_ATTACH_STATE_HW_INIT) {
}
if (attach_state & AHCI_ATTACH_STATE_MUTEX_INIT) {
}
if (attach_state & AHCI_ATTACH_STATE_INTR_ADDED) {
}
if (attach_state & AHCI_ATTACH_STATE_REG_MAP) {
}
}
return (DDI_FAILURE);
}
/*
* The detach entry point for dev_ops.
*/
static int
{
int instance;
int ret;
switch (cmd) {
case DDI_DETACH:
/* disable the interrupts for an uninterrupted detach */
/* unregister from the sata framework. */
if (ret != AHCI_SUCCESS) {
return (DDI_FAILURE);
}
/* stop the watchdog handler */
ahci_ctlp->ahcictl_timeout_id = 0;
/* deallocate the controller structures */
/* destroy any mutexes */
/* remove the interrupts */
/* remove the reg maps. */
/* free the soft state. */
return (DDI_SUCCESS);
case DDI_SUSPEND:
/* It will be implemented in Phase 2 */
return (DDI_FAILURE);
default:
return (DDI_FAILURE);
}
}
/*
* The info entry point for dev_ops.
*
*/
static int
{
#ifndef __lock_lint
#endif /* __lock_lint */
int instance;
switch (infocmd) {
case DDI_INFO_DEVT2DEVINFO:
return (DDI_SUCCESS);
} else {
return (DDI_FAILURE);
}
case DDI_INFO_DEVT2INSTANCE:
break;
default:
break;
}
return (DDI_SUCCESS);
}
/*
* Registers the ahci with sata framework.
*/
static int
{
struct sata_hba_tran *sata_hba_tran;
"ahci_register_sata_hba_tran enter");
/* Allocate memory for the sata_hba_tran */
/* Report the number of implemented ports */
/* Get the data transfer capability for PIO command by the HBA */
if (cap_status & AHCI_HBA_CAP_PMD) {
"DRQ block data transfer for PIO command protocol");
} else {
"DRQ block data transfer for PIO command protocol");
}
/* Report the number of command slots */
#ifdef __lock_lint
#endif
/*
* When SATA framework adds support for pwrmgt the
* pwrmgt_ops needs to be updated
*/
/* Attach it to SATA framework */
!= DDI_SUCCESS) {
return (AHCI_FAILURE);
}
return (AHCI_SUCCESS);
}
/*
* Unregisters the ahci with sata framework.
*/
static int
{
"ahci_unregister_sata_hba_tran enter");
/* Detach from the SATA framework. */
DDI_SUCCESS) {
return (AHCI_FAILURE);
}
/* Deallocate sata_hba_tran. */
sizeof (sata_hba_tran_t));
return (AHCI_SUCCESS);
}
/*
* ahci_tran_probe_port is called by SATA framework. It returns port state,
* port status registers and an attached device type via sata_device
* structure.
*
* We return the cached information from a previous hardware probe. The
* actual hardware probing itself was done either from within
* ahci_initialize_controller() during the driver attach or from a phy
* ready change interrupt handler.
*/
static int
{
"ahci_tran_probe_port enter: cport: 0x%x, "
switch (port_state) {
case SATA_PSTATE_FAILED:
"ahci_tran_probe_port %d: PORT FAILED", port);
goto out;
case SATA_PSTATE_SHUTDOWN:
"ahci_tran_probe_port %d: PORT SHUTDOWN", port);
goto out;
case SATA_PSTATE_PWROFF:
"ahci_tran_probe_port %d: PORT PWROFF", port);
goto out;
case SATA_PSTATE_PWRON:
"ahci_tran_probe_port %d: PORT PWRON", port);
break;
default:
"ahci_tran_probe_port %d: PORT NORMAL %x",
port, port_state);
break;
}
switch (device_type) {
case SATA_DTYPE_ATADISK:
"ahci_tran_probe_port %d: DISK found", port);
break;
case SATA_DTYPE_ATAPICD:
"ahci_tran_probe_port %d: ATAPI found", port);
break;
case SATA_DTYPE_PMULT:
"ahci_tran_probe_port %d: Port Multiplier found",
port);
break;
case SATA_DTYPE_UNKNOWN:
"ahci_tran_probe_port %d: Unknown device found", port);
break;
default:
/* we don't support any other device types */
"ahci_tran_probe_port %d: No device found", port);
break;
}
out:
return (SATA_SUCCESS);
}
/*
* Called by sata framework to transport a sata packet down stream.
*/
static int
{
int slot;
"ahci_tran_start enter: cport %d satapkt 0x%p",
/*
* In case the targer driver would send the packet before
* sata framework can have the opportunity to process those
* event reports.
*/
&spkt->satapkt_device);
"ahci_tran_start returning PORT_ERROR while "
"cport: 0x%x", port);
return (SATA_TRAN_PORT_ERROR);
}
/*
* ahci_intr_phyrdy_change() may have rendered it to
* SATA_DTYPE_NONE.
*/
&spkt->satapkt_device);
"ahci_tran_start returning PORT_ERROR while "
"no device attached: cport: 0x%x", port);
return (SATA_TRAN_PORT_ERROR);
}
/*
* SATA HBA driver should remember that a device was reset and it
* is supposed to reject any packets which do not specify either
* SATA_IGNORE_DEV_RESET_STATE or SATA_CLEAR_DEV_RESET_STATE.
*
* This is to prevent a race condition when a device was arbitrarily
* reset by the HBA driver (and lost it's setting) and a target
* driver sending some commands to a device before the sata framework
* has a chance to restore the device setting (such as cache enable/
* disable or other resettable stuff).
*/
"ahci_tran_start clearing the "
"reset_in_progress for port: 0x%x", port);
}
if (ahci_portp->ahciport_reset_in_progress &&
! ddi_in_panic()) {
"ahci_tran_start returning BUSY while "
"reset in progress: cport: 0x%x", port);
return (SATA_TRAN_BUSY);
}
"ahci_tran_start returning BUSY while "
"mopping in progress: port: 0x%x", port);
return (SATA_TRAN_BUSY);
}
== AHCI_FAILURE) {
"returning QUEUE_FULL: port %d", port);
return (SATA_TRAN_QUEUE_FULL);
}
if (spkt->satapkt_op_mode &
/* we need to poll now */
}
"sata tran accepted: port %d", port);
return (SATA_TRAN_ACCEPTED);
}
if (satapkt) { \
/* \
* We set the satapkt_reason in both sync and \
* non-sync cases. \
*/ \
} \
if (satapkt && \
satapkt->satapkt_comp) { \
}
/*
* Searches for and claims a free slot.
*
* Returns: AHCI_FAILURE if no slots found
* claimed slot number if successful
*
* WARNING!!! ahciport_mutex should be acquired before the function
* is called.
*/
/*ARGSUSED*/
static int
{
int slot;
"ahciport_pending_tags = 0x%x",
if (slot == -1) {
"ahci_claim_free_slot: no empty slots");
return (AHCI_FAILURE);
}
"ahci_claim_free_slot: found slot: 0x%x", slot);
return (slot);
}
/*
* Builds the Command Table for the sata packet and delivers it to controller.
*
* Returns:
* slot number if we can obtain a slot successfully
* otherwise, return AHCI_FAILURE
*
* WARNING!!! ahciport_mutex should be acquired before the function is called.
*/
static int
{
int slot;
int ncookies;
int i;
/* Check if there is an empty command slot */
if (slot == AHCI_FAILURE) {
return (AHCI_FAILURE);
}
"ahci_deliver_satapkt enter: cmd_reg: 0x%x, slot: 0x%x, "
/* For data transfer operations, this is the H2D Register FIS */
}
switch (cmd->satacmd_addr_type) {
case ATA_ADDR_LBA:
/* fallthrough */
case ATA_ADDR_LBA28:
/* LBA[7:0] */
/* LBA[15:8] */
/* LBA[23:16] */
/* LBA [27:24] (also called dev_head) */
break;
case ATA_ADDR_LBA48:
/* LBA[7:0] */
/* LBA[15:8] */
/* LBA[23:16] */
/* LBA [31:24] */
/* LBA [39:32] */
/* LBA [47:40] */
/* Set dev_head */
/* Set the extended sector count and features */
break;
}
"ncookies = 0x%x, ahci_dma_prdt_number = 0x%x",
/* *** now fill the scatter gather list ******* */
for (i = 0; i < ncookies; i++) {
}
/* Set Command Header in Command List */
"sata_data_direction = 0x%x",
/* Now remember the sata packet in ahciport_slot_pkts[]. */
/*
* We are overloading satapkt_hba_driver_private with
* watched_cycle count.
*/
/* *** finished filling the scatter gather list , sync******* */
0,
slot * sizeof (ahci_cmd_header_t),
sizeof (ahci_cmd_header_t),
/* Indicate to the HBA that a command is active. */
(0x1 << slot));
"exit: port %d", port);
return (slot);
}
/*
* Polls for the completion of the command. This is safe with both
* interrupts enabled or disabled.
*/
static void
{
int pkt_timeout_ticks;
int in_panic = ddi_in_panic();
"ahci_poll_cmd entered, port: %x", port);
/* we start out with SATA_PKT_COMPLETED as the satapkt_reason */
/*
* The interrupt handler will return directly for poll commands in case
* the interrupt has been generated before interrupts were disabled.
*/
do {
if (in_panic) {
/*
* If we are in panic, we can't rely on
* timers; so, busy wait instead of delay().
*/
} else {
#ifndef __lock_lint
#endif /* __lock_lint */
}
} else {
break;
}
} while (pkt_timeout_ticks > 0);
goto poll_done;
}
}
}
/*
* Called by the sata framework to abort the previously sent packet(s).
*
* Reset device to abort commands.
*/
static int
{
int tmp_slot;
"ahci_tran_abort on cport %d", cport);
/*
* To prevent recursive enter to ahci_mop_commands, we need
* check AHCI_PORT_STATE_MOPPING flag.
*/
"ahci_tran_abort: port %d is in "
"mopping process, so just return directly ", port);
return (SATA_SUCCESS);
}
/*
* In case the targer driver would send the request before
* sata framework can have the opportunity to process those
* event reports.
*/
&spkt->satapkt_device);
"ahci_tran_abort returning SATA_FAILURE while "
"cport: 0x%x", port);
return (SATA_FAILURE);
}
/*
* ahci_intr_phyrdy_change() may have rendered it to
* AHCI_PORT_TYPE_NODEV.
*/
&spkt->satapkt_device);
"ahci_tran_abort returning SATA_FAILURE while "
"no device attached: cport: 0x%x", port);
return (SATA_FAILURE);
}
if (flag == SATA_ABORT_ALL_PACKETS) {
} else {
aborted_tags = 0xffffffff;
/*
* Aborting one specific packet, first search our
* ahciport_slot_pkts[] list for matching spkt.
*/
for (tmp_slot = 0;
break;
}
}
if (aborted_tags == 0xffffffff) {
/* request packet is not on the pending list */
"Cannot find the aborting pkt 0x%p on the "
"pending list", (void *)spkt);
&spkt->satapkt_device);
return (SATA_FAILURE);
}
}
/*
* To abort the packet(s), first we are trying to clear PxCMD.ST
* and PxCMD.FRE to stop the port, and if the port can be stopped
* successfully with PxTFD.STS.BSY and PxTFD.STS.DRQ cleared to '0',
* then we just send back the aborted packet(s) with ABORTED flag
* and then restart the port by setting PxCMD.ST and PxCMD.FRE.
* If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then we
* perform a COMRESET.
*/
/*
* Compute which have finished and which need to be retried.
*
* The finished tags are ahciport_pending_tags minus the slot_status.
* The aborted_tags have to be reduced by finished_tags since we
* can't possibly abort a tag which had finished already.
*/
port,
0, /* failed tags */
0, /* timeout tags */
0); /* reset tags */
return (SATA_SUCCESS);
}
/*
* Used to do device reset and reject all the pending packets on a device
* during the reset operation.
*
* WARNING!!! ahciport_mutex should be acquired before the function is called.
*/
static int
{
int ret;
"ahci_reset_device_reject_pkts on port: %d", port);
/*
* To prevent recursive enter to ahci_mop_commands, we need
* check AHCI_PORT_STATE_MOPPING flag.
*/
"ahci_reset_device_reject_pkts: port %d is in "
"mopping process, so return directly ", port);
return (SATA_SUCCESS);
}
!= AHCI_SUCCESS) {
"Try to do a port reset after software "
"reset failed", port);
if (ret != AHCI_SUCCESS) {
"ahci_reset_device_reject_pkts: port %d "
"failed", port);
return (SATA_FAILURE);
}
}
/* Set the reset in progress flag */
/* Indicate to the framework that a reset has happened */
} else {
}
&sdevice,
"port %d sending event up: SATA_EVNT_RESET", port);
/* Next try to mop the pending commands */
reset_tags &= ~finished_tags;
port,
0, /* failed tags */
0, /* timeout tags */
0, /* aborted tags */
reset_tags); /* reset tags */
return (SATA_SUCCESS);
}
/*
* Used to do port reset and reject all the pending packets on a port during
* the reset operation.
*
* WARNING!!! ahciport_mutex should be acquired before the function is called.
*/
static int
{
"ahci_reset_port_reject_pkts on port: %d", port);
/*
* To prevent recursive enter to ahci_mop_commands, we need
* check AHCI_PORT_STATE_MOPPING flag.
*/
"ahci_reset_port_reject_pkts: port %d is in "
"mopping process, so return directly ", port);
return (SATA_SUCCESS);
}
return (SATA_FAILURE);
reset_tags &= ~finished_tags;
port,
0, /* failed tags */
0, /* timeout tags */
0, /* aborted tags */
reset_tags); /* reset tags */
return (SATA_SUCCESS);
}
/*
* Used to do hba reset and reject all the pending packets on all ports
* during the reset operation.
*/
static int
{
int ret = SATA_SUCCESS;
"ahci_reset_hba_reject_pkts enter");
continue;
}
}
ret = SATA_FAILURE;
goto out;
}
continue;
}
/*
* To prevent recursive enter to ahci_mop_commands, we need
* check AHCI_PORT_STATE_MOPPING flag.
*/
"ahci_reset_hba_reject_pkts: port %d is in "
"mopping process, so return directly ", port);
continue;
}
/* Indicate to the framework that a reset has happened */
} else {
}
"port %d sending event up: SATA_EVNT_RESET",
port);
port,
0, /* failed tags */
0, /* timeout tags */
0, /* aborted tags */
}
out:
return (ret);
}
/*
* Called by sata framework to reset a port(s) or device.
*/
static int
{
int ret = SATA_SUCCESS;
"ahci_tran_reset_port enter: cport: 0x%x", cport);
case SATA_ADDR_CPORT:
/* Port reset */
break;
case SATA_ADDR_DCPORT:
/* Device reset */
/*
* In case the targer driver would send the request
* before sata framework can have the opportunity to
* process those event reports.
*/
"ahci_tran_reset_dport returning SATA_FAILURE "
"cport: 0x%x", port);
ret = SATA_FAILURE;
break;
}
/*
* ahci_intr_phyrdy_change() may have rendered it to
* AHCI_PORT_TYPE_NODEV.
*/
"ahci_tran_reset_dport returning SATA_FAILURE "
"while no device attached: cport: 0x%x", port);
ret = SATA_FAILURE;
break;
}
ahci_portp, port);
break;
case SATA_ADDR_CNTRL:
/* Reset the whole controller */
break;
case SATA_ADDR_PMPORT:
case SATA_ADDR_DPMPORT:
"port multiplier will be supported later");
/* FALLSTHROUGH */
default:
ret = SATA_FAILURE;
}
return (ret);
}
/*
* Called by sata framework to activate a port as part of hotplug.
* (cfgadm -c connect satax/y)
* Note: Not port-mult aware.
*/
static int
{
"ahci_tran_hotplug_port_activate cport %d enter", cport);
/* Enable the interrupts on the port. */
/*
* Reset the port so that the PHY communication would be re-established.
* But this reset is an internal operation; the sata framework does
* not need to know about it.
*/
/*
* Need to check the link status and device status of the port
* and consider raising power if the port was in D3 state
*/
return (SATA_SUCCESS);
}
/*
* Called by sata framework to deactivate a port as part of hotplug.
* (cfgadm -c disconnect satax/y)
* Note: Not port-mult aware.
*/
static int
{
"ahci_tran_hotplug_port_deactivate cport %d enter", cport);
/* Disable the interrupts on the port. */
/* First to abort all the pending commands */
/* Then shut down the port */
ahci_portp, port);
/* Update ahciport_port_state */
return (SATA_SUCCESS);
}
/*
* To be used to mark all the pending pkts with ABORTED
* when a device is unplugged or a port is deactivated.
*
* WARNING!!! ahciport_mutex should be acquired before the function is called.
*/
static void
{
"ahci_reject_all_abort_pkts on port: %d", port);
/*
* To prevent recursive enter to ahci_mop_commands, we need
* check AHCI_PORT_STATE_MOPPING flag.
*/
"ahci_reject_all_abort_pkts: port %d is in "
"mopping process, so return directly ", port);
return;
}
port,
0, /* failed tags */
0, /* timeout tags */
abort_tags, /* aborting tags */
0); /* reset tags */
}
#if defined(__lock_lint)
static int
{
return (SATA_SUCCESS);
}
#endif
/*
* Initialize the controller and set up driver data structures.
*
* This routine can be called from three seperate cases: DDI_ATTACH,
* PM_LEVEL_D0 and DDI_RESUME. The DDI_ATTACH case is different from
* other two cases; the memory allocation and device signature probing
* are attempted only during DDI_ATTACH case.
*
* WARNING!!! Disable the whole controller's interrupts before calling and
* the interrupts will be enabled upon successfully return.
*/
static int
{
"ahci_initialize_controller enter");
/*
* Indicate that system software is AHCI aware by setting
* GHC.AE to 1
*/
/* Initialize the implemented ports and structures */
"hba port %d not implemented", port);
continue;
}
/* only allocate port during attach */
#ifndef __lock_lint
#endif /* __lock_lint */
AHCI_SUCCESS) {
goto err_out;
}
}
/*
* Ensure that the controller is not in the running state
* by checking every implemented port's PxCMD register
*/
!= AHCI_SUCCESS) {
"ahci_initialize_controller: failed to "
"initialize port %d", port);
/*
* Set the port state to SATA_PSTATE_FAILED if
* failed to initialize it.
*/
}
}
/* Enable the whole controller interrupts */
return (AHCI_SUCCESS);
}
}
return (AHCI_FAILURE);
}
/*
* Reverse of ahci_initialize_controller(), only need to de-allocate
* all ports' state structures for AHCI_DETACH case.
*
* WARNING!!! ahcictl_mutex should be acquired before the function is called.
*/
static void
{
"ahci_deallocate_controller enter");
/* disable all the interrupts. */
/* if this port is implemented by the HBA */
}
}
}
/*
* The routine is to initialize the port. First put the port in NOTRunning
* state, then enable port interrupt and clear Serror register. And under
* AHCI_ATTACH case, find device signature and then try to start the port.
*
* WARNING!!! ahcictl_mutex and ahciport_mutex should be acquired before
* the function is called.
*/
static int
{
"ahci_initialize_port: port %d "
/*
* Check whether the port is in NotRunning state, if not,
* put the port in NotRunning state
*/
if (!(port_cmd_status &
AHCI_CMD_STATUS_FR))) {
goto done_out;
}
return (AHCI_FAILURE);
"port %d is in NotRunning state", port);
/* Enable port interrupts */
/*
* devices during attach.
*/
return (AHCI_FAILURE);
}
/* Try to start the port */
== SATA_DTYPE_ATADISK) &&
!= AHCI_SUCCESS)) {
return (AHCI_FAILURE);
}
}
return (AHCI_SUCCESS);
}
/*
* AHCI device reset ...; a single device on one of the ports is reset,
* but the HBA and physical communication remain intact. This is the
* least intrusive.
*
* When issuing a software reset sequence, there should not be other
* commands in the command list, so we will first clear and then re-set
* PxCMD.ST to clear PxCI. And before issuing the software reset,
* the port must be idle and PxTFD.STS.BSY and PxTFD.STS.DRQ must be
* cleared.
*
* WARNING!!! ahciport_mutex should be acquired and PxCMD.FRE should be
* set before the function is called.
*/
static int
{
int slot, loop_count;
"Port %d device resetting", port);
/* First to clear PxCMD.ST */
/* And then to re-set PxCMD.ST */
/* Check PxTFD.STS.BSY and PxTFD.STS.DRQ */
if (port_task_file & AHCI_TFD_STS_BSY ||
if (!(port_cmd_status & AHCI_CMD_STATUS_CLO)) {
"PxTFD.STS.BSY or PxTFD.STS.DRQ is still set, "
"but PxCMD.CLO isn't supported, so a port "
"reset is needed.");
return (AHCI_FAILURE);
}
}
if (slot == AHCI_FAILURE) {
"ahci_software_reset: no free slot");
return (AHCI_FAILURE);
}
/* Now send the first R2H FIS with SRST set to 1 */
/* Set Command Header in Command List */
0,
slot * sizeof (ahci_cmd_header_t),
sizeof (ahci_cmd_header_t),
/* Indicate to the HBA that a command is active. */
(0x1 << slot));
loop_count = 0;
/* Loop till the first command is finished */
do {
if (loop_count++ > AHCI_POLLRATE_PORT_SOFTRESET) {
/* We are effectively timing out after 0.1 sec. */
break;
}
/* Wait for 10 millisec */
#ifndef __lock_lint
#endif /* __lock_lint */
"ahci_software_reset: 1st loop count: %d, "
"port_cmd_issue = 0x%x, slot = 0x%x",
/* Now send the second R2H FIS with SRST cleard to zero */
/* Set Command Header in Command List */
0,
slot * sizeof (ahci_cmd_header_t),
sizeof (ahci_cmd_header_t),
/* Indicate to the HBA that a command is active. */
(0x1 << slot));
loop_count = 0;
/* Loop till the second command is finished */
do {
if (loop_count++ > AHCI_POLLRATE_PORT_SOFTRESET) {
/* We are effectively timing out after 0.1 sec. */
break;
}
/* Wait for 10 millisec */
#ifndef __lock_lint
#endif /* __lock_lint */
"ahci_software_reset: 2nd loop count: %d, "
"port_cmd_issue = 0x%x, slot = 0x%x",
return (AHCI_SUCCESS);
}
/*
* AHCI port reset ...; the physical communication between the HBA and device
* on a port are disabled. This is more intrusive.
*
* When an HBA or port reset occurs, Phy communication shall
* be re-established with the device through a COMRESET followed by the
* normal out-of-band communication sequence defined in Serial ATA. AT
* the end of reset, the device, if working properly, will send a D2H
* Register FIS, which contains the device signature. When the HBA receives
* this FIS, it updates PxTFD.STS and PxTFD.ERR register fields, and updates
* the PxSIG register with the signature.
*
* Staggered spin-up is an optional feature in SATA II, and it enables an HBA
* to individually spin-up attached devices. Please refer to chapter 10.9 of
* AHCI 1.1 spec.
*/
/*
* WARNING!!! ahciport_mutex should be acquired, intr should be disabled,
* and PxCMD.ST and PxCMD.FRE should be also cleared before the function
* is called.
*/
static int
{
int loop_count;
"Port %d port resetting...", port);
if (cap_status & AHCI_HBA_CAP_SSS) {
/*
* HBA support staggered spin-up, if the port has
* not spin up yet, then force it to do spin-up
*/
if (!(port_cmd_status & AHCI_CMD_STATUS_SUD)) {
if (!(ahci_portp->ahciport_flags
& AHCI_PORT_STATE_SPINUP)) {
"Port %d PxCMD.SUD is zero, force "
"it to do spin-up", port);
}
}
} else {
/*
* HBA doesn't support stagger spin-up, force it
* to do normal COMRESET
*/
if (ahci_portp->ahciport_flags &
"HBA does not support staggered spin-up "
"force it to do normal COMRESET");
}
}
/* Do normal COMRESET */
"ahci_port_reset: do normal COMRESET", port);
/* Enable PxCMD.FRE to read device */
/* give time for COMRESET to percolate */
#ifndef __lock_lint
#endif /* __lock_lint */
/* Fetch the SCONTROL again and rewrite the DET part with 0 */
} else {
/* Do staggered spin-up */
/* PxSCTL.DET must be 0 */
/* 0 -> 1 edge */
#ifndef __lock_lint
#endif /* __lock_lint */
/* Set PxCMD.SUD to 1 */
/* Enable PxCMD.FRE to read device */
}
/*
* After PxSCTL.DET is set to 0h, software should wait for
* communication to be re-established as indicated by bit 0
* of PxSSTS.DET being set to '1'.
*/
loop_count = 0;
do {
if (port_intr_status & AHCI_INTR_STATUS_PCS) {
"COMINIT signal is received", port);
/*
* Clear PxSERR.DIAG.X to update PxTFD by the D2H FIS
* received by HBA
*/
}
if (loop_count++ > AHCI_POLLRATE_PORT_COMRESET) {
/*
* We are effectively timing out after 0.1 sec.
*/
break;
}
/* Wait for 10 millisec */
#ifndef __lock_lint
#endif /* __lock_lint */
} while (!(port_intr_status & AHCI_INTR_STATUS_PCS));
"ahci_port_reset: 1st loop count: %d, "
/*
* The DET field is valid only if IPM field indicates
* that the interface is in active state.
*/
loop_count = 0;
do {
if (AHCI_SSTATUS_GET_IPM(port_sstatus) !=
/*
* If the interface is not active, the DET field
* is considered not accurate. So we want to
* continue looping.
*/
}
if (loop_count++ > AHCI_POLLRATE_PORT_SSTATUS) {
/*
* We are effectively timing out after 0.1 sec.
*/
break;
}
/* Wait for 10 millisec */
#ifndef __lock_lint
#endif /* __lock_lint */
} while (AHCI_SSTATUS_GET_DET(port_sstatus) !=
"ahci_port_reset: 2nd loop count: %d, "
if ((AHCI_SSTATUS_GET_IPM(port_sstatus) !=
/*
* Either the port is not active or there
* is no device present.
*/
ahci_portp, port);
}
if (AHCI_SSTATUS_GET_DET(port_sstatus) ==
/*
* If device exist, then first check PxTFD.STS.BSY
*/
loop_count = 0;
do {
if (loop_count++ > AHCI_POLLRATE_PORT_TFD_BSY) {
/*
* We are effectively timing out after 11 sec.
*/
break;
}
if (port_intr_status & AHCI_INTR_STATUS_PCS) {
/*
* Clear PxSERR.DIAG.X to update PxTFD by
* the D2H FIS received by HBA.
*/
}
/* Wait for 10 millisec */
#ifndef __lock_lint
#endif /* __lock_lint */
} while (port_task_file & AHCI_TFD_STS_BSY);
"ahci_port_reset: 3rd loop count: %d, "
"port_task_file = 0x%x",
/*
* Next check COMRESET is completed successfully
*/
loop_count = 0;
do {
if (((port_task_file & AHCI_TFD_ERR_MASK)
>> AHCI_TFD_ERR_SHIFT) == 0x1) {
"COMRESET success, D2H register FIS "
"post to received FIS structure");
break;
}
if (loop_count++ > AHCI_POLLRATE_PORT_TFD_ERROR) {
/*
* We are effectively timing out after 0.1 sec.
*/
break;
}
/* Wait for 10 millisec */
#ifndef __lock_lint
#endif /* __lock_lint */
} while (((port_task_file & AHCI_TFD_ERR_MASK)
>> AHCI_TFD_ERR_SHIFT) != 0x1);
"ahci_port_reset: 4th loop count: %d, "
"port_task_file = 0x%x",
/*
* Check device status, if keep busy or COMRESET error
* do device reset to patch some SATA disks' issue
*
* For VT8251, sometimes need to do the device reset
*/
if (port_task_file & AHCI_TFD_STS_BSY) {
"need to do device reset", port);
!= AHCI_SUCCESS) {
"port %d device reset failed", port);
return (AHCI_FAILURE);
}
if (port_task_file & AHCI_TFD_STS_BSY) {
"port %d keep busy after device reset "
"port_task_file = 0x%x",
return (AHCI_FAILURE);
}
}
}
/* Clear port serror register for each implemented port. */
return (AHCI_SUCCESS);
}
/*
* AHCI HBA reset ...; the entire HBA is reset, and all ports are disabled.
* This is the most intrusive.
*
* When an HBA reset occurs, Phy communication shall
* be re-established with the device through a COMRESET followed by the
* normal out-of-band communication sequence defined in Serial ATA. AT
* the end of reset, the device, if working properly, will send a D2H
* Register FIS, which contains the device signature. When the HBA receives
* this FIS, it updates PxTFD.STS and PxTFD.ERR register fields, and updates
* the PxSIG register with the signature.
*
* Remember to set GHC.AE to 1 before calling ahci_hba_reset.
*
* WARNING!!! ahcictl_mutex should be already held before the function
* is called.
*/
static int
{
int loop_count;
int rval = AHCI_SUCCESS;
/* Setting GHC.HR to 1, remember GHC.AE is already set to 1 before */
/*
* Wait until HBA Reset complete or timeout
*/
loop_count = 0;
do {
if (loop_count++ > AHCI_POLLRATE_HBA_RESET) {
"ahci hba reset is timing out, "
"ghc_control = 0x%x", ghc_control);
/* We are effectively timing out after 1 sec. */
break;
}
/* Wait for 10 millisec */
#ifndef __lock_lint
#endif /* __lock_lint */
} while (ghc_control & AHCI_HBA_GHC_HR);
"ahci_hba_reset: 1st loop count: %d, "
if (ghc_control & AHCI_HBA_GHC_HR) {
/* The hba is not reset for some reasons */
"hba reset failed: HBA in a hung or locked state");
return (AHCI_FAILURE);
}
/* Only check implemented ports */
continue;
}
!= AHCI_SUCCESS) {
rval = AHCI_FAILURE;
"ahci_hba_reset: port %d failed", port);
}
}
/*
* Indicate that system software is AHCI aware by setting
* GHC.AE to 1
*/
return (rval);
}
/*
* This routine is only called from AHCI_ATTACH or phyrdy change
* case. It first calls port reset to initialize port, probe port and probe
* device, then read PxSIG register to find the type of device attached to
* the port.
*
* WARNING!!! ahciport_mutex should be acquired before the function
* is called.
*/
static int
{
int ret = AHCI_SUCCESS;
"port %d: ahci_find_dev_signature enter", port);
/* Call port reset to check link status and get device signature */
"ahci_find_dev_signature failed for port %d: ", port);
return (AHCI_FAILURE);
}
switch (signature) {
case AHCI_SIGNATURE_DISK:
"Disk is found at port: %d", port);
break;
case AHCI_SIGNATURE_ATAPI:
"ATAPI device is found at port: %d", port);
break;
"Port Multiplier is found at port: %d", port);
break;
case AHCI_SIGNATURE_NONE:
"No device is found at port: %d", port);
break;
default:
"Unknown device is found at port: %d", port);
}
return (ret);
}
/*
* Try to start the port - set PxCMD.ST to 1, if PxCMD.FRE is not set
* to 1, then set it.
*
* WARNING!!! ahciport_mutex should be acquired before the function
* is called.
*/
static int
{
"ahci_start_port: %d enter", port);
if (port_task_file & AHCI_TFD_STS_BSY ||
"Port %d cannot start!!! port_task_file = 0x%x",
return (AHCI_FAILURE);
} else {
"Port %d start!!! port_task_file = 0x%x",
/* First to set PxCMD.FRE before setting PxCMD.ST. */
if (!(port_cmd_status & AHCI_CMD_STATUS_FRE)) {
}
return (AHCI_SUCCESS);
}
}
/*
* Allocate the ahci_port_t including Received FIS and Command List.
* The argument - port is the physical port number, and not logical
* port number seen by the SATA framework.
*
* WARNING!!! ahcictl_mutex should be acquired before the function
* is called.
*/
static int
{
#ifndef __lock_lint
#endif /* __lock_lint */
/*
* Allocate memory for received FIS structure and
* command list for this port
*/
goto err_case1;
}
goto err_case2;
}
return (AHCI_SUCCESS);
return (AHCI_FAILURE);
}
/*
* Reverse of ahci_dealloc_port_state().
*
* WARNING!!! ahcictl_mutex should be acquired before the function
* is called.
*/
static void
{
#ifndef __lock_lint
#endif /* __lock_lint */
}
/*
* Allocates memory for the Received FIS Structure
*
* WARNING!!! ahciport_mutex should be acquired before the function
* is called.
*/
static int
{
rcvd_fis_size = sizeof (ahci_rcvd_fis_t);
/* Check whether the HBA can access 64-bit data structures */
/*
* If 64-bit addressing is not supported,
* change dma_attr_addr_hi of ahcictl_rcvd_fis_dma_attr
*/
if (!(cap_status & AHCI_HBA_CAP_S64A)) {
"hba does not support 64-bit addressing");
0xffffffffull;
}
/* allocate rcvd FIS dma handle. */
NULL,
DDI_SUCCESS) {
"rcvd FIS dma handle alloc failed");
return (AHCI_FAILURE);
}
&accattr,
NULL,
&ret_len,
"rcvd FIS dma mem alloc fail");
/* error.. free the dma handle. */
return (AHCI_FAILURE);
}
NULL,
NULL,
&cookie_count) != DDI_DMA_MAPPED) {
"rcvd FIS dma handle bind fail");
/* error.. free the dma handle & free the memory. */
return (AHCI_FAILURE);
}
/* Config Port Received FIS Base Address */
return (AHCI_SUCCESS);
}
/*
* Deallocates the Received FIS Structure
*
* WARNING!!! ahciport_mutex should be acquired before the function
* is called.
*/
static void
{
"ahci_dealloc_rcvd_fis: port %d enter",
/* Unbind the cmd list dma handle first. */
/* Then free the underlying memory. */
/* Now free the handle itself. */
}
/*
* Allocates memory for the Command List, which contains up to 32 entries.
* Each entry contains a command header, which is a 32-byte structure that
* includes the pointer to the command table.
*
* WARNING!!! ahciport_mutex should be acquired before the function
* is called.
*/
static int
{
/*
* If 64-bit addressing is not supported,
* change dma_attr_addr_hi of ahcictl_cmd_list_dma_attr
*/
if (!(cap_status & AHCI_HBA_CAP_S64A)) {
"hba does not support 64-bit addressing");
0xffffffffull;
}
/* allocate cmd list dma handle. */
NULL,
"cmd list dma handle alloc failed");
return (AHCI_FAILURE);
}
&accattr,
NULL,
&ret_len,
"cmd list dma mem alloc fail");
/* error.. free the dma handle. */
return (AHCI_FAILURE);
}
NULL,
NULL,
&cookie_count) != DDI_DMA_MAPPED) {
"cmd list dma handle bind fail");
/* error.. free the dma handle & free the memory. */
return (AHCI_FAILURE);
}
/* Config Port Command List Base Address */
return (AHCI_FAILURE);
}
return (AHCI_SUCCESS);
}
/*
* Deallocates the Command List
*
* WARNING!!! ahciport_mutex should be acquired before the function
* is called.
*/
static void
{
/* First dealloc command table */
/* Unbind the cmd list dma handle first. */
/* Then free the underlying memory. */
/* Now free the handle itself. */
}
/*
* Allocates memory for all Command Tables, which contains Command FIS,
* ATAPI Command and Physical Region Descriptor Table.
*
* WARNING!!! ahciport_mutex should be acquired before the function
* is called.
*/
static int
{
int slot;
"ahci_alloc_cmd_tables: port %d enter",
/* Check whether the HBA can access 64-bit data structures */
/*
* If 64-bit addressing is not supported,
* change dma_attr_addr_hi of ahcictl_cmd_table_dma_attr
*/
if (!(cap_status & AHCI_HBA_CAP_S64A)) {
"hba does not support 64-bit addressing");
0xffffffffull;
}
/* Allocate cmd table dma handle. */
NULL,
DDI_SUCCESS) {
"cmd table dma handle alloc failed");
goto err_out;
}
if (ddi_dma_mem_alloc(
&accattr,
NULL,
&ret_len,
NULL) {
"cmd table dma mem alloc fail");
/* error.. free the dma handle. */
goto err_out;
}
NULL,
NULL,
&cookie_count) != DDI_DMA_MAPPED) {
"cmd table dma handle bind fail");
/* error.. free the dma handle & free the memory. */
goto err_out;
}
/* Config Port Command Table Base Address */
#ifndef __lock_lint
#endif /* __lock_lint */
}
return (AHCI_SUCCESS);
/* Unbind the cmd table dma handle first */
(void) ddi_dma_unbind_handle(
/* Then free the underlying memory */
/* Now free the handle itself */
}
return (AHCI_FAILURE);
}
/*
* Deallocates memory for all Command Tables.
*
* WARNING!!! ahciport_mutex should be acquired before the function
* is called.
*/
static void
{
int slot;
"ahci_dealloc_cmd_tables: %d enter",
/* Unbind the cmd table dma handle first. */
(void) ddi_dma_unbind_handle(
/* Then free the underlying memory. */
/* Now free the handle itself. */
}
}
/*
* WARNING!!! ahciport_mutex should be acquired before the function
* is called.
*/
static void
{
}
/*
* Set the auto sense data for ATAPI devices.
*
* Note: Currently the sense data is simulated; this code will be enhanced
* in second phase to fetch the real sense data from the atapi device.
*/
static void
{
struct scsi_extended_sense *sense;
sense = (struct scsi_extended_sense *)
sense->es_cmd_info[0] = 0;
sense->es_add_code = 0;
sense->es_qual_code = 0;
}
}
/*
* Interrupt service handler
*/
/* ARGSUSED1 */
static uint_t
{
/*
* global_intr_status indicates that the corresponding port has
* an interrupt pending.
*/
"ahci_intr enter: global_intr_status = 0x%x", global_intr_status);
/* The interrupt is not ours */
return (DDI_INTR_UNCLAIMED);
}
/* Loop for all the ports */
continue;
}
continue;
}
/*
* port_intr_stats indicates that the corresponding interrupt
* condition is active.
*/
/*
* port_intr_enable indicates that the corresponding interrrupt
* reporting is enabled.
*/
"ahci_intr: port %d, port_intr_status = 0x%x, "
"port_intr_enable = 0x%x", port,
/* First clear the port interrupts status */
if (port_intr_status & AHCI_INTR_STATUS_DHRS) {
port);
}
if (port_intr_status & AHCI_INTR_STATUS_PSS) {
port);
}
if (port_intr_status & AHCI_INTR_STATUS_DSS) {
port);
}
if (port_intr_status & AHCI_INTR_STATUS_SDBS) {
ahci_portp, port);
}
if (port_intr_status & AHCI_INTR_STATUS_UFS) {
port);
}
if (port_intr_status & AHCI_INTR_STATUS_DPS) {
ahci_portp, port);
}
if (port_intr_status & AHCI_INTR_STATUS_PCS) {
ahci_portp, port);
}
if (port_intr_status & AHCI_INTR_STATUS_DMPS) {
}
if (port_intr_status & AHCI_INTR_STATUS_PRCS) {
port);
}
if (port_intr_status & AHCI_INTR_STATUS_IPMS) {
ahci_portp, port);
}
if (port_intr_status & AHCI_INTR_STATUS_OFS) {
}
if (port_intr_status & AHCI_INTR_STATUS_INFS) {
ahci_portp, port);
}
if (port_intr_status & AHCI_INTR_STATUS_IFS) {
ahci_portp, port);
}
if (port_intr_status & AHCI_INTR_STATUS_HBDS) {
ahci_portp, port);
}
if (port_intr_status & AHCI_INTR_STATUS_HBFS) {
ahci_portp, port);
}
if (port_intr_status & AHCI_INTR_STATUS_TFES) {
port);
}
if (port_intr_status & AHCI_INTR_STATUS_CPDS) {
(void) ahci_intr_cold_port_detect(ahci_ctlp,
ahci_portp, port);
}
/* Second clear the corresponding bit in IS.IPS */
}
return (DDI_INTR_CLAIMED);
}
/*
* A D2H Register FIS has been received with the 'I' bit set.
*
* The following commands will send this FIS upon the successful completion:
* 1. Non-data commands
* 2. DMA data-in command
* 3. DMA data-out command
* 4. PIO data-out command
*/
static int
{
int finished_slot, i, num = 0;
"ahci_intr_d2h_register_fis enter, port %d", port);
if (!ahci_portp->ahciport_pending_tags) {
/*
* Spurious interrupt. Nothing to be done.
*/
return (AHCI_SUCCESS);
}
"ahci_intr_d2h_reigster_fis: pending_tags = 0x%x, "
"port_cmd_issue = 0x%x, finished_tags = 0x%x,",
for (i = 0; i < ahci_ctlp->ahcictl_num_cmd_slots; i++) {
if ((0x1 << i) & finished_tags)
num++;
}
if (finished_slot == -1) {
goto out;
}
/*
* In case the interrupt generates before disabling for poll commands.
*/
if (satapkt->satapkt_op_mode &
goto out;
}
/* Return the status */
"ahci_intr_d2h_register_fis: sending up pkt 0x%p "
"with SATA_PKT_COMPLETED", (void *)satapkt);
out:
"ahci_intr_d2h_register_fis pending_tags = 0x%x",
return (AHCI_SUCCESS);
}
/*
* A PIO Setup FIS has been received with the 'I' bit set.
*
* The following commands will send this FIS upon the successful completion:
* PIO data-in command
*/
static int
{
int finished_slot, i, num = 0;
"ahci_intr_pio_setup_fis enter, port %d", port);
if (!ahci_portp->ahciport_pending_tags) {
/*
* Spurious interrupt. Nothing to be done.
*/
return (AHCI_SUCCESS);
}
"ahci_intr_pio_setup_fis: pending_tags = 0x%x, "
"port_cmd_issue = 0x%x, finished_tags = 0x%x,",
for (i = 0; i < ahci_ctlp->ahcictl_num_cmd_slots; i++) {
if ((0x1 << i) & finished_tags)
num++;
}
if (finished_slot == -1) {
goto out;
}
/*
* In case the interrupt generates before disabling.
*/
if (satapkt->satapkt_op_mode &
goto out;
}
/* Return the status */
"ahci_intr_pio_setup_fis: sending up pkt 0x%p "
"with SATA_PKT_COMPLETED", (void *)satapkt);
out:
"ahci_intr_pio_setup_fis pending_tags = 0x%x",
return (AHCI_SUCCESS);
}
/*
* A DMA Setup FIS has been received with the 'I' bit set
*
* DMA Setup FIS will be used during NCQ transfers to activate data
* transfer.
*
* For the first phase, this interrupt is disabled and we just
* log a debug message.
*/
/* ARGSUSED */
static int
{
"ahci_intr_dma_setup_fis enter, port %d", port);
return (AHCI_SUCCESS);
}
/*
* A Set Device Bits FIS has been received with the 'I' bit set
*
* Set Device Bits FIS will be sent during NCQ completion.
*
* For the first phase, this interrupt is disabled and we just log
* the debug message.
*/
/* ARGSUSED */
static int
{
"ahci_intr_set_device_bits_fis enter, port %d", port);
return (AHCI_SUCCESS);
}
/*
* An unknown FIS was received and has been copied into system memory.
*
* An unknown FIS is not considered an illegal FIS, unless the length
* received is more than 64 bytes. If an unknown FIS arrives with length
* <= 64 bytes, it is posted and the HBA continues normal operation.
*
* Therefore we just need to clear PxSERR.DIAG.F to clear the intr bit
* and log the debug message.
*/
static int
{
"ahci_intr_unknown_fis: port %d, port_serror = 0x%x",
port, port_serror);
/* Clear the interrupt bit by clearing PxSERR.DIAG.F */
return (AHCI_SUCCESS);
}
/*
* A PRD with the 'I' bit set has tranfered all of its data.
*
* The PRD Interrupt is an opportunistic interrupt. And it should not
* be used to definitively indicate the end of a transfer since two
* PRD interrupts could happen close in time together such that the
* second interrupt is missed when the first PRD interrupt is being
* cleared.
*
* For the first phase, this interrupt is disabled and we just
* log the debug message.
*/
/* ARGSUSED */
static int
{
"ahci_intr_descriptor_processed enter, port %d", port);
return (AHCI_SUCCESS);
}
/*
* 1=Change in Current Connect Status. 0=No change in Current Connect Status.
* This bit reflects the state of PxSERR.DIAG.X. This bit is only cleared
* when PxSERR.DIAG.X is cleared.
*
* When PxSERR.DIAG.X is set to one, it indicates a COMINIT signal was received.
*
* For the first phase, this interrupt is disabled.
*/
static int
{
"ahci_intr_port_connect_change: port %d, "
"ahci_intr_port_connect_change: port %d, "
/* Clear PxSERR.DIAG.X to clear the interrupt bit */
return (AHCI_SUCCESS);
}
/*
* Hot Plug Operation for platforms that support Mechanical Presence
* Switches.
*
* When set, it indicates that a mechanical presence switch attached to this
* port has been opened or closed, which may lead to a change in the connection
* state of the device. This bit is only valid if both CAP.SMPS and PxCMD.MPSP
* are set to '1'.
*
* For the first phase, this interrupt is disabled and we just log
* the debug message.
*/
/* ARGSUSED */
static int
{
"ahci_intr_device_mechanical_presence_status enter, "
"port %d", port);
if (!(cap_status & AHCI_HBA_CAP_SMPS) ||
!(port_cmd_status & AHCI_CMD_STATUS_MPSP)) {
"CAP.SMPS or PxCMD.MPSP is not set, so just ignore "
"the interrupt: cap_status = 0x%x, "
return (AHCI_SUCCESS);
}
if (port_cmd_status & AHCI_CMD_STATUS_MPSS) {
"The mechanical presence switch is open: "
"port %d, port_cmd_status = 0x%x",
} else {
"The mechanical presence switch is close: "
"port %d, port_cmd_status = 0x%x",
}
return (AHCI_SUCCESS);
}
/*
* Native Hot Plug Support.
*
* When set, it indicates that the internal PHYRDY signal changed state.
* This bit reflects the state of PxSERR.DIAG.N.
*/
static int
{
int dev_exists_now = 0;
int dev_existed_previously = 0;
"ahci_intr_phyrdy_change enter, port %d", port);
/* Clear PxSERR.DIAG.N to clear the interrupt bit */
(ahci_portp == NULL)) {
/* The whole controller setup is not yet done. */
return (AHCI_SUCCESS);
}
/* SStatus tells the presence of device. */
}
if (dev_exists_now) {
if (dev_existed_previously) {
/* Things are fine now. The loss was temporary. */
"device link lost/established", port);
&sdevice,
} else {
"device link established", port);
/* A new device has been detected. */
!= AHCI_SUCCESS) {
"phyrdy: port %d failed "
"at find dev signature", port);
}
== SATA_DTYPE_ATADISK) &&
!= AHCI_SUCCESS)) {
"phyrdy: port %d failed "
"at start port", port);
}
&sdevice,
}
} else { /* No device exists now */
if (dev_existed_previously) {
"device link lost", port);
ahci_portp, port);
/* An existing device is lost. */
&sdevice,
} else {
/* Spurious interrupt */
"spurious phy ready interrupt");
}
}
return (AHCI_SUCCESS);
}
/*
* PxIS.IPMS - Port Multiplier Errors.
*
* Which indicates that the HBA received a FIS from a device whose Port
* Multiplier field did not match what was expected.
*
* For the first phase, this interrupt is disabled, and we just log
* the debug message.
*/
/* ARGSUSED */
static int
{
"ahci_intr_incorrect_port_multiplier enter, port %d", port);
return (AHCI_SUCCESS);
}
/*
* PxIS.OFS - Fatal Error
*
* Which indicates that the HBA received more bytes from a device than
* was specified in the PRD table for the command.
*
* Overflow is a serious error, thus software should perform a fatal error
* recovery procedure to ensure that the HBA is brought back to a known
* condition before continuing.
*/
static int
{
"ahci_intr_overflow enter, port %d", port);
return (AHCI_SUCCESS);
}
/*
* PxIS.IFS and PxIS.INFS are errors that occur due to eletrical issues
* on the interface, or protocol miscommunication between the device
* and HBA.
*
* 1. in PxSERR.ERR, P bit is set to '1'
* 2. in PxSERR.DIAG, C or H bit is set to '1'
* 3. PhyRdy drop unexpectly, N bit is set to '1'
*/
/*
* PxIS.INFS - Interface Error
*
* Which indicates that the HBA encountered an error on the Serial ATA interface
* but was able to continue operation. It's non-fatal error, so we just log
* the debug message.
*
* The error occurred during a non-Data FIS, and the FIS will be
* re-transmitted by HBA automatically.
*/
static int
{
int current_slot;
"ahci_intr_interface_non_fatal_error: port %d, "
/*
* Record the error occurred command's slot.
*/
#if AHCI_DEBUG
"ahci_intr_interface_non_fatal_error: "
"pending_tags= 0x%x ",
"ahci_intr_interface_non_fatal_error: cmd= 0x%x ",
"ahci_intr_interface_non_fatal_error: port %d, "
"satapkt = %p will be re-transmitted",
}
#endif
return (AHCI_SUCCESS);
}
/*
* PxIS.IFS - Interface Error and Fatal Error
*
* Which indicates that the HBA encountered an error on the Serial ATA interface
* which caused the transfer to stop.
*
* The error occurred during a Data FIS, the transfer shall stop.
*/
static int
{
"ahci_intr_interface_fatal_error: port %d, "
return (AHCI_SUCCESS);
}
/*
* PxIS.HBDS - System Memory Error and Fatal Error
*
* Which indicates that the HBA encountered a data error
*/
static int
{
"ahci_intr_host_bus_data_error: port %d, "
return (AHCI_SUCCESS);
}
/*
* PxIS.HBFS - System Memory Error and Fatal Error
*
* Which indicates that the HBA encountered a host bus error that it cannot
* recover from, such as a bad software pointer.
*/
static int
{
"ahci_intr_host_bus_fatal_error: port %d, "
return (AHCI_SUCCESS);
}
/*
* PxIS.TFES - Device Error and Fatal Error
*
* This bit is set whenever the status register is updated by the device
* and the error bit (bit 0) is set.
*/
static int
{
"ahci_intr_task_file_error: port %d: "
return (AHCI_SUCCESS);
}
/*
* Hot Plug Operation for platforms that support Cold Presence Detect.
*
* When set, a device status has changed as detected by the cold presence
* detect logic. This bit can either be set due to a non-connected port
* receiving a device, or a connected port having its device removed.
* This bit is only valid if the port supports cold presence detect as
* indicated by PxCMD.CPD set to '1'.
*
* For the first phase, this interrupt is disabled and we just log
* the debug message.
*/
/* ARGSUSED */
static int
{
"ahci_intr_cold_port_detect enter, port %d", port);
if (!(port_cmd_status & AHCI_CMD_STATUS_CPD)) {
"port %d does not support cold presence detect, so "
"we just ignore this interrupt", port);
return (AHCI_SUCCESS);
}
"port %d device status has changed", port);
if (port_cmd_status & AHCI_CMD_STATUS_CPS) {
"port %d: a device is hot plugged", port);
&sdevice,
} else {
"port %d: a device is hot unplugged", port);
&sdevice,
}
return (AHCI_SUCCESS);
}
/*
* Enable the interrupts for a particular port.
*
* WARNING!!! ahciport_mutex should be acquired before the function
* is called.
*/
/* ARGSUSED */
static void
{
"ahci_enable_port_intrs enter, port %d", port);
/*
* Clear port interrupt status before enabling interrupt
*/
/*
* Clear the pending bit from IS.IPS
*/
/*
* Enable the following interrupts:
* Device to Host Register FIS Interrupt (DHRS)
* PIO Setup FIS Interrupt (PSS)
* Unknown FIS Interrupt (UFS)
* Port Connect Change Status (PCS)
* PhyRdy Change Status (PRCS)
* Overflow Status (OFS)
* Interface Non-fatal Error Status (INFS)
* Interface Fatal Error Status (IFS)
* Host Bus Data Error Status (HBDS)
* Host Bus Fatal Error Status (HBFS)
* Task File Error Status (TFES)
*/
}
/*
* Enable interrupts for all the ports.
*
* WARNING!!! ahcictl_mutex should be acquired before the function
* is called.
*/
static void
{
}
/*
* Disable interrupts for a particular port.
*
* WARNING!!! ahciport_mutex should be acquired before the function
* is called.
*/
/* ARGSUSED */
static void
{
"ahci_disable_port_intrs enter, port %d", port);
}
/*
* Disable interrupts for the whole HBA.
*
* The global bit is cleared, then all interrupt sources from all
* ports are disabled.
*
* WARNING!!! ahcictl_mutex should be acquired before the function
* is called.
*/
static void
{
ghc_control &= ~ AHCI_HBA_GHC_IE;
}
/*
* Handle INTx and legacy interrupts.
*/
static int
{
"ahci_add_legacy_intrs enter");
/* get number of interrupts. */
"ddi_intr_get_nintrs() failed, "
return (DDI_FAILURE);
}
/* Allocate an array of interrupt handles. */
/* call ddi_intr_alloc(). */
"ddi_intr_alloc() failed, rc %d\n", rc);
return (DDI_FAILURE);
}
for (x = 0; x < actual; x++) {
}
return (DDI_FAILURE);
}
/* Get intr priority. */
"ddi_intr_get_pri() failed");
for (x = 0; x < actual; x++) {
}
return (DDI_FAILURE);
}
/* Test for high level interrupt. */
"ahci_add_legacy_intrs: Hi level intr not supported");
for (x = 0; x < actual; x++) {
}
sizeof (ddi_intr_handle_t));
return (DDI_FAILURE);
}
/* Call ddi_intr_add_handler(). */
for (x = 0; x < actual; x++) {
"ddi_intr_add_handler() failed");
for (y = 0; y < actual; y++) {
(void) ddi_intr_free(
ahci_ctlp->ahcictl_intr_htable[y]);
}
return (DDI_FAILURE);
}
}
/* Call ddi_intr_enable() for legacy interrupts. */
for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) {
}
return (DDI_SUCCESS);
}
/*
* Handle MSI interrupts.
*/
static int
{
"ahci_add_msi_intrs enter");
/* get number of interrupts. */
"ddi_intr_get_nintrs() failed, "
return (DDI_FAILURE);
}
/* get number of available interrupts. */
"ddi_intr_get_navail() failed, "
return (DDI_FAILURE);
}
"ddi_intr_get_nvail returned %d, navail() returned %d",
}
/* Allocate an array of interrupt handles. */
/* call ddi_intr_alloc(). */
"ddi_intr_alloc() failed, rc %d\n", rc);
return (DDI_FAILURE);
}
/* use interrupt count returned */
}
/*
* Get priority for first msi, assume remaining are all the same.
*/
"ddi_intr_get_pri() failed");
/* Free already allocated intr. */
for (y = 0; y < actual; y++) {
}
return (DDI_FAILURE);
}
/* Test for high level interrupt. */
"ahci_add_msi_intrs: Hi level intr not supported");
/* Free already allocated intr. */
for (y = 0; y < actual; y++) {
}
sizeof (ddi_intr_handle_t));
return (DDI_FAILURE);
}
/* Call ddi_intr_add_handler(). */
for (x = 0; x < actual; x++) {
"ddi_intr_add_handler() failed");
/* Free already allocated intr. */
for (y = 0; y < actual; y++) {
(void) ddi_intr_free(
ahci_ctlp->ahcictl_intr_htable[y]);
}
return (DDI_FAILURE);
}
}
/* Call ddi_intr_block_enable() for MSI. */
} else {
/* Call ddi_intr_enable() for MSI non block enable. */
for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) {
(void) ddi_intr_enable(
ahci_ctlp->ahcictl_intr_htable[x]);
}
}
return (DDI_SUCCESS);
}
/*
* Removes the registered interrupts irrespective of whether they
* were legacy or MSI.
*
* WARNING!!! The controller interrupts must be disabled before calling
* this routine.
*/
static void
{
int x;
/* Disable all interrupts. */
/* Call ddi_intr_block_disable(). */
} else {
for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) {
(void) ddi_intr_disable(
ahci_ctlp->ahcictl_intr_htable[x]);
}
}
/* Call ddi_intr_remove_handler(). */
for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) {
(void) ddi_intr_remove_handler(
ahci_ctlp->ahcictl_intr_htable[x]);
}
}
/*
* This routine tries to put port into NotRunning state by clearing
* PxCMD.ST and PxCMD.FRE. Remember to clear PxCMD.FRE before clearing
* PxCMD.ST.
*
* WARNING!!! ahciport_mutex should be acquired before the function
* is called.
*/
/* ARGSUSED */
static int
{
int loop_count;
"ahci_port_into_notrunning_state enter: port %d", port);
if (!(port_cmd_status & AHCI_CMD_STATUS_ST))
goto clear_fre;
/* Wait until PxCMD.CR is cleared */
loop_count = 0;
do {
if (loop_count++ > AHCI_POLLRATE_PORT_IDLE) {
"clearing port %d CMD.CR timeout, "
"port_cmd_status = 0x%x", port,
/*
* We are effectively timing out after 0.5 sec.
* This value is specified in AHCI spec.
*/
break;
}
/* Wait for 10 millisec */
#ifndef __lock_lint
#endif /* __lock_lint */
} while (port_cmd_status & AHCI_CMD_STATUS_CR);
"ahci_port_into_notrunning_state: 1st loop count: %d, "
if (port_cmd_status & AHCI_CMD_STATUS_FRE) {
/* Wait until PxCMD.FR is cleared */
loop_count = 0;
do {
if (loop_count++ > AHCI_POLLRATE_PORT_IDLE) {
"clearing port %d CMD.FR "
"timeout, port_cmd_status = 0x%x",
/*
* We are effectively timing out after 0.5 sec.
* This value is specified in AHCI spec.
*/
break;
}
/* Wait for 10 millisec */
#ifndef __lock_lint
#endif /* __lock_lint */
} while (port_cmd_status & AHCI_CMD_STATUS_FR);
"ahci_port_into_notrunning_state: 2nd loop count: "
"%d, port_cmd_status = 0x%x",
}
if (port_cmd_status &
"port %d cannot be put in NotRunning state", port);
return (AHCI_FAILURE);
} else {
"port %d is put in NotRunning state", port);
return (AHCI_SUCCESS);
}
}
/*
* This routine will be called under five scenarios:
* 1. Initialize the port
* 2. To abort the packet(s)
* 3. To reset the port
* 4. Fatal error recovery
* 5. To abort the timeout packet(s)
*
* WARNING!!! ahciport_mutex should be acquired before the function
* is called.
*/
static int
{
int rval;
"ahci_restart_port_wait_till_ready: port %d enter", port);
if (rval == AHCI_SUCCESS) {
if (task_file_status & AHCI_TFD_STS_BSY ||
rval = AHCI_FAILURE;
}
goto out;
/* Set the reset in progress flag */
if (!(flag & AHCI_RESET_NO_EVENTS_UP)) {
}
if (rval != AHCI_SUCCESS) {
"ahci_restart_port_wait_till_ready: port %d failed",
port);
}
/* Indicate to the framework that a reset has happened. */
if (!(flag & AHCI_RESET_NO_EVENTS_UP)) {
} else {
}
if (ahci_ctlp->ahcictl_sata_hba_tran) {
&sdevice,
}
"sending event up: SATA_EVNT_RESET");
}
out:
if (!(flag & AHCI_PORT_INIT)) {
}
return (rval);
}
/*
* This routine is called under four scenarios:
* a) some commands failed with errors
* b) or we need to timeout some commands
* c) or we need to abort some commands
* d) or we need reset device/port/controller
*
* In all these scenarios, we need to send any pending unfinished
* commands up to sata framework.
*
* Only one mopping process at a time is allowed; this is achieved
* by checking AHCI_PORT_STATE_MOPPING by the caller.
*/
static void
{
int tmp_slot;
int i, num = 0;
"ahci_mop_commands entered: port: %d slot_status: 0x%x",
port, slot_status);
"ahci_mop_commands: failed_tags: 0x%x, "
"timeout_tags: 0x%x aborted_tags: 0x%x, "
"reset_tags: 0x%x", failed_tags,
/*
* We could be here for four reasons: abort, reset,
* timeout or error handling. Only one such mopping
* is allowed at a time.
*/
~failed_tags &
~aborted_tags &
~reset_tags &
/*
* Try to check if there are more than one command which have
* been finished.
*/
for (i = 0; i < ahci_ctlp->ahcictl_num_cmd_slots; i++) {
if ((0x1 << i) & finished_tags)
num++;
}
/* Set finished packets with SATA_PKT_COMPLETED */
while (finished_tags) {
if (tmp_slot == -1) {
break;
}
/* Return the status */
"sending up pkt 0x%p with SATA_PKT_COMPLETED",
(void *)satapkt);
}
ASSERT(finished_tags == 0);
/* Send up failed_tags with SATA_PKT_DEV_ERROR. */
while (failed_tags) {
if (tmp_slot == -1) {
break;
}
}
/* Return the status */
"sending up pkt 0x%p with SATA_PKT_DEV_ERROR",
(void *)satapkt);
}
ASSERT(failed_tags == 0);
/* Send up timeout_tags with SATA_PKT_TIMEOUT. */
while (timeout_tags) {
if (tmp_slot == -1) {
break;
}
"sending up pkt 0x%p with SATA_PKT_TIMEOUT",
(void *)satapkt);
}
ASSERT(timeout_tags == 0);
/* Set aborted packets with SATA_PKT_ABORTED */
while (aborted_tags) {
if (tmp_slot == -1) {
break;
}
}
"sending up pkt 0x%p with SATA_PKT_ABORTED",
(void *)satapkt);
}
ASSERT(aborted_tags == 0);
/* Reset tags are sent up to framework with SATA_PKT_RESET. */
while (reset_tags) {
if (tmp_slot == -1) {
break;
}
"sending up pkt 0x%p with SATA_PKT_RESET",
(void *)satapkt);
}
ASSERT(reset_tags == 0);
/* Set unfinished packets with SATA_PKT_BUSY */
while (unfinished_tags) {
if (tmp_slot == -1) {
break;
}
"sending up pkt 0x%p with SATA_PKT_BUSY",
(void *)satapkt);
}
ASSERT(unfinished_tags == 0);
}
/*
* Fatal errors will cause the HBA to enter the ERR: Fatal state. To recover,
* the port must be restarted.
*
* Fatal errors include the following:
* PxIS.OFS - Overflow Status
* PxIS.IFS - Interface Fatal Error Status
* PxIS.HBDS - Host Bus Data Error Status
* PxIS.HBFS - Host Bus Fatal Error Status
* PxIS.TFES - Task File Error Status
*
* WARNING!!! ahciport_mutex should be acquired before the function is called.
*/
static int
{
int current_slot;
"ahci_recovery_fatal_error enter port %d", port);
/*
* ahci_intr_phyrdy_change() may have rendered it to
* SATA_DTYPE_NONE.
*/
"ahci_recovery_fatal_error: no device attached, and just "
"return without doing anything", port);
return (SATA_SUCCESS);
}
/* Record the error occurred command slot */
/*
* For example, sometimes PxIS.OFS and PxIS.IFS can be set
* concurrently.
*/
"ahci_recovery_fatal_error: port %d has done "
"fatal error recovery, so return directory", port);
return (SATA_SUCCESS);
}
/*
* To prevent recursive enter to ahci_mop_commands, we need
* check AHCI_PORT_STATE_MOPPING flag.
*/
"ahci_recovery_fatal_error: port %d is in "
"mopping process, so return directly", port);
return (SATA_SUCCESS);
}
switch (error) {
case AHCI_INTR_STATUS_IFS:
case AHCI_INTR_STATUS_HBFS:
case AHCI_INTR_STATUS_HBDS:
/*
* For PxIS.IFS, PxIS.HBFS and PxIS.HBDS, we need to return
* PxSERR in satapkt.
*/
&spkt->satapkt_device);
break;
case AHCI_INTR_STATUS_TFES:
/*
* For PxIS.TFES, we need to return the status and error
* registers in sata_cmd structure
*/
break;
case AHCI_INTR_STATUS_OFS:
/*
* For PxIS.OFS, until now have no way to send the error
* to sata framework.
*/
"ahci_recovery_fatal_error: "
"PxOFS occured for port %d", port);
break;
default:
"Not supported error 0x%x for port %d",
break;
}
"ahci_recovery_fatal_error: current_slot = 0x%x "
port,
failed_tags, /* failed tags */
0, /* timeout tags */
0, /* aborted tags */
0); /* reset tags */
return (SATA_SUCCESS);
}
/*
* ahci_watchdog_handler() calls us if it detects that there are some
* commands which timed out.
*/
static void
{
"ahci_timeout_pkts entered");
/*
* To prevent recursive enter to ahci_mop_commands, we need
* check AHCI_PORT_STATE_MOPPING flag.
*/
"ahci_timeout_pkts: port %d is in "
"mopping process, so return directly ", port);
return;
}
/*
* Re-identify timeout tags because some previously checked commands
* could already complete.
*/
"ahci_timeout_pkts: port %d, finished_tags = 0x%x, "
"timeout_tags = 0x%x", port,
port,
0, /* failed tags */
timeout_tags, /* timeout tags */
0, /* aborted tags */
0); /* reset tags */
}
/*
* Watchdog handler kicks in every 5 seconds to timeout any commands pending
* for long time.
*/
static void
{
uint32_t pending_tags = 0;
uint32_t timeout_tags = 0;
int tmp_slot;
/* max number of cycles this packet should survive */
int max_life_cycles;
/* how many cycles this packet survived so far */
int watched_cycles;
"ahci_watchdog_handler entered");
continue;
}
continue;
}
timeout_tags = 0;
while (pending_tags) {
if (tmp_slot == -1) {
break;
}
/*
* We are overloading satapkt_hba_driver_private
* with watched_cycle count.
*
* If a packet has survived for more than it's
* max life cycles, it is a candidate for time
* out.
*/
watched_cycles = (int)(intptr_t)
ahci_watchdog_timeout - 1) /
if (watched_cycles > max_life_cycles) {
"port %d satapkt 0x%p timed out\n",
}
(void *)(intptr_t)watched_cycles;
}
}
if (timeout_tags) {
port, timeout_tags);
}
}
/* Re-install the watchdog timeout handler */
if (ahci_ctlp->ahcictl_timeout_id != 0) {
timeout((void (*)(void *))ahci_watchdog_handler,
}
}
/*
* Put a copy back to sata_cmd_t.
*/
static void
{
}
/*
* Dump the serror message to the log.
*/
static void
{
char *err_str;
if (port_serror & AHCI_SERROR_ERR_I) {
err_str = "Recovered Data Integrity Error (I)";
"command error: port: %d, error: %s",
}
if (port_serror & AHCI_SERROR_ERR_M) {
err_str = "Recovered Communication Error (M)";
"command error: port: %d, error: %s",
}
if (port_serror & AHCI_SERROR_ERR_T) {
err_str = "Transient Data Integrity Error (T)";
"command error: port: %d, error: %s",
}
if (port_serror & AHCI_SERROR_ERR_C) {
err_str =
"Persistent Communication or Data Integrity Error (C)";
"command error: port: %d, error: %s",
}
if (port_serror & AHCI_SERROR_ERR_P) {
err_str = "Protocol Error (P)";
"command error: port: %d, error: %s",
}
if (port_serror & AHCI_SERROR_ERR_E) {
err_str = "Internal Error (E)";
"command error: port: %d, error: %s",
}
if (port_serror & AHCI_SERROR_DIAG_N) {
err_str = "PhyRdy Change (N)";
"command error: port: %d, error: %s",
}
if (port_serror & AHCI_SERROR_DIAG_I) {
err_str = "Phy Internal Error (I)";
"command error: port: %d, error: %s",
}
if (port_serror & AHCI_SERROR_DIAG_W) {
err_str = "Comm Wake (W)";
"command error: port: %d, error: %s",
}
if (port_serror & AHCI_SERROR_DIAG_B) {
err_str = "10B to 8B Decode Error (B)";
"command error: port: %d, error: %s",
}
if (port_serror & AHCI_SERROR_DIAG_D) {
err_str = "Disparity Error (D)";
"command error: port: %d, error: %s",
}
if (port_serror & AHCI_SERROR_DIAG_C) {
err_str = "CRC Error (C)";
"command error: port: %d, error: %s",
}
if (port_serror & AHCI_SERROR_DIAG_H) {
err_str = "Handshake Error (H)";
"command error: port: %d, error: %s",
}
if (port_serror & AHCI_SERROR_DIAG_S) {
err_str = "Link Sequence Error (S)";
"command error: port: %d, error: %s",
}
if (port_serror & AHCI_SERROR_DIAG_T) {
err_str = "Transport state transition error (T)";
"command error: port: %d, error: %s",
}
if (port_serror & AHCI_SERROR_DIAG_F) {
err_str = "Unknown FIS Type (F)";
"command error: port: %d, error: %s",
}
if (port_serror & AHCI_SERROR_DIAG_X) {
err_str = "Exchanged (X)";
"command error: port: %d, error: %s",
}
}
/*
* This routine is to calculate the total number of ports implemented
* by the HBA.
*/
static int
{
uint8_t i;
int num = 0;
for (i = 0; i < AHCI_MAX_PORTS; i++) {
num++;
}
return (num);
}
static void
{
if (ahci_ctlp) {
} else {
}
}