a72f7ea693101cc48bafbb4db6bb437d828011c4ql/*
9aa73b6813b3fd35e78fcc44fd17535e765e504cQin Michael Li * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Use is subject to license terms.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql/*
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Copyright (c) 2004, 2005 David Young. All rights reserved.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql *
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Driver for the Realtek RTL8180 802.11 MAC/BBP by David Young.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql *
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Redistribution and use in source and binary forms, with or without
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * modification, are permitted provided that the following conditions
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * are met:
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 1. Redistributions of source code must retain the above copyright
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * notice, this list of conditions and the following disclaimer.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 2. Redistributions in binary form must reproduce the above copyright
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * notice, this list of conditions and the following disclaimer in the
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * documentation and/or other materials provided with the distribution.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 3. The name of David Young may not be used to endorse or promote
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * products derived from this software without specific prior
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * written permission.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql *
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * OF SUCH DAMAGE.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#ifndef _RTWVAR_H_
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define _RTWVAR_H_
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
9aa73b6813b3fd35e78fcc44fd17535e765e504cQin Michael Li#ifdef __cplusplus
9aa73b6813b3fd35e78fcc44fd17535e765e504cQin Michael Liextern "C" {
9aa73b6813b3fd35e78fcc44fd17535e765e504cQin Michael Li#endif
9aa73b6813b3fd35e78fcc44fd17535e765e504cQin Michael Li
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#include <sys/list.h>
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#include <sys/net80211.h>
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#ifndef __func__
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define __func__ ""
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#endif
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4qlextern void rtw_dbg(uint32_t dbg_flags, const int8_t *fmt, ...);
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_DEBUG_TUNE 0x000001
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_DEBUG_PKTFILT 0x000002
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_DEBUG_XMIT 0x000004
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_DEBUG_DMA 0x000008
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_DEBUG_NODE 0x000010
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_DEBUG_PWR 0x000020
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_DEBUG_ATTACH 0x000040
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_DEBUG_REGDUMP 0x000080
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_DEBUG_ACCESS 0x000100
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_DEBUG_RESET 0x000200
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_DEBUG_INIT 0x000400
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_DEBUG_PKTDUMP 0x000800
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_DEBUG_RECV 0x001000
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_DEBUG_RECV_DESC 0x002000
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_DEBUG_IOSTATE 0x004000
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_DEBUG_INTR 0x008000
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_DEBUG_PHY 0x010000
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_DEBUG_PHYIO 0x020000
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_DEBUG_PHYBITIO 0x040000
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_DEBUG_TIMEOUT 0x080000
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_DEBUG_BUGS 0x100000
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_DEBUG_BEACON 0x200000
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_DEBUG_WIFICFG 0x400000
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_DEBUG_80211 0x800000
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_DEBUG_MAX 0xffffff
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#ifdef DEBUG
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_DPRINTF \
a72f7ea693101cc48bafbb4db6bb437d828011c4ql rtw_dbg
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#else /* DEBUG */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_DPRINTF
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#endif /* DEBUG */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4qlenum rtw_locale {
a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_LOCALE_USA = 0,
a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_LOCALE_EUROPE,
a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_LOCALE_JAPAN,
a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_LOCALE_UNKNOWN
a72f7ea693101cc48bafbb4db6bb437d828011c4ql};
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4qlenum rtw_rfchipid {
a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_RFCHIPID_RESERVED = 0,
a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_RFCHIPID_INTERSIL = 1,
a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_RFCHIPID_RFMD = 2,
a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_RFCHIPID_PHILIPS = 3,
a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_RFCHIPID_MAXIM = 4,
a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_RFCHIPID_GCT = 5
a72f7ea693101cc48bafbb4db6bb437d828011c4ql};
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql/*
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * sc_flags
a72f7ea693101cc48bafbb4db6bb437d828011c4ql */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_F_ENABLED 0x00000001 /* chip is enabled */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_F_DIGPHY 0x00000002 /* digital PHY */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_F_DFLANTB 0x00000004 /* B antenna is default */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_F_ANTDIV 0x00000010 /* h/w antenna diversity */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_F_9356SROM 0x00000020 /* 93c56 SROM */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_F_SLEEP 0x00000040 /* chip is asleep */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_F_INVALID 0x00000080 /* chip is absent */
9aa73b6813b3fd35e78fcc44fd17535e765e504cQin Michael Li#define RTW_F_SUSPEND 0x00000100 /* driver is suspended */
9aa73b6813b3fd35e78fcc44fd17535e765e504cQin Michael Li#define RTW_F_PLUMBED 0x00000200 /* driver is plumbed */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_F_ATTACHED 0x01000000 /* driver is attached */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql/*
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * all PHY flags
a72f7ea693101cc48bafbb4db6bb437d828011c4ql */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_F_ALLPHY (RTW_F_DIGPHY|RTW_F_DFLANTB|RTW_F_ANTDIV)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4qlenum rtw_access {RTW_ACCESS_NONE = 0,
a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_ACCESS_CONFIG = 1,
a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_ACCESS_ANAPARM = 2};
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4qlstruct rtw_regs {
a72f7ea693101cc48bafbb4db6bb437d828011c4ql ddi_acc_handle_t r_handle;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql caddr_t r_base;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql enum rtw_access r_access;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql};
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_SR_GET(sr, ofs) \
a72f7ea693101cc48bafbb4db6bb437d828011c4ql (((sr)->sr_content[(ofs)/2] >> (((ofs) % 2 == 0) ? 0 : 8)) & 0xff)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_SR_GET16(sr, ofs) \
a72f7ea693101cc48bafbb4db6bb437d828011c4ql (RTW_SR_GET((sr), (ofs)) | (RTW_SR_GET((sr), (ofs) + 1) << 8))
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4qlstruct rtw_srom {
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint16_t *sr_content;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint16_t sr_size;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql};
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_NTXPRI 4 /* number of Tx priorities */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_TXPRILO 0
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_TXPRIMD 1
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_TXPRIHI 2
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_TXPRIBCN 3 /* beacon priority */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_MAXPKTSEGS 64 /* Max 64 segments per Tx packet */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql/*
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Note well: the descriptor rings must begin on RTW_DESC_ALIGNMENT
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * boundaries. I allocate them consecutively from one buffer, so
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * just round up.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_TXQLENLO 64 /* low-priority queue length */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_TXQLENMD 64 /* medium-priority */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_TXQLENHI 64 /* high-priority */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_TXQLENBCN 2 /* beacon */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_NTXDESCLO RTW_TXQLENLO
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_NTXDESCMD RTW_TXQLENMD
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_NTXDESCHI RTW_TXQLENHI
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_NTXDESCBCN RTW_TXQLENBCN
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_NTXDESCTOTAL (RTW_NTXDESCLO + RTW_NTXDESCMD + \
a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_NTXDESCHI + RTW_NTXDESCBCN)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_RXQLEN 64
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_DMA_SYNC(area, flag) ((void) ddi_dma_sync((area).dma_hdl,\
a72f7ea693101cc48bafbb4db6bb437d828011c4ql (area).offset, (area).alength, (flag)))
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_DMA_SYNC_DESC(area, offset, len, flag) \
a72f7ea693101cc48bafbb4db6bb437d828011c4ql ((void) ddi_dma_sync((area).dma_hdl, offset, len, (flag)))
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_MINC(x, y) (x) = ((x + 1) % y)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define list_empty(a) ((a)->list_head.list_next == &(a)->list_head)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4qltypedef struct dma_area {
a72f7ea693101cc48bafbb4db6bb437d828011c4ql ddi_acc_handle_t acc_hdl; /* handle for memory */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql caddr_t mem_va; /* CPU VA of memory */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t nslots; /* number of slots */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t size; /* size per slot */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql size_t alength; /* allocated size */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql /* >= product of above */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql ddi_dma_handle_t dma_hdl; /* DMA handle */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql offset_t offset; /* relative to handle */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql ddi_dma_cookie_t cookie; /* associated cookie */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t ncookies; /* must be 1 */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t token; /* arbitrary identifier */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql} dma_area_t; /* 0x50 (80) bytes */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4qlstruct rtw_txbuf {
a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct rtw_txdesc *txdesc; /* virtual addr of desc */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t bf_daddr; /* physical addr of desc */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t next_bf_daddr; /* physical addr of next desc */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql dma_area_t bf_dma; /* dma area for buf */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct ieee80211_node *bf_in; /* pointer to the node */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql list_node_t bf_node;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t order;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql};
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4qlstruct rtw_rxbuf {
a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct rtw_rxdesc *rxdesc; /* virtual addr of desc */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t bf_daddr; /* physical addr of desc */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql dma_area_t bf_dma; /* dma area for buf */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql};
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4qlstruct rtw_txq {
a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct rtw_txdesc *txdesc_h;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct rtw_txbuf *txbuf_h;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t tx_prod;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t tx_cons;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t tx_nfree;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql kmutex_t txbuf_lock;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql list_t tx_free_list;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql list_t tx_dirty_list;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql};
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4qlstruct rtw_descs {
a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct rtw_txdesc hd_txlo[RTW_NTXDESCLO];
a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct rtw_txdesc hd_txmd[RTW_NTXDESCMD];
a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct rtw_txdesc hd_txhi[RTW_NTXDESCHI];
a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct rtw_rxdesc hd_rx[RTW_RXQLEN];
a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct rtw_txdesc hd_bcn[RTW_NTXDESCBCN];
a72f7ea693101cc48bafbb4db6bb437d828011c4ql};
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_DESC_OFFSET(ring, i) offsetof(struct rtw_descs, ring[i])
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_RING_OFFSET(ring) RTW_DESC_OFFSET(ring, 0)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_RING_BASE(baseaddr0, ring) \
a72f7ea693101cc48bafbb4db6bb437d828011c4ql (baseaddr0 + RTW_RING_OFFSET(ring))
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql/*
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * One Time Unit (TU) is 1Kus = 1024 microseconds.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define IEEE80211_DUR_TU 1024
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql/*
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * IEEE 802.11b durations for DSSS PHY in microseconds
a72f7ea693101cc48bafbb4db6bb437d828011c4ql */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define IEEE80211_DUR_DS_LONG_PREAMBLE 144
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define IEEE80211_DUR_DS_SHORT_PREAMBLE 72
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define IEEE80211_DUR_DS_SLOW_PLCPHDR 48
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define IEEE80211_DUR_DS_FAST_PLCPHDR 24
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define IEEE80211_DUR_DS_SLOW_ACK 112
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define IEEE80211_DUR_DS_FAST_ACK 56
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define IEEE80211_DUR_DS_SLOW_CTS 112
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define IEEE80211_DUR_DS_FAST_CTS 56
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define IEEE80211_DUR_DS_SLOT 20
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define IEEE80211_DUR_DS_SIFS 10
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define IEEE80211_DUR_DS_PIFS (IEEE80211_DUR_DS_SIFS + IEEE80211_DUR_DS_SLOT)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define IEEE80211_DUR_DS_DIFS (IEEE80211_DUR_DS_SIFS + \
a72f7ea693101cc48bafbb4db6bb437d828011c4ql 2 * IEEE80211_DUR_DS_SLOT)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define IEEE80211_DUR_DS_EIFS (IEEE80211_DUR_DS_SIFS + \
a72f7ea693101cc48bafbb4db6bb437d828011c4ql IEEE80211_DUR_DS_SLOW_ACK + \
a72f7ea693101cc48bafbb4db6bb437d828011c4ql IEEE80211_DUR_DS_LONG_PREAMBLE + \
a72f7ea693101cc48bafbb4db6bb437d828011c4ql IEEE80211_DUR_DS_SLOW_PLCPHDR + \
a72f7ea693101cc48bafbb4db6bb437d828011c4ql IEEE80211_DUR_DIFS)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql/*
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 802.11 frame duration definitions.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql */
a72f7ea693101cc48bafbb4db6bb437d828011c4qlstruct rtw_ieee80211_duration {
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint16_t d_rts_dur;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint16_t d_data_dur;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint16_t d_plcp_len;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint8_t d_residue; /* unused octets in time slot */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint8_t resv;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql};
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#ifdef RTW_RADIOTAP
a72f7ea693101cc48bafbb4db6bb437d828011c4ql/*
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Radio capture format for RTL8180.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_RX_RADIOTAP_PRESENT \
a72f7ea693101cc48bafbb4db6bb437d828011c4ql ((1 << IEEE80211_RADIOTAP_TSFT) | \
a72f7ea693101cc48bafbb4db6bb437d828011c4ql (1 << IEEE80211_RADIOTAP_FLAGS) | \
a72f7ea693101cc48bafbb4db6bb437d828011c4ql (1 << IEEE80211_RADIOTAP_RATE) | \
a72f7ea693101cc48bafbb4db6bb437d828011c4ql (1 << IEEE80211_RADIOTAP_CHANNEL) | \
a72f7ea693101cc48bafbb4db6bb437d828011c4ql (1 << IEEE80211_RADIOTAP_LOCK_QUALITY) | \
a72f7ea693101cc48bafbb4db6bb437d828011c4ql (1 << IEEE80211_RADIOTAP_DB_ANTSIGNAL) | \
a72f7ea693101cc48bafbb4db6bb437d828011c4ql 0)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4qlstruct rtw_rx_radiotap_header {
a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct ieee80211_radiotap_header rr_ihdr;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint64_t rr_tsft;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint8_t rr_flags;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint8_t rr_rate;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint16_t rr_chan_freq;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint16_t rr_chan_flags;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint16_t rr_barker_lock;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint8_t rr_antsignal;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql} __attribute__((__packed__));
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_TX_RADIOTAP_PRESENT \
a72f7ea693101cc48bafbb4db6bb437d828011c4ql ((1 << IEEE80211_RADIOTAP_FLAGS) | \
a72f7ea693101cc48bafbb4db6bb437d828011c4ql (1 << IEEE80211_RADIOTAP_RATE) | \
a72f7ea693101cc48bafbb4db6bb437d828011c4ql (1 << IEEE80211_RADIOTAP_CHANNEL) | \
a72f7ea693101cc48bafbb4db6bb437d828011c4ql 0)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4qlstruct rtw_tx_radiotap_header {
a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct ieee80211_radiotap_header rt_ihdr;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint8_t rt_flags;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint8_t rt_rate;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint16_t rt_chan_freq;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint16_t rt_chan_flags;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql} __attribute__((__packed__));
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#endif
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4qlenum rtw_attach_state {FINISHED, FINISH_DESCMAP_LOAD, FINISH_DESCMAP_CREATE,
a72f7ea693101cc48bafbb4db6bb437d828011c4ql FINISH_DESC_MAP, FINISH_DESC_ALLOC, FINISH_RXMAPS_CREATE,
a72f7ea693101cc48bafbb4db6bb437d828011c4ql FINISH_TXMAPS_CREATE, FINISH_RESET, FINISH_READ_SROM, FINISH_PARSE_SROM,
a72f7ea693101cc48bafbb4db6bb437d828011c4ql FINISH_RF_ATTACH, FINISH_ID_STA, FINISH_TXDESCBLK_SETUP,
a72f7ea693101cc48bafbb4db6bb437d828011c4ql FINISH_TXCTLBLK_SETUP, DETACHED};
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4qlstruct rtw_hooks {
a72f7ea693101cc48bafbb4db6bb437d828011c4ql void *rh_shutdown; /* shutdown hook */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql void *rh_power; /* power management hook */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql};
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4qlenum rtw_pwrstate { RTW_OFF = 0, RTW_SLEEP, RTW_ON };
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4qltypedef void (*rtw_continuous_tx_cb_t)(void *arg, int);
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4qlstruct rtw_phy {
a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct rtw_rf *p_rf;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct rtw_regs *p_regs;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql};
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4qlstruct rtw_bbpset {
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint_t bb_antatten;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint_t bb_chestlim;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint_t bb_chsqlim;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint_t bb_ifagcdet;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint_t bb_ifagcini;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint_t bb_ifagclimit;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint_t bb_lnadet;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint_t bb_sys1;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint_t bb_sys2;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint_t bb_sys3;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint_t bb_trl;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint_t bb_txagc;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql};
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4qlstruct rtw_rf {
a72f7ea693101cc48bafbb4db6bb437d828011c4ql void (*rf_destroy)(struct rtw_rf *);
a72f7ea693101cc48bafbb4db6bb437d828011c4ql /*
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * args: frequency, txpower, power state
a72f7ea693101cc48bafbb4db6bb437d828011c4ql */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql int (*rf_init)(struct rtw_rf *, uint_t, uint8_t, enum rtw_pwrstate);
a72f7ea693101cc48bafbb4db6bb437d828011c4ql /*
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * arg: power state
a72f7ea693101cc48bafbb4db6bb437d828011c4ql */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql int (*rf_pwrstate)(struct rtw_rf *, enum rtw_pwrstate);
a72f7ea693101cc48bafbb4db6bb437d828011c4ql /*
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * arg: frequency
a72f7ea693101cc48bafbb4db6bb437d828011c4ql */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql int (*rf_tune)(struct rtw_rf *, uint_t);
a72f7ea693101cc48bafbb4db6bb437d828011c4ql /*
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * arg: txpower
a72f7ea693101cc48bafbb4db6bb437d828011c4ql */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql int (*rf_txpower)(struct rtw_rf *, uint8_t);
a72f7ea693101cc48bafbb4db6bb437d828011c4ql rtw_continuous_tx_cb_t rf_continuous_tx_cb;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql void *rf_continuous_tx_arg;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct rtw_bbpset rf_bbpset;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql};
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4qltypedef int (*rtw_rf_write_t)(struct rtw_regs *, enum rtw_rfchipid, uint_t,
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t);
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4qlstruct rtw_rfbus {
a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct rtw_regs *b_regs;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql rtw_rf_write_t b_write;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql};
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4qlstruct rtw_max2820 {
a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct rtw_rf mx_rf;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct rtw_rfbus mx_bus;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql int mx_is_a; /* 1: MAX2820A/MAX2821A */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql};
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4qlstruct rtw_sa2400 {
a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct rtw_rf sa_rf;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct rtw_rfbus sa_bus;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql int sa_digphy; /* 1: digital PHY */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql};
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4qltypedef void (*rtw_pwrstate_t)(struct rtw_regs *, enum rtw_pwrstate, int, int);
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4qlunion rtw_keys {
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint8_t rk_keys[4][16];
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t rk_words[16];
a72f7ea693101cc48bafbb4db6bb437d828011c4ql};
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_LED_SLOW_TICKS MAX(1, hz/2)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_LED_FAST_TICKS MAX(1, hz/10)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4qlstruct rtw_led_state {
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_LED0 0x1
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_LED1 0x2
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint8_t ls_slowblink:2;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint8_t ls_actblink:2;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint8_t ls_default:2;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint8_t ls_state;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint8_t ls_event;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_LED_S_RX 0x1
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_LED_S_TX 0x2
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_LED_S_SLOW 0x4
a72f7ea693101cc48bafbb4db6bb437d828011c4ql};
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4qltypedef struct rtw_softc {
a72f7ea693101cc48bafbb4db6bb437d828011c4ql ieee80211com_t sc_ic; /* IEEE 802.11 common */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql dev_info_t *sc_dev; /* back pointer to dev_info_t */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql kmutex_t sc_genlock;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct rtw_regs sc_regs;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql ddi_acc_handle_t sc_cfg_handle;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql caddr_t sc_cfg_base;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql enum ieee80211_phymode sc_curmode;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t sc_flags;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t sc_invalid;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql ddi_iblock_cookie_t sc_iblock;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t sc_need_reschedule;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint16_t sc_cachelsz; /* cache line size */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uchar_t sc_macaddr[6];
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql enum rtw_rfchipid sc_rfchipid;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql enum rtw_locale sc_locale;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint8_t sc_phydelay;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t sc_dmabuf_size;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql dma_area_t sc_desc_dma;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct rtw_txq sc_txq[RTW_NTXPRI];
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct rtw_rxdesc *rxdesc_h;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct rtw_rxbuf *rxbuf_h;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t rx_next;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql kmutex_t rxbuf_lock;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql kmutex_t sc_txlock;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct rtw_srom sc_srom;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql enum rtw_pwrstate sc_pwrstate;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql rtw_pwrstate_t sc_pwrstate_cb;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct rtw_rf *sc_rf;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint16_t sc_inten;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql void (*sc_intr_ack)(struct rtw_regs *);
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql int (*sc_enable)(struct rtw_softc *);
a72f7ea693101cc48bafbb4db6bb437d828011c4ql void (*sc_disable)(struct rtw_softc *);
a72f7ea693101cc48bafbb4db6bb437d828011c4ql void (*sc_power)(struct rtw_softc *, int);
a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct rtw_hooks sc_hooks;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint_t sc_cur_chan;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t sc_tsfth; /* most significant TSFT bits */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t sc_rcr; /* RTW_RCR */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint8_t sc_csthr; /* carrier-sense threshold */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint8_t sc_rev; /* PCI/Cardbus revision */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t sc_anaparm; /* register RTW_ANAPARM */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#ifdef RTW_RADIOTAP
a72f7ea693101cc48bafbb4db6bb437d828011c4ql union {
a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct rtw_rx_radiotap_header tap;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint8_t pad[64];
a72f7ea693101cc48bafbb4db6bb437d828011c4ql } sc_rxtapu;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql union {
a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct rtw_tx_radiotap_header tap;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint8_t pad[64];
a72f7ea693101cc48bafbb4db6bb437d828011c4ql } sc_txtapu;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#endif
a72f7ea693101cc48bafbb4db6bb437d828011c4ql union rtw_keys sc_keys;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql int sc_txkey;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql struct rtw_led_state sc_led_state;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql int sc_hwverid;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql int (*sc_newstate)(ieee80211com_t *,
a72f7ea693101cc48bafbb4db6bb437d828011c4ql enum ieee80211_state, int);
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql timeout_id_t sc_scan_id;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql timeout_id_t sc_ratectl_id;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t sc_tx_ok;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t sc_tx_err;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t sc_tx_retr;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t sc_xmtretry;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t sc_noxmtbuf;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t sc_norcvbuf;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t sc_bytexmt64;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t sc_bytercv64;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t sc_pktxmt64;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t sc_pktrcv64;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t sc_intr;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t sc_ioerror;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t hw_start;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql uint32_t hw_go;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql} rtw_softc_t;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_SC(ic) ((rtw_softc_t *)ic)
9aa73b6813b3fd35e78fcc44fd17535e765e504cQin Michael Li#ifdef __cplusplus
9aa73b6813b3fd35e78fcc44fd17535e765e504cQin Michael Li}
9aa73b6813b3fd35e78fcc44fd17535e765e504cQin Michael Li#endif
a72f7ea693101cc48bafbb4db6bb437d828011c4ql
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#endif /* _RTWVAR_H_ */