9aa73b6813b3fd35e78fcc44fd17535e765e504cQin Michael Li * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Use is subject to license terms.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Copyright (c) 2004, 2005 David Young. All rights reserved.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Programmed for NetBSD by David Young.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Redistribution and use in source and binary forms, with or without
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * modification, are permitted provided that the following conditions
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * are met:
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 1. Redistributions of source code must retain the above copyright
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * notice, this list of conditions and the following disclaimer.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 2. Redistributions in binary form must reproduce the above copyright
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * notice, this list of conditions and the following disclaimer in the
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * documentation and/or other materials provided with the distribution.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 3. The name of David Young may not be used to endorse or promote
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * products derived from this software without specific prior
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * written permission.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * OF SUCH DAMAGE.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql/* Macros for bit twiddling. */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * nth bit, BIT(0) == 0x1.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * bits m through n, m < n.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define BITS(m, n) ((BIT(MAX((m), (n)) + 1) - 1) ^ (BIT(MIN((m), (n))) - 1))
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * find least significant bit that is set
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * for x a power of two and p a non-negative integer, is x a greater
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * power than 2**p?
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define MASK_TO_SHIFT2(m) (GTEQ_POWER(LOWEST_SET_BIT((m)), 1) ? 1 : 0)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define MASK_AND_RSHIFT(x, mask) (((x) & (mask)) >> MASK_TO_SHIFT(mask))
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define MASK_AND_REPLACE(reg, val, mask) ((reg & ~mask) | LSHIFT(val, mask))
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#endif /* _BIT_TWIDDLE */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql/* RTL8180L Host Control and Status Registers */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * ID Register: MAC addr, 6 bytes.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Auto-loaded from EEPROM. Read by byte, by word, or by double word,
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * but write only by double word.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Timing Synchronization Function Timer Register,
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * low word, 32b, read-only.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Transmit Low Priority Descriptors Start Address,
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 32b, 256-byte alignment.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Transmit Normal Priority Descriptors Start Address,
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 32b, 256-byte alignment.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Transmit High Priority Descriptors Start Address,
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 32b, 256-byte alignment.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 1: use short PLCP header for CTS/ACK packet,
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 0: use long PLCP header
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_BRSR_MBR8180_MASK BITS(1, 0) /* Maximum Basic Service Rate */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_BRSR_MBR8180_1MBPS LSHIFT(0, RTW_BRSR_MBR8180_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_BRSR_MBR8180_2MBPS LSHIFT(1, RTW_BRSR_MBR8180_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_BRSR_MBR8180_5MBPS LSHIFT(2, RTW_BRSR_MBR8180_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_BRSR_MBR8180_11MBPS LSHIFT(3, RTW_BRSR_MBR8180_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 8181 and 8180 docs conflict!
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * BSSID, 6 bytes
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Reset: host sets to 1 to disable
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * transmitter & receiver, reinitialize FIFO.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * RTL8180L sets to 0 to signal completion.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Receiver Enable: host enables receiver
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * by writing 1. RTL8180L indicates receiver
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * is active with 1. After power-up, host
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * must wait for reset before writing.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Transmitter Enable: host enables transmitter
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * by writing 1. RTL8180L indicates transmitter
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * is active with 1. After power-up, host
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * must wait for reset before writing.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * PCI Multiple Read/Write enable:
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 1 enables,
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 0 disables. XXX RTL8180, only?
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Time Out: 1 indicates RTW_TSFTR[0:31] = RTW_TINT
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Beacon Time Out: time for host to prepare beacon:
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * RTW_TSFTR % (RTW_BCNITV_BCNITV * TU) =
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * (RTW_BCNITV_BCNITV * TU - RTW_BINTRITV)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * ATIM Time Out: ATIM interval will pass,
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * RTW_TSFTR % (RTW_BCNITV_BCNITV * TU) =
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * (RTW_ATIMWND_ATIMWND * TU - RTW_ATIMTRITV)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Tx Beacon Descriptor Error:
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * beacon transmission aborted because
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * frame Rx'd
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_INTR_TBDOK BIT(10) /* Tx Beacon Descriptor OK */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Tx High Priority Descriptor Error:
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * reached short/long retry limit
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_INTR_THPDOK BIT(8) /* Tx High Priority Descriptor OK */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Tx Normal Priority Descriptor Error:
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * reached short/long retry limit
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_INTR_TNPDOK BIT(6) /* Tx Normal Priority Descriptor OK */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Rx FIFO Overflow: either RDU (see below)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * or PCI bus too slow/busy
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_INTR_RDU BIT(4) /* Rx Descriptor Unavailable */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Tx Low Priority Descriptor Error
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * reached short/long retry limit
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_INTR_TLPDOK BIT(2) /* Tx Low Priority Descriptor OK */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_INTR_RER BIT(1) /* Rx Error: CRC32 or ICV error */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Convenient interrupt conjunctions.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_INTR_TX (RTW_INTR_TLPDER|RTW_INTR_TLPDOK|RTW_INTR_THPDER|\
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_INTR_IOERROR (RTW_INTR_TXFOVW|RTW_INTR_RXFOVW|RTW_INTR_RDU)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_TCR 0x40 /* Transmit Configuration Register, 32b */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_TCR_CWMIN BIT(31) /* 1: CWmin = 8, 0: CWmin = 32. */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 1: host assigns 802.11 sequence number,
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 0: hardware assigns sequence number
a72f7ea693101cc48bafbb4db6bb437d828011c4ql/* Hardware version ID, read-only */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_TCR_HWVERID_D LSHIFT(26, RTW_TCR_HWVERID_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_TCR_HWVERID_F LSHIFT(27, RTW_TCR_HWVERID_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Set ACK/CTS Timeout (EIFS).
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 1: ACK rate = max(RTW_BRSR_MBR, Rx rate) (XXX not min? typo in datasheet?)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 0: ACK rate = 1Mbps
a72f7ea693101cc48bafbb4db6bb437d828011c4ql/* Max DMA Burst Size per Tx DMA Burst */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_TCR_DISCW BIT(20) /* disable 802.11 random backoff */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * host lets RTL8180 append ICV to WEP packets
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Loopback Test: disables TXI/TXQ outputs.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_TCR_LBK_NORMAL LSHIFT(0, RTW_TCR_LBK_MASK) /* normal ops */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_TCR_LBK_MAC LSHIFT(1, RTW_TCR_LBK_MASK) /* MAC loopback */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_TCR_LBK_BBP LSHIFT(2, RTW_TCR_LBK_MASK) /* baseband loop. */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_TCR_LBK_CONT LSHIFT(3, RTW_TCR_LBK_MASK) /* continuous Tx */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 0: RTL8180 appends CRC32
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 1: host appends CRC32
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * (I *think* this is right. The docs have a mysterious
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * description in the passive voice.)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_TCR_SRL_MASK BITS(15, 8) /* Short Retry Limit */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_TCR_LRL_MASK BITS(7, 0) /* Long Retry Limit */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_RCR 0x44 /* Receive Configuration Register, 32b */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * only do Early Rx on packets longer than 1536 bytes
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_RCR_ENCS2 BIT(30) /* enable carrier sense method 2 */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_RCR_ENCS1 BIT(29) /* enable carrier sense method 1 */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_RCR_ENMARP BIT(28) /* enable MAC auto-reset PHY */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Check BSSID/ToDS/FromDS: set "Link On" when received BSSID
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * matches RTW_BSSID and received ToDS/FromDS are appropriate
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * according to RTW_MSR_NETYPE.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_RCR_APWRMGT BIT(22) /* accept packets w/ PWRMGMT bit set */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * when RTW_MSR_NETYPE == RTW_MSR_NETYPE_INFRA_OK, accept
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * broadcast/multicast packets whose 3rd address matches RTL8180's MAC.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_RCR_AMF BIT(20) /* accept management frames */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Rx FIFO Threshold: RTL8180 begins PCI transfer when this many data
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * bytes are received
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_RCR_AICV BIT(12) /* accept frames w/ ICV errors */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Max DMA Burst Size per Rx DMA Burst
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_RCR_MXDMA_UNLIMITED LSHIFT(7, RTW_RCR_MXDMA_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * EEPROM type, read-only. 1: EEPROM is 93c56, 0: 93c46
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_RCR_ACRC32 BIT(5) /* accept frames w/ CRC32 errors */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * accept physical match frames. XXX means PLCP header ok?
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_RCR_AAP BIT(0) /* accept frames w/ destination */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Additional bits to set in monitor mode.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * The packet filter bits.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Receive power-management frames and mgmt/ctrl/data frames.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Transmit Beacon Descriptor Start Address,
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 32b, 256-byte alignment
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_9346CR 0x50 /* 93c46/93c56 Command Register, 8b */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_9346CR_EEM_MASK BITS(7, 6) /* Operating Mode */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_9346CR_EEM_NORMAL LSHIFT(0, RTW_9346CR_EEM_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Load the EEPROM. Reset registers to defaults.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Takes ~2ms. RTL8180 indicates completion with RTW_9346CR_EEM_NORMAL.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * XXX RTL8180 only?
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_9346CR_EEM_AUTOLOAD LSHIFT(1, RTW_9346CR_EEM_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Disable network & bus-master operations and enable
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * _EECS, _EESK, _EEDI, _EEDO.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * XXX RTL8180 only?
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_9346CR_EEM_PROGRAM LSHIFT(2, RTW_9346CR_EEM_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql/* Enable RTW_CONFIG[0123] registers. */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_9346CR_EEM_CONFIG LSHIFT(3, RTW_9346CR_EEM_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * EEPROM pin status/control in _EEM_CONFIG, _EEM_AUTOLOAD modes.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * XXX RTL8180 only?
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_CONFIG0 0x51 /* Configuration Register 0, 8b */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * implements 40-bit WEP, XXX RTL8180 only?
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * implements 104-bit WEP, from EEPROM, read-only XXX RTL8180 only?
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 1: RTW_PSR_LEDGPO[01] control LED[01] pins.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 0: LED behavior defined by RTW_CONFIG1_LEDS10_MASK
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * XXX RTL8180 only?
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * auxiliary power is present, read-only
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Geographic Location, read-only
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * _RTW_CONFIG0_GL_* is what the datasheet says, but RTW_CONFIG0_GL_*
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define _RTW_CONFIG0_GL_USA LSHIFT(3, RTW_CONFIG0_GL_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_CONFIG0_GL_EUROPE LSHIFT(2, RTW_CONFIG0_GL_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_CONFIG0_GL_JAPAN LSHIFT(1, RTW_CONFIG0_GL_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * RTL8181 datasheet says RTW_CONFIG0_GL_JAPAN = 0.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_CONFIG1 0x52 /* Configuration Register 1, 8b */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * LED configuration. From EEPROM. Read/write.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Setting LED0 LED1
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * ------- ---- ----
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * RTW_CONFIG1_LEDS_ACT_INFRA Activity Infrastructure
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * RTW_CONFIG1_LEDS_ACT_LINK Activity Link
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * RTW_CONFIG1_LEDS_TX_RX Tx Rx
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * RTW_CONFIG1_LEDS_LINKACT_INFRA Link/Activity Infrastructure
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_CONFIG1_LEDS_ACT_INFRA LSHIFT(0, RTW_CONFIG1_LEDS_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_CONFIG1_LEDS_ACT_LINK LSHIFT(1, RTW_CONFIG1_LEDS_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_CONFIG1_LEDS_TX_RX LSHIFT(2, RTW_CONFIG1_LEDS_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_CONFIG1_LEDS_LINKACT_INFRA LSHIFT(3, RTW_CONFIG1_LEDS_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * LWAKE Output Signal. Only applicable to Cardbus. Pulse width is 150ms.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * RTW_CONFIG1_LWACT
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * RTW_CONFIG4_LWPTN 0 active high active low
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 1 positive pulse negative pulse
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_CONFIG1_MEMMAP BIT(3) /* using PCI memory space, read-only */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_CONFIG1_IOMAP BIT(2) /* using PCI I/O space, read-only */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * if set, VPD from offsets 0x40-0x7f in EEPROM are at
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * registers 0x60-0x67 of PCI Configuration Space ( XXX huh? )
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_CONFIG1_PMEN BIT(0) /* Power Management Enable: TBD */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_CONFIG2 0x53 /* Configuration Register 2, 8b */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * clocks are locked, read-only:
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Tx frequency & symbol clocks are derived from the same OSC
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_CONFIG2_ANT BIT(6) /* diversity enabled, read-only */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Descriptor Polling State: enable test mode.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_CONFIG2_PAPESIGN BIT(2) /* TBD, from EEPROM */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_CONFIG2_PAPETIME_MASK BITS(1, 0) /* TBD, from EEPROM */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * undocumented bits which appear to control the power state of the RF
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * components
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 1: disable Tx DAC,
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 0: enable
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * undocumented bits which appear to control the power state of the RF
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * components
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Maxim On/Sleep/Off control
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_ANAPARM_RFPOW_MAXIM_ON LSHIFT(0x8, RTW_ANAPARM_RFPOW1_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_ANAPARM_RFPOW_MAXIM_SLEEP LSHIFT(0x378, RTW_ANAPARM_RFPOW1_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_ANAPARM_RFPOW_MAXIM_OFF LSHIFT(0x379, RTW_ANAPARM_RFPOW1_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * RFMD On/Sleep/Off control
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_ANAPARM_RFPOW_RFMD_ON LSHIFT(0x408, RTW_ANAPARM_RFPOW1_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_ANAPARM_RFPOW_RFMD_SLEEP LSHIFT(0x378, RTW_ANAPARM_RFPOW1_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_ANAPARM_RFPOW_RFMD_OFF LSHIFT(0x379, RTW_ANAPARM_RFPOW1_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Philips On/Sleep/Off control
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF;
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_ANAPARM_RFPOW_PHILIPS_ON LSHIFT(0x328, RTW_ANAPARM_RFPOW1_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * undocumented card-specific bits from the EEPROM.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Network Type and Link Status
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * AP, XXX RTL8181 only?
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_MSR_NETYPE_AP_OK LSHIFT(3, RTW_MSR_NETYPE_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * infrastructure link ok
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_MSR_NETYPE_INFRA_OK LSHIFT(2, RTW_MSR_NETYPE_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * ad-hoc link ok
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_MSR_NETYPE_ADHOC_OK LSHIFT(1, RTW_MSR_NETYPE_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_MSR_NETYPE_NOLINK LSHIFT(0, RTW_MSR_NETYPE_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_CONFIG3 0x59 /* Configuration Register 3, 8b */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_CONFIG3_GNTSEL BIT(7) /* Grant Select, read-only */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Set RTW_CONFIG3_PARMEN and RTW_9346CR_EEM_CONFIG to
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * allow RTW_ANAPARM writes.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Valid when RTW_CONFIG1_PMEN is set. If set, RTL8180 wakes up
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * OS when Magic Packet is Rx'd.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Cardbus-related registers and functions are enabled,
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * read-only. XXX RTL8180 only.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * CLKRUN enabled, read-only. XXX RTL8180 only.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Function Registers Enabled, read-only. XXX RTL8180 only.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Fast back-to-back enabled, read-only.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_CONFIG4 0x5A /* Configuration Register 4, 8b */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * VCO Power Down
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 0: normal operation
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * (power-on default)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 1: power-down VCO, RF front-end,
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * and most RTL8180 components.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Power Off
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 0: normal operation
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * (power-on default)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 1: power-down RF front-end,
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * and most RTL8180 components,
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * but leave VCO on.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * XXX RFMD front-end only?
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Power Management
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 0: normal operation
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * (power-on default)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 1: set Tx packet's PWRMGMT bit.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * LANWAKE vs. PMEB: Cardbus-only
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 0: LWAKE & PMEB asserted
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * simultaneously
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 1: LWAKE asserted only if
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * both PMEB is asserted and
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * ISOLATEB is low.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * XXX RTL8180 only.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * see RTW_CONFIG1_LWACT XXX RTL8180 only.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Radio Front-End Programming Method
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_CONFIG4_RFTYPE_INTERSIL LSHIFT(1, RTW_CONFIG4_RFTYPE_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_CONFIG4_RFTYPE_RFMD LSHIFT(2, RTW_CONFIG4_RFTYPE_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_CONFIG4_RFTYPE_PHILIPS LSHIFT(3, RTW_CONFIG4_RFTYPE_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_PSR_GPO BIT(7) /* Control/status of pin 52. */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Status/control of LED1 pin if RTW_CONFIG0_LEDGPOEN is set.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Status/control of LED0 pin if RTW_CONFIG0_LEDGPOEN is set.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_PSR_UWF BIT(1) /* Enable Unicast Wakeup Frame */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_SCR 0x5f /* Security Configuration Register, 8b */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Enable Tx WEP. Invalid if neither RTW_CONFIG0_WEP40 nor
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * RTW_CONFIG0_WEP104 is set.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Enable Rx WEP. Invalid if neither RTW_CONFIG0_WEP40 nor
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * RTW_CONFIG0_WEP104 is set.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_BCNITV 0x70 /* Beacon Interval Register, 16b */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * TU between TBTT, written by host.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * ATIM Window length in TU, written by host.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_BINTRITV 0x74 /* Beacon Interrupt Interval Register, 16b */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * RTL8180 wakes host with RTW_INTR_BCNINT at BINTRITV
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * microseconds before TBTT
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_ATIMTRITV 0x76 /* ATIM Interrupt Interval Register, 16b */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * RTL8180 wakes host with RTW_INTR_ATIMINT at ATIMTRITV
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * microseconds before end of ATIM Window
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Rev. C magic from reference driver
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * microsecond Tx delay between MAC and RF front-end
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_CRC16ERR 0x7a /* CRC16 error count, 16b, XXX RTL8181 only? */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * used for writing RTL8180's integrated baseband processor
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_PHYADDR 0x7c /* Address register for PHY interface, 8b */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_PHYDATAW 0x7d /* Write data to PHY, 8b, write-only */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_PHYDATAR 0x7e /* Read data from PHY, 8b (?), read-only */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_PHYCFG 0x80 /* PHY Configuration Register, 32b */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * if !RTW_PHYCFG_HST, host sets. MAC clears after banging bits.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 1: host bangs bits
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 0: MAC bangs bits
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_PHYCFG_MAC_RFTYPE_INTERSIL LSHIFT(0, RTW_PHYCFG_MAC_RFTYPE_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_PHYCFG_MAC_RFTYPE_RFMD LSHIFT(1, RTW_PHYCFG_MAC_RFTYPE_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_PHYCFG_MAC_RFTYPE_GCT RTW_PHYCFG_MAC_RFTYPE_RFMD
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_PHYCFG_MAC_RFTYPE_PHILIPS LSHIFT(3, RTW_PHYCFG_MAC_RFTYPE_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 0x84 - 0xD3, page 1, selected when RTW_PSR[PSEN] == 1.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_WAKEUP0L 0x84 /* Power Management Wakeup Frame */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 0x84 - 0xD3, page 0, selected when RTW_PSR[PSEN] == 0.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Default Key Registers, each 128b
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * If RTW_SCR_KM_WEP104, 104 lsb are the key.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * If RTW_SCR_KM_WEP40, 40 lsb are the key.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_CONFIG5 0xd8 /* Configuration Register 5, 8b */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_CONFIG5_TXFIFOOK BIT(7) /* Tx FIFO self-test pass, read-only */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_CONFIG5_RXFIFOOK BIT(6) /* Rx FIFO self-test pass, read-only */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 1: start calibration cycle and raise AGCRESET pin.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 0: lower AGCRESET pin
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_CONFIG5_EACPI BIT(2) /* Enable ACPI Wake up, default 0 */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Enable LAN Wake signal, from EEPROM
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 1: both software & PCI Reset reset PME_Status
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 0: only software resets PME_Status
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * From EEPROM.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Transmit Priority Polling Register, 8b, write-only.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * RTL8180 clears to notify host of a beacon
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Tx. Host writes have no effect.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Host writes 1 to notify RTL8180 of high-priority Tx packets, RTL8180 clears
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * to after high-priority Tx is complete.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * If RTW_CONFIG2_DPS is set, host writes 1 to notify RTL8180 of
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * normal-priority Tx packets, RTL8180 clears
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * after normal-priority Tx is complete.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * If RTW_CONFIG2_DPS is clear, host writes have no effect. RTL8180 clears after
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * normal-priority Tx is complete.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Host writes 1 to notify RTL8180 of low-priority Tx packets, RTL8180 clears
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * after low-priority Tx is complete.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Host writes 1 to tell RTL8180 to stop beacon DMA. This bit is invalid
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * when RTW_CONFIG2_DPS is set.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Host writes 1 to tell RTL8180 to stop high-priority DMA.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Host writes 1 to tell RTL8180 to stop normal-priority DMA.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * This bit is invalid when RTW_CONFIG2_DPS is set.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Host writes 1 to tell RTL8180 to stop low-priority DMA.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql/* Start all queues. */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_TPPOLL_ALL (RTW_TPPOLL_BQ | RTW_TPPOLL_HPQ | \
a72f7ea693101cc48bafbb4db6bb437d828011c4ql/* Start queues solaris required. */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql/* Stop all queues. */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_TPPOLL_SALL (RTW_TPPOLL_SBQ | RTW_TPPOLL_SHPQ | \
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_CWR 0xdc /* Contention Window Register, 16b, read-only */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Contention Window: indicates number of contention windows before Tx
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Retry Count Register, 16b, read-only
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Retry Count: indicates number of retries after Tx
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Receive descriptor Start Address Register,
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 32b, 256-byte alignment.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Function Event Register, 32b, Cardbus only. Only valid when
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN are set.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_FER_INTR BIT(15) /* set when RTW_FFER_INTR is set */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Function Event Mask Register, 32b, Cardbus only. Only valid when
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN are set.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_FEMR_INTR BIT(15) /* set when RTW_FFER_INTR is set */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Function Present State Register, 32b, read-only, Cardbus only.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Only valid when both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * are set.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Function Force Event Register, 32b, write-only, Cardbus only.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Only valid when both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * are set.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Serial EEPROM offsets
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_SR_PMC 0x16 /* Power Management Capabilities, 16b */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_SR_CHANNELPLAN 0x2e /* bitmap of channels to scan */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_SR_ENERGYDETTHR 0x2f /* energy-detect threshold */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_SR_ENERGYDETTHR_DEFAULT 0x0c /* use this if old SROM */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_SR_RFPARM_DFLANTB BIT(1) /* 1: antenna B is default */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_SR_RFPARM_CS_MASK BITS(2, 3) /* carrier-sense type */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_SR_VERSION 0x3c /* EEPROM content version, 16b */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_SR_VPD 0x40 /* Vital Product Data, 64 bytes */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_SR_CIS 0x80 /* CIS Data, 93c56 only, 128 bytes */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * RTL8180 Transmit/Receive Descriptors
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * the first descriptor in each ring must be on a 256-byte boundary
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Tx descriptor
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_TXCTL0_RATE_1MBPS LSHIFT(0, RTW_TXCTL0_RATE_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_TXCTL0_RATE_2MBPS LSHIFT(1, RTW_TXCTL0_RATE_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_TXCTL0_RATE_5MBPS LSHIFT(2, RTW_TXCTL0_RATE_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_TXCTL0_RATE_11MBPS LSHIFT(3, RTW_TXCTL0_RATE_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_TXCTL0_RTSRATE_MASK BITS(22, 19) /* Tx rate */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_TXCTL0_RTSRATE_1MBPS LSHIFT(0, RTW_TXCTL0_RTSRATE_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_TXCTL0_RTSRATE_2MBPS LSHIFT(1, RTW_TXCTL0_RTSRATE_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_TXCTL0_RTSRATE_5MBPS LSHIFT(2, RTW_TXCTL0_RTSRATE_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_TXCTL0_RTSRATE_11MBPS LSHIFT(3, RTW_TXCTL0_RTSRATE_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_TXCTL0_BEACON BIT(18) /* packet is a beacon */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_TXCTL0_MOREFRAG BIT(17) /* another fragment follows */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * add short PLCP preamble and header
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_TXCTL0_KEYID_MASK BITS(15, 14) /* default key id */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Tx packet size in bytes
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_TXSTAT_RTSRETRY_MASK BITS(14, 8) /* RTS retry count */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_TXSTAT_DRC_MASK BITS(7, 0) /* Data retry count */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * supplements _LENGTH in packets sent 5.5Mb/s or faster
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_TXCTL1_LENGTH_MASK BITS(30, 16) /* PLCP length (microseconds) */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * RTS Duration (microseconds)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_TXLEN_LENGTH_MASK BITS(11, 0) /* Tx buffer length in bytes */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Rx descriptor
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define rd_tsftl rd_buf /* valid only when RTW_RXSTAT_LS is set */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define rd_tsfth rd_rsvd1 /* valid only when RTW_RXSTAT_LS is set */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_RXCTL_LENGTH_MASK BITS(11, 0) /* Rx buffer length */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_RXSTAT_DMAFAIL BIT(27) /* DMA failure on this pkt */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * buffer overflow XXX means FIFO exhausted?
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Rx'd with short preamble and PLCP header
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_RXSTAT_RATE_1MBPS LSHIFT(0, RTW_RXSTAT_RATE_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_RXSTAT_RATE_2MBPS LSHIFT(1, RTW_RXSTAT_RATE_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_RXSTAT_RATE_5MBPS LSHIFT(2, RTW_RXSTAT_RATE_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_RXSTAT_RATE_11MBPS LSHIFT(3, RTW_RXSTAT_RATE_MASK)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_RXSTAT_MIC BIT(19) /* XXX from reference driver */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_RXSTAT_PAR BIT(17) /* matches RTL8180's MAC */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * error summary. valid when RTW_RXSTAT_LS set. indicates
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * that either RTW_RXSTAT_CRC32 or RTW_RXSTAT_ICV is set.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_RXSTAT_PWRMGT BIT(14) /* 802.11 PWRMGMT bit is set */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * XXX CRC16 error, from reference driver
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * frame length, including CRC32
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Convenient status conjunction.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Convenient status disjunctions.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_RXSTAT_IOERROR (RTW_RXSTAT_DMAFAIL|RTW_RXSTAT_BOVF)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_RXSTAT_DEBUG (RTW_RXSTAT_SPLCP|RTW_RXSTAT_MAR|\
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_RXRSSI_VLAN BITS(32, 16) /* XXX from reference driver */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * for Philips RF front-ends
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_RXRSSI_RSSI BITS(15, 8) /* RF energy at the PHY */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * for RF front-ends by Intersil, Maxim, RFMD
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_RXRSSI_IMR_RSSI BITS(15, 9) /* RF energy at the PHY */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_RXRSSI_SQ BITS(7, 0) /* Barker code-lock quality */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_WRITE((regs), (reg), RTW_READ((regs), (reg)) & ~(mask))
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * bus_space(9) lied?
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define BUS_SPACE_BARRIER_SYNC (BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define BUS_SPACE_BARRIER_READ_BEFORE_READ BUS_SPACE_BARRIER_READ
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define BUS_SPACE_BARRIER_READ_BEFORE_WRITE BUS_SPACE_BARRIER_READ
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define BUS_SPACE_BARRIER_WRITE_BEFORE_READ BUS_SPACE_BARRIER_WRITE
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE BUS_SPACE_BARRIER_WRITE
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Bus barrier
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Complete outstanding read and/or write ops on [reg0, reg1]
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * ([reg1, reg0]) before starting new ops on the same region. See
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * acceptable bus_space_barrier(9) for the flag definitions.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * ***just define a dummy macro here in solaris***
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * bus_space_barrier((regs)->r_bh, (regs)->r_bt, \
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * MIN(reg0, reg1), MAX(reg0, reg1) - MIN(reg0, reg1) + 4, flags)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Barrier convenience macros.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * write-before-write
a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * write-before-read
a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_READ)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * read-before-read
a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_READ_BEFORE_READ)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * read-before-read
a72f7ea693101cc48bafbb4db6bb437d828011c4ql RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_READ_BEFORE_WRITE)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * Registers for RTL8180L's built-in baseband modem.
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_BBP_TXAGC 0x03 /* guess: transmit auto gain control */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * guess: low-noise amplifier activation threshold
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * guess: intermediate frequency (IF)
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * auto-gain control (AGC) initial value
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_BBP_IFAGCLIMIT 0x06 /* guess: IF AGC maximum value */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * guess: activation threshold for IF AGC loop
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_BBP_ANTATTEN 0x10 /* guess: antenna & attenuation */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * guess: transmit/receive switch latency
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#define RTW_BBP_SYS2_ANTDIV 0x80 /* enable antenna diversity */
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * loopback rate?
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 0: 1Mbps
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 1: 2Mbps
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 2: 5.5Mbps
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * 3: 11Mbps
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * carrier-sense threshold
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * guess: channel energy-detect threshold
a72f7ea693101cc48bafbb4db6bb437d828011c4ql * guess: channel signal-quality threshold
a72f7ea693101cc48bafbb4db6bb437d828011c4ql#endif /* _RTW_REG_H_ */