cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * CDDL HEADER START
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * The contents of this file are subject to the terms of the
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Common Development and Distribution License (the "License").
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * You may not use this file except in compliance with the License.
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * or http://www.opensolaris.org/os/licensing.
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * See the License for the specific language governing permissions
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * and limitations under the License.
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * When distributing Covered Code, include this CDDL HEADER in each
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * If applicable, add the following below this CDDL HEADER, with the
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * fields enclosed by brackets "[]" replaced with your own identifying
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * information: Portions Copyright [yyyy] [name of copyright owner]
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * CDDL HEADER END
ace3c3ff753a94432e3a936c2931b81a66cd03d1Venugopal Iyer * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
2c6a6ad1e812de6043502f2f52d21711033ab43eIlya Yanok * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * rtls -- REALTEK 8139-serials PCI Fast Ethernet Driver, Depends on the
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Generic LAN Driver utility functions in /kernel/misc/mac
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * This product is covered by one or more of the following patents:
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * US5,307,459, US5,434,872, US5,732,094, US6,570,884, US6,115,776, and
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * US6,327,625.
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Currently supports:
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Declarations and Module Linkage
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * This is the string displayed by modinfo, etc.
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amorestatic char rtls_ident[] = "RealTek 8139 Ethernet driver";
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Required system entry points
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amorestatic int rtls_attach(dev_info_t *, ddi_attach_cmd_t);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amorestatic int rtls_detach(dev_info_t *, ddi_detach_cmd_t);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Required driver entry points for MAC
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amorestatic int rtls_m_start(void *);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amorestatic void rtls_m_stop(void *);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amorestatic int rtls_m_unicst(void *, const uint8_t *);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amorestatic int rtls_m_multicst(void *, boolean_t, const uint8_t *);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amorestatic int rtls_m_promisc(void *, boolean_t);
ace3c3ff753a94432e3a936c2931b81a66cd03d1Venugopal Iyerstatic int rtls_m_getprop(void *, const char *, mac_prop_id_t, uint_t,
ace3c3ff753a94432e3a936c2931b81a66cd03d1Venugopal Iyerstatic int rtls_m_setprop(void *, const char *, mac_prop_id_t, uint_t,
ace3c3ff753a94432e3a936c2931b81a66cd03d1Venugopal Iyer const void *);
ace3c3ff753a94432e3a936c2931b81a66cd03d1Venugopal Iyerstatic void rtls_m_propinfo(void *, const char *, mac_prop_id_t,
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amorestatic int rtls_m_stat(void *, uint_t, uint64_t *);
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore * MII entry points
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amorestatic uint16_t rtls_mii_read(void *, uint8_t, uint8_t);
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amorestatic void rtls_mii_write(void *, uint8_t, uint8_t, uint16_t);
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amorestatic void rtls_mii_notify(void *, link_state_t);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Internal functions used by the above entry points
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amorestatic int rtls_chip_reset(rtls_t *, boolean_t);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amorestatic void rtls_chip_restart(rtls_t *rtlsp);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amorestatic void rtls_get_mac_addr(rtls_t *, uint8_t *);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amorestatic void rtls_set_mac_addr(rtls_t *, const uint8_t *);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amorestatic uint_t rtls_hash_index(const uint8_t *);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amorestatic boolean_t rtls_send(rtls_t *, mblk_t *);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Buffer Management Routines
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amorestatic int rtls_alloc_dma_mem(rtls_t *, size_t, ddi_device_acc_attr_t *,
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amorestatic void rtls_reg_print(rtls_t *); /* debug routine */
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Used for buffers allocated by ddi_dma_mem_alloc()
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore 0, /* dma_attr_addr_lo */
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore 0, /* dma_attr_flags */
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * PIO access attributes for registers
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amorestatic ddi_device_acc_attr_t rtls_reg_accattr = {
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * DMA access attributes for data
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amorestatic ddi_device_acc_attr_t rtls_buf_accattr = {
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'AmoreDDI_DEFINE_STREAM_OPS(rtls_dev_ops, nulldev, nulldev, rtls_attach, rtls_detach,
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Standard module linkage initialization for a MAC driver
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore &mod_driverops, /* type of module. This one is a driver */
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * ========== RealTek chip register access Routines ==========
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amorestatic uint8_t rtls_reg_get8(rtls_t *rtlsp, uint32_t reg);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amorestatic uint16_t rtls_reg_get16(rtls_t *rtlsp, uint32_t reg);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amorestatic uint32_t rtls_reg_get32(rtls_t *rtlsp, uint32_t reg);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amorestatic void rtls_reg_set8(rtls_t *rtlsp, uint32_t reg, uint8_t value);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amorertls_reg_set8(rtls_t *rtlsp, uint32_t reg, uint8_t value)
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amorestatic void rtls_reg_set16(rtls_t *rtlsp, uint32_t reg, uint16_t value);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amorertls_reg_set16(rtls_t *rtlsp, uint32_t reg, uint16_t value)
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amorestatic void rtls_reg_set32(rtls_t *rtlsp, uint32_t reg, uint32_t value);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amorertls_reg_set32(rtls_t *rtlsp, uint32_t reg, uint32_t value)
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * ========== Module Loading Entry Points ==========
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore mac_init_ops(&rtls_dev_ops, RTLS_DRIVER_NAME);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore if ((rv = mod_install(&modlinkage)) != DDI_SUCCESS) {
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore if ((rv = mod_remove(&modlinkage)) == DDI_SUCCESS) {
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * ========== DDI Entry Points ==========
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * attach(9E) -- Attach a device to the system
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Called once for each board successfully probed.
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amorertls_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd)
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore rtls_t *rtlsp; /* Our private device info */
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore if ((rtlsp = ddi_get_driver_private(devinfo)) == NULL) {
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Turn on Master Enable (DMA) and IO Enable bits.
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Enable PCI Memory Space accesses
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Disable Memory Write/Invalidate
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore if (pci_config_setup(devinfo, &pci_handle) != DDI_SUCCESS) {
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore pci_commond = pci_config_get16(pci_handle, PCI_CONF_COMM);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore pci_commond |= PCI_COMM_ME | PCI_COMM_MAE | PCI_COMM_IO;
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore pci_config_put32(pci_handle, PCI_CONF_COMM, pci_commond);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * we don't support high level interrupts in the driver
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore cmn_err(CE_WARN, "unsupported high level interrupt");
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Get handle to access pci configuration space
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore if (pci_config_setup(devinfo, &pci_handle) != DDI_SUCCESS) {
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Make sure we support this particular vendor/device
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore vendorid = pci_config_get16(pci_handle, PCI_CONF_VENID);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore deviceid = pci_config_get16(pci_handle, PCI_CONF_DEVID);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore device = (device << 16) | deviceid; /* combine two id together */
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * See if we support this device
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * We do not return for wrong device id. It's user risk.
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore "RTLS doesn't support this device: "
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore "vendorID = 0x%x, deviceID = 0x%x",
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Turn on Master Enable (DMA) and IO Enable bits.
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Enable PCI Memory Space accesses
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Disable Memory Write/Invalidate
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore pci_commond = pci_config_get16(pci_handle, PCI_CONF_COMM);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore pci_commond |= PCI_COMM_ME | PCI_COMM_MAE | PCI_COMM_IO;
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore pci_config_put32(pci_handle, PCI_CONF_COMM, pci_commond);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Free handle to access pci configuration space
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore rtlsp = kmem_zalloc(sizeof (rtls_t), KM_SLEEP);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore rtlsp->instance = ddi_get_instance(devinfo);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Map operating register
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore err = ddi_regs_map_setup(devinfo, 1, &rtlsp->io_reg,
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore (offset_t)0, 0, &rtls_reg_accattr, &rtlsp->io_handle);
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore cmn_err(CE_WARN, "ddi_regs_map_setup fail.");
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Allocate the TX and RX descriptors/buffers
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore if (rtls_alloc_bufs(rtlsp) == DDI_FAILURE) {
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore cmn_err(CE_WARN, "DMA buffer allocation fail.");
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Reset the chip
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Init rtls_t structure
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Add the interrupt handler
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * This will prevent receiving interrupts before device is ready, as
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * we are initializing device after setting the interrupts. So we
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * will not get our interrupt handler invoked by OS while our device
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * is still coming up or timer routines will not start till we are
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * all set to process...
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore if (ddi_add_intr(devinfo, 0, &rtlsp->iblk, NULL, rtls_intr,
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore if ((rtlsp->mii = mii_alloc(rtlsp, devinfo, &rtls_mii_ops)) == NULL) {
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore * Note: Some models of 8139 can support pause, but we have
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore * not implemented support for it at this time. This might be
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore * an interesting feature to add later.
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore mii_set_pauseable(rtlsp->mii, B_FALSE, B_FALSE);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore if ((macp = mac_alloc(MAC_VERSION)) == NULL) {
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore mutex_init(&rtlsp->rtls_io_lock, NULL, MUTEX_DRIVER, rtlsp->iblk);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore mutex_init(&rtlsp->rtls_tx_lock, NULL, MUTEX_DRIVER, rtlsp->iblk);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore mutex_init(&rtlsp->rtls_rx_lock, NULL, MUTEX_DRIVER, rtlsp->iblk);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Initialize pointers to device specific functions which will be
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * used by the generic layer.
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore macp->m_type_ident = MAC_PLUGIN_IDENT_ETHER;
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * detach(9E) -- Detach a device from the system
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amorertls_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd)
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore rtls_t *rtlsp; /* our private device info */
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Get the driver private structure
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore if ((rtlsp = ddi_get_driver_private(devinfo)) == NULL) {
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore /* device busy */
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * quiesce(9E) entry point.
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * This function is called when the system is single-threaded at high
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * PIL with preemption disabled. Therefore, this function must not be
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure.
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * DDI_FAILURE indicates an error condition and should almost never happen.
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore rtls_t *rtlsp; /* our private device info */
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Get the driver private structure
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore if ((rtlsp = ddi_get_driver_private(devinfo)) == NULL) {
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * ========== MAC Entry Points ==========
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * rtls_m_start() -- start the board receiving and allow transmits
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * rtls_m_stop() -- stop board receiving and transmits
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * rtls_m_unicst() -- set the physical network address
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * on the board
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amorertls_m_unicst(void *arg, const uint8_t *macaddr)
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * rtls_m_multicst() -- set(enable) or disable a multicast address
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Program the hardware to enable/disable the multicast address in "mcast".
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amorertls_m_multicst(void *arg, boolean_t enable, const uint8_t *mcast)
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore /* index value is between 0 and 63 */
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Set multicast register
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore rtls_reg_set32(rtlsp, MULTICAST_0_REG, hashp[0]);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore rtls_reg_set32(rtlsp, MULTICAST_4_REG, hashp[1]);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * rtls_hash_index() -- a hashing function used for setting the
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * node address or a multicast address
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore for (bytes = 0; bytes < ETHERADDRL; bytes++) {
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * rtls_m_promisc() -- set or reset promiscuous mode on the board
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore uint32_t val32 = rtls_reg_get32(rtlsp, RX_CONFIG_REG);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore rtls_reg_set32(rtlsp, RX_CONFIG_REG, val32);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * rtls_m_stat() -- retrieve statistic
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * MAC calls this routine just before it reads the driver's statistics
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * structure. If your board maintains statistics, this is the time to
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * read them in and update the values in the structure. If the driver
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * maintains statistics continuously, this routine need do nothing.
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amorertls_m_stat(void *arg, uint_t stat, uint64_t *val)
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore if (mii_m_getstat(rtlsp->mii, stat, val) == 0) {
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * RTL8139 don't support MII statistics,
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * these values are maintained by the driver software.
ace3c3ff753a94432e3a936c2931b81a66cd03d1Venugopal Iyerrtls_m_getprop(void *arg, const char *name, mac_prop_id_t num, uint_t sz,
ace3c3ff753a94432e3a936c2931b81a66cd03d1Venugopal Iyer return (mii_m_getprop(rtlsp->mii, name, num, sz, val));
ace3c3ff753a94432e3a936c2931b81a66cd03d1Venugopal Iyerrtls_m_setprop(void *arg, const char *name, mac_prop_id_t num, uint_t sz,
ace3c3ff753a94432e3a936c2931b81a66cd03d1Venugopal Iyer return (mii_m_setprop(rtlsp->mii, name, num, sz, val));
ace3c3ff753a94432e3a936c2931b81a66cd03d1Venugopal Iyerrtls_m_propinfo(void *arg, const char *name, mac_prop_id_t num,
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * rtls_send() -- send a packet
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Called when a packet is ready to be transmitted. A pointer to an
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * M_DATA message that contains the packet is passed to this routine.
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * The complete LLC header is contained in the message's first message
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * block, and the remainder of the packet is contained within
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * additional M_DATA message blocks linked to the first message block.
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Returns B_TRUE if the packet was properly disposed of, or B_FALSE if
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * if the packet is being deferred and should be tried again later.
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * If chip error ...
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore "%s: send fail--CHIP ERROR!",
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore * If chip link down ... Note that experimentation shows that
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore * the device seems not to care about whether or not we have
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore * this check, but if we don't add the check here, it might
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore * not be properly reported as a carrier error.
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore if (rtls_reg_get8(rtlsp, MEDIA_STATUS_REG) & MEDIA_STATUS_LINK) {
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore "%s: send fail--LINK DOWN!",
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Current transmit descriptor
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * RealTek 8139 has 4 tx descriptor for transmit. In the first tx loop
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * of transmit,we needn't judge transmit status.
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore if (rtlsp->tx_first_loop < RTLS_MAX_TX_DESC) {
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * If it's not the first tx loop, we need judge whether the chip is
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * busy or not. Otherwise, we have to reschedule send and wait...
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore tx_status = rtls_reg_get32(rtlsp, TX_STATUS_DESC0_REG + 4 * cur_desc);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * H/W doesn't complete packet transmit
2c6a6ad1e812de6043502f2f52d21711033ab43eIlya Yanok "%s: rtls_send: need_sched", mac_name(rtlsp->mh));
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Through test, we find RTL8139 tx status might be
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * not-completing all along. We have to reset chip
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * to make RTL8139 tansmit re-work.
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore if (rtlsp->tx_retry++ > RTLS_TX_RETRY_NUM) {
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Wait transmit h/w more time...
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Judge tx status again, if it remains not-completing,
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * we can confirm RTL8139 is in chip error state
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * and must reset it.
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore cmn_err(CE_NOTE, "%s: tx chip_error = 0x%x",
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Transmit error?
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore cmn_err(CE_NOTE, "%s: transmit error, status = 0x%x",
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore ncc = ((tx_status & TX_STATUS_NCC) >> TX_STATUS_NCC_SHIFT);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Initialize variable
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Copy packet to tx descriptor buffer
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore if (totlen > (ETHERMAX + 4)) { /* 4 bytes for VLAN header */
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore "%s: rtls_send: try to send large %d packet",
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore /* this will free the mblk */
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore /* update stats */
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore uint16_t *ptr = (void *)rtlsp->tx_buf[cur_desc];
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore bzero(rtlsp->tx_buf[cur_desc] + totlen, ETHERMIN - totlen);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore /* make sure caches are flushed */
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore (void) ddi_dma_sync(rtlsp->dma_area_tx[cur_desc].dma_hdl, 0, totlen,
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Start transmit
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * set transmit FIFO threshhold to 0x30*32 = 1536 bytes
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * to avoid tx underrun.
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore rtls_reg_set32(rtlsp, TX_STATUS_DESC0_REG + 4 * cur_desc,
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore totlen | (0x30 << TX_STATUS_TX_THRESHOLD_SHIFT));
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Update the value of current tx descriptor
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * rtls_m_tx() -- send a chain of packets, linked by mp->b_next.
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * rtls_receive() -- receive packets
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Called when receive interrupts detected
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore while ((rtls_reg_get8(rtlsp, RT_COMMAND_REG)
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Chip error state
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore "%s: receive fail--CHIP ERROR!",
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore packet_len = (rx_ptr[3] << 8) | (rx_ptr[2]);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * DMA still in progress
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore cmn_err(CE_NOTE, "%s: Rx DMA still in progress",
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Check receive status
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore (packet_len > (ETHERMAX + ETHERFCSL + 4))) {
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore "%s: receive error, status = 0x%x, length = %d",
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Rx error statistics
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore else if (packet_len > (ETHERMAX + ETHERFCSL + 4))
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Set chip_error flag to reset chip:
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * (suggested in RealTek programming guide.)
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * We need not up-send ETHERFCSL bytes of receive packet
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Allocate buffer to receive this good packet
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Copy the data found into the new cluster, we have (+4)
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * to get us past the packet head data that the rtl chip
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * places at the start of the message
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore wrap_size = cur_rx + packet_len + RX_HEADER_SIZE
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore "%s: Rx: packet_len = %d, wrap_size = %d",
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore /* Flush caches */
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore (void) ddi_dma_sync(rtlsp->dma_area_rx.dma_hdl,
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore (void) ddi_dma_sync(rtlsp->dma_area_rx.dma_hdl,
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Copy in first section of message as stored
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * at the end of the ring buffer
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore bcopy(rtlsp->rx_ring, mp->b_wptr, wrap_size);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore cur_rx = RTLS_RX_ADDR_ALIGNED(wrap_size + ETHERFCSL);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore /* 4-byte aligned */
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore /* Flush caches */
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore (void) ddi_dma_sync(rtlsp->dma_area_rx.dma_hdl,
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore cur_rx += packet_len + RX_HEADER_SIZE + ETHERFCSL;
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore /* 4-byte aligned */
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Update rx buffer ring read pointer:
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * give us a little leeway to ensure no overflow
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore rtls_reg_set16(rtlsp, RX_CURRENT_READ_ADDR_REG,
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Upsend packet
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * rtls_intr() -- interrupt from board to inform us that a receive or
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * link change.
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Was this interrupt caused by our device...
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore int_status = rtls_reg_get16(rtlsp, RT_INT_STATUS_REG);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore /* indicate it wasn't our interrupt */
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Clear interrupt
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore rtls_reg_set16(rtlsp, RT_INT_STATUS_REG, int_status);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * If chip error, restart chip...
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore /* no need to hand other interrupts */
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Transmit error interrupt
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore val32 = rtls_reg_get32(rtlsp, TX_CONFIG_REG);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore rtls_reg_set32(rtlsp, TX_CONFIG_REG, val32);
2c6a6ad1e812de6043502f2f52d21711033ab43eIlya Yanok cmn_err(CE_WARN, "%s: transmit abort!!!", mac_name(rtlsp->mh));
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Trigger mac_tx_update
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Receive interrupt
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore * Link change interrupt.
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore return (DDI_INTR_CLAIMED); /* indicate it was our interrupt */
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * ========== Buffer Management Routines ==========
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * rtls_alloc_dma_mem() -- allocate an area of memory and a DMA handle
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * for accessing it
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amorertls_alloc_dma_mem(rtls_t *rtlsp, size_t memsize,
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore ddi_device_acc_attr_t *attr_p, uint_t dma_flags, dma_area_t *dma_p)
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Allocate handle
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore err = ddi_dma_alloc_handle(rtlsp->devinfo, &dma_attr,
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore "%s: rtls_alloc_dma_mem: ddi_dma_alloc_handle failed: %d",
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Allocate memory
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore err = ddi_dma_mem_alloc(dma_p->dma_hdl, memsize, attr_p,
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore dma_flags & (DDI_DMA_CONSISTENT | DDI_DMA_STREAMING),
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore DDI_DMA_SLEEP, NULL, &vaddr, &dma_p->alength, &dma_p->acc_hdl);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore "%s: rtls_alloc_dma_mem: ddi_dma_mem_alloc failed: %d",
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Bind the two together
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore err = ddi_dma_addr_bind_handle(dma_p->dma_hdl, NULL,
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore vaddr, dma_p->alength, dma_flags, DDI_DMA_SLEEP, NULL,
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore if (err != DDI_DMA_MAPPED || dma_p->ncookies != 1) {
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore "%s: rtls_alloc_dma_mem: "
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore "ddi_dma_addr_bind_handle failed: %d",
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * rtls_free_dma_mem() -- free one allocated area of DMAable memory
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore (void) ddi_dma_unbind_handle(dma_p->dma_hdl);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * rtls_alloc_bufs() -- allocate descriptors/buffers for this device instance
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Allocate memory & handle for Tx buffers
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore for (i = 0; i < RTLS_MAX_TX_DESC; i++) {
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore rtlsp->tx_buf[i] = (uint8_t *)rtlsp->dma_area_tx[i].mem_va;
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Allocate memory & handle for Rx buffers
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore rtlsp->rx_ring = (uint8_t *)rtlsp->dma_area_rx.mem_va;
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * rtls_free_bufs() -- free descriptors/buffers allocated for this
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * device instance.
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore for (i = 0; i < RTLS_MAX_TX_DESC; i++) {
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * ========== Chip H/W Operation Routines ==========
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * rtls_chip_reset() -- reset chip
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amorertls_chip_reset(rtls_t *rtlsp, boolean_t quiesce)
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Chip should be in STOP state
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore val8 &= ~(RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Disable interrupt
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore val16 = rtls_reg_get16(rtlsp, RT_INT_MASK_REG);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore rtls_reg_set16(rtlsp, RT_INT_MASK_REG, val16 & (~RTLS_INT_MASK_ALL));
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Clear pended interrupt
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore val16 = rtls_reg_get16(rtlsp, RT_INT_STATUS_REG);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore rtls_reg_set16(rtlsp, RT_INT_STATUS_REG, val16);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore rtls_reg_set8(rtlsp, RT_COMMAND_REG, val8 | RT_COMMAND_RESET);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Wait for reset success
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore while (rtls_reg_get8(rtlsp, RT_COMMAND_REG) & RT_COMMAND_RESET) {
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * At quiesce path we can't call cmn_err(), as
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * it might block
2c6a6ad1e812de6043502f2f52d21711033ab43eIlya Yanok "%s: chip reset fail.",
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * rtls_chip_init() -- initialize the specified network board short of
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * actually starting the board. Call after rtls_chip_reset().
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Initialize internal data structures
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Set DMA physical rx/tx buffer address to register
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore (ulong_t)rtlsp->dma_area_rx.cookie.dmac_address);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore (ulong_t)rtlsp->dma_area_tx[0].cookie.dmac_address);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore (ulong_t)rtlsp->dma_area_tx[1].cookie.dmac_address);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore (ulong_t)rtlsp->dma_area_tx[2].cookie.dmac_address);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore (ulong_t)rtlsp->dma_area_tx[3].cookie.dmac_address);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Start transmit/receive before set tx/rx configuration register
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore val8 | RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Set transmit configuration register
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore val32 = rtls_reg_get32(rtlsp, TX_CONFIG_REG);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore rtls_reg_set32(rtlsp, TX_CONFIG_REG, val32 | TX_CONFIG_DEFAULT);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Set receive configuration register
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore val32 = rtls_reg_get32(rtlsp, RX_CONFIG_REG);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore rtls_reg_set32(rtlsp, RX_CONFIG_REG, val32 | RX_CONFIG_DEFAULT);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Set multicast register
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore rtls_reg_set32(rtlsp, MULTICAST_0_REG, rtlsp->multi_hash[0]);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore rtls_reg_set32(rtlsp, MULTICAST_4_REG, rtlsp->multi_hash[1]);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Set unicast address
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Set current address of packet read
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore rtls_reg_set16(rtlsp, RX_CURRENT_READ_ADDR_REG, RX_READ_RESET_VAL);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * No early-rx interrupts
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore val16 = rtls_reg_get16(rtlsp, RT_MUL_INTSEL_REG);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore rtls_reg_set16(rtlsp, RT_MUL_INTSEL_REG, val16);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * rtls_chip_start() -- start chip
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore val8 | RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Enable interrupt
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore val16 = rtls_reg_get16(rtlsp, RT_INT_MASK_REG);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore rtls_reg_set16(rtlsp, RT_INT_MASK_REG, val16 | RTLS_INT_MASK);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * rtls_chip_restart() -- restart chip
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * rtls_chip_stop() -- stop board receiving
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Disable interrupt
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore val16 = rtls_reg_get16(rtlsp, RT_INT_MASK_REG);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore rtls_reg_set16(rtlsp, RT_INT_MASK_REG, val16 & (~RTLS_INT_MASK_ALL));
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Clear pended interrupt
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore val16 = rtls_reg_get16(rtlsp, RT_INT_STATUS_REG);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore rtls_reg_set16(rtlsp, RT_INT_STATUS_REG, val16);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Stop the board and disable transmit/receive
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore val8 &= ~(RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * rtls_get_mac_addr() -- get the physical network address on the board
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amorertls_get_mac_addr(rtls_t *rtlsp, uint8_t *macaddr)
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Read first 4-byte of mac address
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Read last 2-byte of mac address
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amorertls_set_mac_addr(rtls_t *rtlsp, const uint8_t *macaddr)
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Change to config register write enable mode
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore val8 = rtls_reg_get8(rtlsp, RT_93c46_COMMAND_REG);
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore rtls_reg_set8(rtlsp, RT_93c46_COMMAND_REG, val8);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Get first 4 bytes of mac address
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Set first 4 bytes of mac address
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Get last 2 bytes of mac address
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Set last 2 bytes of mac address
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore val32 |= rtls_reg_get32(rtlsp, ID_4_REG) & ~0xffff;
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * Return to normal network/host communication mode
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore rtls_reg_set8(rtlsp, RT_93c46_COMMAND_REG, val8);
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amorertls_mii_read(void *arg, uint8_t phy, uint8_t reg)
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore return (0xffff);
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore val = rtls_reg_get16(rtlsp, BASIC_MODE_CONTROL_REG);
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore val = rtls_reg_get16(rtlsp, BASIC_MODE_STATUS_REG);
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore val = rtls_reg_get16(rtlsp, AUTO_NEGO_AD_REG);
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore val = rtls_reg_get16(rtlsp, AUTO_NEGO_LP_REG);
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore val = rtls_reg_get16(rtlsp, AUTO_NEGO_EXP_REG);
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore * We "simulate" a vendor private register so that the
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore * PHY layer can access it to determine detected link
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore val = rtls_reg_get8(rtlsp, MEDIA_STATUS_REG);
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amorertls_mii_write(void *arg, uint8_t phy, uint8_t reg, uint16_t val)
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore /* Enable writes to all bits of BMCR */
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore val8 = rtls_reg_get8(rtlsp, RT_93c46_COMMAND_REG);
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore rtls_reg_set8(rtlsp, RT_93c46_COMMAND_REG, val8);
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore /* write out the value */
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore rtls_reg_set16(rtlsp, BASIC_MODE_CONTROL_REG, val);
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore /* Return to normal network/host communication mode */
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore rtls_reg_set8(rtlsp, RT_93c46_COMMAND_REG, val8);
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore rtls_reg_set16(rtlsp, BASIC_MODE_STATUS_REG, val);
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore rtls_reg_set16(rtlsp, AUTO_NEGO_AD_REG, val);
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore rtls_reg_set16(rtlsp, AUTO_NEGO_LP_REG, val);
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore rtls_reg_set16(rtlsp, AUTO_NEGO_EXP_REG, val);
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore /* these are not writable */
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amorertls_mii_notify(void *arg, link_state_t link)
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore * rtls_reg_print() -- print out reg value(for debug use only)
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore cmn_err(CE_NOTE, "%s: RT_COMMAND_REG = 0x%x",
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore val16 = rtls_reg_get16(rtlsp, RT_INT_STATUS_REG);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore cmn_err(CE_NOTE, "%s: RT_INT_STATUS_REG = 0x%x",
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore val16 = rtls_reg_get16(rtlsp, RT_INT_MASK_REG);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore cmn_err(CE_NOTE, "%s: RT_INT_MASK_REG = 0x%x",
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore val32 = rtls_reg_get32(rtlsp, RX_CONFIG_REG);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore cmn_err(CE_NOTE, "%s: RX_CONFIG_REG = 0x%x",
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore val16 = rtls_reg_get16(rtlsp, TX_DESC_STAUS_REG);
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore cmn_err(CE_NOTE, "%s: TX_DESC_STAUS_REG = 0x%x, cur_desc = %d",
2c6a6ad1e812de6043502f2f52d21711033ab43eIlya Yanok mac_name(rtlsp->mh), val16, rtlsp->tx_current_desc);
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore val32 = rtls_reg_get32(rtlsp, TX_STATUS_DESC0_REG);
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore cmn_err(CE_NOTE, "%s: TX_STATUS_DESC0_REG = 0x%x",
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore val32 = rtls_reg_get32(rtlsp, TX_STATUS_DESC1_REG);
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore cmn_err(CE_NOTE, "%s: TX_STATUS_DESC1_REG = 0x%x",
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore val32 = rtls_reg_get32(rtlsp, TX_STATUS_DESC2_REG);
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore cmn_err(CE_NOTE, "%s: TX_STATUS_DESC2_REG = 0x%x",
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore val32 = rtls_reg_get32(rtlsp, TX_STATUS_DESC3_REG);
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore cmn_err(CE_NOTE, "%s: TX_STATUS_DESC3_REG = 0x%x",
bbb1277b6ec1b0daad4e3ed1a2b891d3e2ece2ebGarrett D'Amore cmn_err(CE_NOTE, "%s: in = %llu, multicast = %llu, broadcast = %llu",
cde2885fdf538266ee2a3b08dee2d5075ce8fa2bGarrett D'Amore (unsigned long long)rtlsp->stats.brdcst_rcv);