rge_chip.c revision c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * CDDL HEADER START
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c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
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c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * CDDL HEADER END
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Copyright 2005 Sun Microsystems, Inc. All rights reserved.
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Use is subject to license terms.
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs#pragma ident "%Z%%M% %I% %E% SMI"
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs#define REG32(rgep, reg) ((uint32_t *)(rgep->io_regs+(reg)))
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs#define REG16(rgep, reg) ((uint16_t *)(rgep->io_regs+(reg)))
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs#define REG8(rgep, reg) ((uint8_t *)(rgep->io_regs+(reg)))
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs#define PIO_ADDR(rgep, offset) ((void *)(rgep->io_regs+(offset)))
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Patchable globals:
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * rge_autorecover
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Enables/disables automatic recovery after fault detection
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * globals:
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs#define RGE_DBG RGE_DBG_REGS /* debug flag for this code */
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Operating register get/set access routines
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs pcistatus = pci_config_get16(rgep->cfg_handle, PCI_CONF_STAT);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0)
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs#endif /* RGE_DEBUGGING */
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic uint32_t rge_reg_get32(rge_t *rgep, uintptr_t regno);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs#pragma inline(rge_reg_get32)
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void rge_reg_put32(rge_t *rgep, uintptr_t regno, uint32_t data);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs#pragma inline(rge_reg_put32)
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsrge_reg_put32(rge_t *rgep, uintptr_t regno, uint32_t data)
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void rge_reg_set32(rge_t *rgep, uintptr_t regno, uint32_t bits);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs#pragma inline(rge_reg_set32)
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsrge_reg_set32(rge_t *rgep, uintptr_t regno, uint32_t bits)
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void rge_reg_clr32(rge_t *rgep, uintptr_t regno, uint32_t bits);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs#pragma inline(rge_reg_clr32)
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsrge_reg_clr32(rge_t *rgep, uintptr_t regno, uint32_t bits)
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic uint16_t rge_reg_get16(rge_t *rgep, uintptr_t regno);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs#pragma inline(rge_reg_get16)
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void rge_reg_put16(rge_t *rgep, uintptr_t regno, uint16_t data);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs#pragma inline(rge_reg_put16)
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsrge_reg_put16(rge_t *rgep, uintptr_t regno, uint16_t data)
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void rge_reg_set16(rge_t *rgep, uintptr_t regno, uint16_t bits);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs#pragma inline(rge_reg_set16)
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsrge_reg_set16(rge_t *rgep, uintptr_t regno, uint16_t bits)
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void rge_reg_clr16(rge_t *rgep, uintptr_t regno, uint16_t bits);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs#pragma inline(rge_reg_clr16)
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsrge_reg_clr16(rge_t *rgep, uintptr_t regno, uint16_t bits)
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic uint8_t rge_reg_get8(rge_t *rgep, uintptr_t regno);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs#pragma inline(rge_reg_get8)
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void rge_reg_put8(rge_t *rgep, uintptr_t regno, uint8_t data);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs#pragma inline(rge_reg_put8)
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void rge_reg_set8(rge_t *rgep, uintptr_t regno, uint8_t bits);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs#pragma inline(rge_reg_set8)
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void rge_reg_clr8(rge_t *rgep, uintptr_t regno, uint8_t bits);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs#pragma inline(rge_reg_clr8)
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Waiting for PHY reading OK
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs for (i = 0; i < PHY_RESET_LOOP; i++) {
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs RGE_REPORT((rgep, "rge_mii_get16(0x%x) fail, val = %x", mii, val32));
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs return ((uint16_t)~0u);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsvoid rge_mii_put16(rge_t *rgep, uintptr_t mii, uint16_t data);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Waiting for PHY writing OK
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs for (i = 0; i < PHY_RESET_LOOP; i++) {
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Atomically shift a 32-bit word left, returning
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * the value it had *before* the shift was applied
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic uint32_t rge_atomic_shl32(uint32_t *sp, uint_t count);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs#pragma inline(rge_mii_put16)
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs /* ATOMICALLY */
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * PHY operation routines
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs for (i = 0; i < 32; ++i) {
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs "0x%04x %04x %04x %04x %04x %04x %04x %04x",
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs#endif /* RGE_DEBUGGING */
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Basic low-level function to probe for a PHY
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Returns TRUE if the PHY responds with valid data, FALSE otherwise
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Read the MII_STATUS register twice, in
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * order to clear any sticky bits (but they should
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * have been cleared by the RESET, I think).
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Now check the value read; it should have at least one bit set
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * (for the device capabilities) and at least one clear (one of
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * the error bits). So if we see all 0s or all 1s, there's a
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * problem. In particular, rge_mii_get16() returns all 1s if
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * communications fails ...
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs case 0x0000:
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs case 0xffff:
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * RTL8169S/8110S PHY has the "PCS bug". Need reset PHY
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * every 15 seconds whin link down & advertise is 1000.
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Basic low-level function to reset the PHY.
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Doesn't incorporate any special-case workarounds.
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Returns TRUE on success, FALSE if the RESET bit doesn't clear
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Set the PHY RESET bit, then wait up to 5 ms for it to self-clear
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs rge_mii_put16(rgep, MII_CONTROL, control | MII_CONTROL_RESET);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs RGE_REPORT((rgep, "rge_phy_reset: FAILED, control now 0x%x", control));
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Synchronise the PHY's speed/duplex/autonegotiation capabilities
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * and advertisements with the required settings as specified by the various
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * param_* variables that can be poked via the NDD interface.
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * We always reset the PHY and reprogram *all* the relevant registers,
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * not just those changed. This should cause the link to go down, and then
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * back up again once the link is stable and autonegotiation (if enabled)
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * is complete. We should get a link state change interrupt somewhere along
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * the way ...
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * NOTE: <genlock> must already be held by the caller
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs "pause %d asym_pause %d "
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs "1000fdx %d 1000hdx %d "
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs "100fdx %d 100hdx %d "
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs "10fdx %d 10hdx %d ",
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * PHY settings are normally based on the param_* variables,
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * but if any loopback mode is in effect, that takes precedence.
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * RGE supports MAC-internal loopback, PHY-internal loopback,
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * and External loopback at a variety of speeds (with a special
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * cable). In all cases, autoneg is turned OFF, full-duplex
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * is turned ON, and the speed/mastership is forced.
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs "pause %d asym_pause %d "
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs "1000fdx %d 1000hdx %d "
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs "100fdx %d 100hdx %d "
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs "10fdx %d 10hdx %d ",
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * We should have at least one technology capability set;
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * if not, we select a default of 1000Mb/s full-duplex
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Now transform the adv_* variables into the proper settings
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * of the PHY registers ...
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * If autonegotiation is (now) enabled, we want to trigger
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * a new autonegotiation cycle once the PHY has been
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * programmed with the capabilities to be advertised.
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * RTL8169/8110 doesn't support 1000Mb/s half-duplex.
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Chipset limitation: need set other capabilities to true
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Munge in any other fixed bits we require ...
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Restart the PHY and write the new values. Note the
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * time, so that we can say whether subsequent link state
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * changes can be attributed to our reprogramming the PHY
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Below phy config steps are copied from the Programming Guide
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * (there's no detail comments for these steps.)
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs rge_mii_put16(rgep, PHY_ANAR_REG, val16 & (~ANAR_ASY_PAUSE));
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs rge_mii_put16(rgep, PHY_ANAR_REG, val16 | ANAR_ASY_PAUSE);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs rge_mii_put16(rgep, PHY_ANAR_REG, val16 & (~ANAR_ASY_PAUSE));
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs rge_mii_put16(rgep, PHY_ANAR_REG, (val16 & 0x0fff) | 0x7000);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs rge_mii_put16(rgep, PHY_ANAR_REG, val16 | ANAR_ASY_PAUSE);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs rge_mii_put16(rgep, PHY_ANAR_REG, val16 & (~ANAR_ASY_PAUSE));
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs rge_mii_put16(rgep, PHY_ANAR_REG, (val16 & 0x0fff) | 0xa000);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs rge_mii_put16(rgep, PHY_ANAR_REG, val16 | ANAR_ASY_PAUSE);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs rge_mii_put16(rgep, PHY_ANAR_REG, val16 & (~ANAR_ASY_PAUSE));
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs rge_mii_put16(rgep, PHY_ANAR_REG, (val16 & 0x0fff) | 0xb000);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs rge_mii_put16(rgep, PHY_ANAR_REG, val16 | ANAR_ASY_PAUSE);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs rge_mii_put16(rgep, PHY_ANAR_REG, val16 & (~ANAR_ASY_PAUSE));
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs rge_mii_put16(rgep, PHY_ANAR_REG, (val16 & 0x0fff) | 0xf000);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs rge_mii_put16(rgep, PHY_ANAR_REG, val16 | ANAR_ASY_PAUSE);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs rge_mii_put16(rgep, PHY_ANAR_REG, val16 & (~ANAR_ASY_PAUSE));
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs /* set pci latency timer */
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs if (chip->mac_ver == MAC_VER_NS || chip->mac_ver == MAC_VER_SD)
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs pci_config_put8(rgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 0x40);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Perform first-stage chip (re-)initialisation, using only config-space
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * accesses:
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * + Read the vendor/device/revision/subsystem/cache-line-size registers,
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * returning the data in the structure pointed to by <idp>.
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * + Enable Memory Space accesses.
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * + Enable Bus Mastering according.
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Save PCI cache line size and subsystem vendor ID
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs cidp->revision = pci_config_get8(handle, PCI_CONF_REVID);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Turn on Master Enable (DMA) and IO Enable bits.
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Enable PCI Memory Space accesses
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs RGE_DEBUG(("rge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x",
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs RGE_DEBUG(("rge_chip_cfg_init: clsize %d latency %d command 0x%x",
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Chip should be in STOP state
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Disable interrupt
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Clear pended interrupt
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Reset chip
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Wait for reset success
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs for (i = 0; i < CHIP_RESET_LOOP; i++) {
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs return (0);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs return (-1);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Config MII register
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Enable Rx checksum offload.
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Then for vlan support, we must enable receive vlan de-tagging.
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Otherwise, there'll be checksum error.
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs rge_reg_set16(rgep, CPLUS_COMMAND_REG, RX_CKSM_OFFLOAD | RX_VLAN_DETAG);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Suggested setting from Realtek
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Start transmit/receive before set tx/rx configuration register
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Set dump tally counter register
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Change to config register write enable mode
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Set Tx/Rx maximum packet size
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs rge_reg_put8(rgep, TX_MAX_PKTSIZE_REG, TX_PKTSIZE_JUMBO);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs rge_reg_put16(rgep, RX_MAX_PKTSIZE_REG, RX_PKTSIZE_JUMBO);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Set receive configuration register
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs rge_reg_put32(rgep, RX_CONFIG_REG, val32 | rgep->chipid.rxconfig);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Set transmit configuration register
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs rge_reg_put32(rgep, TX_CONFIG_REG, val32 | rgep->chipid.txconfig);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Initialize PHY registers
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Set Tx/Rx descriptor register
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Suggested setting from Realtek
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Return to normal network/host communication mode
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Set multicast register
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs rge_reg_put32(rgep, MULTICAST_0_REG, rgep->mcast_hash[0]);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs rge_reg_put32(rgep, MULTICAST_4_REG, rgep->mcast_hash[1]);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Mask and clear all Interrupt
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Msic register setting:
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * -- Missed packet counter: clear it
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * -- TimerInt Register
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * -- Timer count register
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * rge_chip_start() -- start the chip transmitting and/or receiving,
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * including enabling interrupts
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Clear statistics
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Enable interrupt
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * All done!
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * rge_chip_stop() -- stop board receiving
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Disable interrupt
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Clear pended interrupt
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Stop the board and disable transmit/receive
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * rge_get_mac_addr() -- get the MAC address on NIC
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs#pragma inline(rge_get_mac_addr)
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Read first 4-byte of mac address
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Read last 2-byte of mac address
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs#pragma inline(rge_set_mac_addr)
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Change to config register write enable mode
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Get first 4 bytes of mac address
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Set first 4 bytes of mac address
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Get last 2 bytes of mac address
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Set last 2 bytes of mac address
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Return to normal network/host communication mode
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs#pragma inline(rge_set_multi_addr)
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs#pragma inline(rge_set_promisc)
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * rge_chip_sync() -- program the chip with the unicast MAC address,
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * the multicast hash table, the required level of promiscuity, and
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * the current loopback mode ...
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs switch (todo) {
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs /* Reprogram the unicast MAC address(es) ... */
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs /* Reprogram the hashed multicast address table ... */
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs /* Set or clear the PROMISCUOUS mode bit */
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsvoid rge_chip_blank(void *arg, time_t ticks, uint_t count);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs rge_reg_set8(rgep, TX_RINGS_POLL_REG, NORMAL_TX_RING_POLL);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs int i = 0;
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs while (rge_reg_get32(rgep, DUMP_COUNTER_REG_0) & DUMP_START) {
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Start H/W statistics dump for RTL8169 chip
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * ========== Hardware interrupt handler ==========
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs#define RGE_DBG RGE_DBG_INT /* debug flag for this code */
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs#pragma inline(rge_wake_factotum)
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * rge_intr() -- handle chip interrupts
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Was this interrupt caused by our device...
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs /* indicate it wasn't our interrupt */
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Clear interrupt
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Cable link change interrupt
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Receive interrupt
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs return (DDI_INTR_CLAIMED); /* indicate it was our interrupt */
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * ========== Factotum, implemented as a softint handler ==========
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs#define RGE_DBG RGE_DBG_FACT /* debug flag for this code */
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs const char *msg;
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Link change. We have to decide whether to write a message
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * on the console or only in the log. If the PHY has
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * been reprogrammed (at user request) "recently", then
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * the message only goes in the log. Otherwise it's an
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * "unexpected" event, and it goes on the console as well.
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs logfn = (msg == NULL || *msg == '\0') ? rge_notice : rge_log;
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs "link up %sbps %s_Duplex%s",
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Factotum routine to check for Tx stall, using the 'watchdog' counter
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Specific check for Tx stall ...
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * The 'watchdog' counter is incremented whenever a packet
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * is queued, reset to 1 when some (but not all) buffers
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * are reclaimed, reset to 0 (disabled) when all buffers
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * are reclaimed, and shifted left here. If it exceeds the
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * threshold value, the chip is assumed to have stalled and
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * is put into the ERROR state. The factotum will then reset
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * it on the next pass.
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * All of which should ensure that we don't get into a state
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * where packets are left pending indefinitely!
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs RGE_REPORT((rgep, "Tx stall detected, watchdog code 0x%x", dogval));
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * The factotum is woken up when there's something to do that we'd rather
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * not do from inside a hardware interrupt handler or high-level cyclic.
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Its two main tasks are:
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * reset & restart the chip after an error
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * check the link status whenever necessary
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Fault detected, time to reset ...
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * If an error is detected, stop the chip now, marking it as
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * faulty, so that it will be reset next time through ...
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * If the link state changed, tell the world about it.
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Note: can't do this while still holding the mutex.
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * High-level cyclic handler
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * This routine schedules a (low-level) softint callback to the
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * factotum, and prods the chip to update the status block (which
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * will cause a hardware interrupt when complete).
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * ========== Ioctl subfunctions ==========
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs#define RGE_DBG RGE_DBG_PPIO /* debug flag for this code */
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void rge_chip_peek_cfg(rge_t *rgep, rge_peekpoke_t *ppd);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void rge_chip_poke_cfg(rge_t *rgep, rge_peekpoke_t *ppd);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void rge_chip_peek_reg(rge_t *rgep, rge_peekpoke_t *ppd);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void rge_chip_poke_reg(rge_t *rgep, rge_peekpoke_t *ppd);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void rge_chip_peek_mii(rge_t *rgep, rge_peekpoke_t *ppd);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs ppd->pp_acc_data = rge_mii_get16(rgep, ppd->pp_acc_offset/2);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void rge_chip_poke_mii(rge_t *rgep, rge_peekpoke_t *ppd);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs rge_mii_put16(rgep, ppd->pp_acc_offset/2, ppd->pp_acc_data);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void rge_chip_peek_mem(rge_t *rgep, rge_peekpoke_t *ppd);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs RGE_DEBUG(("rge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p",
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void rge_chip_poke_mem(rge_t *rgep, rge_peekpoke_t *ppd);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic void
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs RGE_DEBUG(("rge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p",
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic enum ioc_reply rge_pp_ioctl(rge_t *rgep, int cmd, mblk_t *mp,
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsrge_pp_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp)
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs switch (cmd) {
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs /* NOTREACHED */
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Validate format of ioctl
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Validate request parameters
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Config space
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Memory-mapped I/O space
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * PHY's MII registers
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * NB: all PHY registers are two bytes, but the
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * addresses increment in ones (word addressing).
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * So we scale the address here, then undo the
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * transformation inside the peek/poke functions.
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * RGE data structure!
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Various DMA_AREAs
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * All OK - go do it!
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic enum ioc_reply rge_diag_ioctl(rge_t *rgep, int cmd, mblk_t *mp,
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsrge_diag_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp)
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs switch (cmd) {
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs /* NOTREACHED */
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs rge_error(rgep, "rge_diag_ioctl: invalid cmd 0x%x", cmd);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Currently a no-op
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Reset and reinitialise the 570x hardware
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs /* NOTREACHED */
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs#endif /* RGE_DEBUGGING || RGE_DO_PPIO */
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsstatic enum ioc_reply rge_mii_ioctl(rge_t *rgep, int cmd, mblk_t *mp,
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsrge_mii_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp)
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Validate format of ioctl
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs * Validate request parameters ...
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs switch (cmd) {
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs /* NOTREACHED */
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs /* NOTREACHED */
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsenum ioc_reply rge_chip_ioctl(rge_t *rgep, queue_t *wq, mblk_t *mp,
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gsrge_chip_ioctl(rge_t *rgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp)
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs switch (cmd) {
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs /* NOTREACHED */
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs rge_error(rgep, "rge_chip_ioctl: invalid cmd 0x%x", cmd);
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs#endif /* RGE_DEBUGGING || RGE_DO_PPIO */
c7fd2ed091e4e4beb47e1da3a6197a2c38f29c02gs /* NOTREACHED */